ixdp425_pci.c revision 1.4
1 /* $NetBSD: ixdp425_pci.c,v 1.4 2003/10/11 03:53:52 ichiro Exp $ */ 2 #define PCI_DEBUG 3 /* 4 * Copyright (c) 2003 5 * Ichiro FUKUHARA <ichiro (at) ichiro.org>. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Ichiro FUKUHARA. 19 * 4. The name of the company nor the name of the author may be used to 20 * endorse or promote products derived from this software without specific 21 * prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY ICHIRO FUKUHARA ``AS IS'' AND ANY EXPRESS OR 24 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 25 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26 * IN NO EVENT SHALL ICHIRO FUKUHARA OR THE VOICES IN HIS HEAD BE LIABLE FOR 27 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 28 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 29 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 30 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 31 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 32 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 33 * SUCH DAMAGE. 34 */ 35 36 #include <sys/cdefs.h> 37 __KERNEL_RCSID(0, "$NetBSD: ixdp425_pci.c,v 1.4 2003/10/11 03:53:52 ichiro Exp $"); 38 39 /* 40 * IXDP425 PCI interrupt support. 41 */ 42 43 #include <sys/param.h> 44 #include <sys/systm.h> 45 #include <sys/device.h> 46 47 #include <machine/autoconf.h> 48 #include <machine/bus.h> 49 50 #include <evbarm/ixdp425/ixdp425reg.h> 51 #include <evbarm/ixdp425/ixdp425var.h> 52 53 #include <arm/xscale/ixp425reg.h> 54 #include <arm/xscale/ixp425var.h> 55 56 #include <dev/pci/pcidevs.h> 57 #include <dev/pci/ppbreg.h> 58 59 static int ixdp425_pci_intr_map(struct pci_attach_args *, pci_intr_handle_t *); 60 static const char *ixdp425_pci_intr_string(void *, pci_intr_handle_t); 61 static const struct evcnt *ixdp425_pci_intr_evcnt(void *, pci_intr_handle_t); 62 static void *ixdp425_pci_intr_establish(void *, pci_intr_handle_t, int, 63 int (*func)(void *), void *); 64 static void ixdp425_pci_intr_disestablish(void *, void *); 65 66 void 67 ixp425_md_pci_init(struct ixp425_softc *sc) 68 { 69 pci_chipset_tag_t pc = &sc->ia_pci_chipset; 70 u_int32_t reg; 71 72 /* 73 * PCI initialization 74 */ 75 pc->pc_intr_v = sc; 76 pc->pc_intr_map = ixdp425_pci_intr_map; 77 pc->pc_intr_string = ixdp425_pci_intr_string; 78 pc->pc_intr_evcnt = ixdp425_pci_intr_evcnt; 79 pc->pc_intr_establish = ixdp425_pci_intr_establish; 80 pc->pc_intr_disestablish = ixdp425_pci_intr_disestablish; 81 82 /* PCI Reset Assert */ 83 reg = GPIO_CONF_READ_4(sc, IXP425_GPIO_GPOUTR); 84 GPIO_CONF_WRITE_4(sc, IXP425_GPIO_GPOUTR, reg & ~(1U << GPIO_PCI_RESET)); 85 86 /* PCI Clock Disable */ 87 reg = GPIO_CONF_READ_4(sc, IXP425_GPIO_GPCLKR); 88 GPIO_CONF_WRITE_4(sc, IXP425_GPIO_GPCLKR, reg & ~GPCLKR_MUX14); 89 90 /* 91 * set GPIO Direction 92 * Output: PCI_CLK, PCI_RESET 93 * Input: PCI_INTA, PCI_INTB, PCI_INTC, PCI_INTD 94 */ 95 reg = GPIO_CONF_READ_4(sc, IXP425_GPIO_GPOER); 96 reg &= ~(1U << GPIO_PCI_CLK); 97 reg &= ~(1U << GPIO_PCI_RESET); 98 reg |= ((1U << GPIO_PCI_INTA) | (1U << GPIO_PCI_INTB) | 99 (1U << GPIO_PCI_INTC) | (1U << GPIO_PCI_INTD)); 100 GPIO_CONF_WRITE_4(sc, IXP425_GPIO_GPOER, reg); 101 102 /* clear ISR */ 103 GPIO_CONF_WRITE_4(sc, IXP425_GPIO_GPISR, 104 (1U << GPIO_PCI_INTA) | (1U << GPIO_PCI_INTB) | 105 (1U << GPIO_PCI_INTC) | (1U << GPIO_PCI_INTD)); 106 107 /* wait 1ms to satisfy "minimum reset assertion time" of the PCI spec */ 108 DELAY(1000); 109 reg = GPIO_CONF_READ_4(sc, IXP425_GPIO_GPCLKR); 110 GPIO_CONF_WRITE_4(sc, IXP425_GPIO_GPCLKR, reg | 111 (0xf << GPCLKR_CLK0DC_SHIFT) | (0xf << GPCLKR_CLK0TC_SHIFT)); 112 113 /* PCI Clock Enable */ 114 reg = GPIO_CONF_READ_4(sc, IXP425_GPIO_GPCLKR); 115 GPIO_CONF_WRITE_4(sc, IXP425_GPIO_GPCLKR, reg | GPCLKR_MUX14); 116 117 /* 118 * wait 100us to satisfy "minimum reset assertion time from clock stable 119 * requirement of the PCI spec 120 */ 121 DELAY(100); 122 /* PCI Reset deassert */ 123 reg = GPIO_CONF_READ_4(sc, IXP425_GPIO_GPOUTR); 124 GPIO_CONF_WRITE_4(sc, IXP425_GPIO_GPOUTR, reg | (1U << GPIO_PCI_RESET)); 125 126 /* 127 * AHB->PCI address translation 128 * PCI Memory Map allocation in 0x48000000 (64MB) 129 * see. IXP425_PCI_MEM_HWBASE 130 */ 131 PCI_CSR_WRITE_4(sc, PCI_PCIMEMBASE, 0x48494a4b); 132 133 /* 134 * PCI->AHB address translation 135 * begin at the physical memory start + OFFSET 136 */ 137 #define AHB_OFFSET 0x10000000UL 138 PCI_CSR_WRITE_4(sc, PCI_AHBMEMBASE, 139 (AHB_OFFSET & 0xFF000000) + 140 ((AHB_OFFSET & 0xFF000000) >> 8) + 141 ((AHB_OFFSET & 0xFF000000) >> 16) + 142 ((AHB_OFFSET & 0xFF000000) >> 24) + 143 0x00010203); 144 145 /* write Mapping registers PCI Configuration Registers */ 146 /* Base Address 0 - 3 */ 147 ixp425_pci_conf_reg_write(sc, PCI_MAPREG_BAR0, AHB_OFFSET + 0x00000000); 148 ixp425_pci_conf_reg_write(sc, PCI_MAPREG_BAR1, AHB_OFFSET + 0x01000000); 149 ixp425_pci_conf_reg_write(sc, PCI_MAPREG_BAR2, AHB_OFFSET + 0x02000000); 150 ixp425_pci_conf_reg_write(sc, PCI_MAPREG_BAR3, AHB_OFFSET + 0x03000000); 151 152 /* Base Address 4 */ 153 ixp425_pci_conf_reg_write(sc, PCI_MAPREG_BAR4, 0xffffffff); 154 155 /* Base Address 5 */ 156 ixp425_pci_conf_reg_write(sc, PCI_MAPREG_BAR5, 0x00000000); 157 158 /* assert some PCI errors */ 159 PCI_CSR_WRITE_4(sc, PCI_ISR, ISR_AHBE | ISR_PPE | ISR_PFE | ISR_PSE); 160 161 /* 162 * Set up byte lane swapping between little-endian PCI 163 * and the big-endian AHB bus 164 */ 165 PCI_CSR_WRITE_4(sc, PCI_CSR, CSR_IC | CSR_ABE | CSR_PDS); 166 167 /* 168 * Enable bus mastering and I/O,memory access 169 */ 170 ixp425_pci_conf_reg_write(sc, PCI_COMMAND_STATUS_REG, 171 PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE | 172 PCI_COMMAND_MASTER_ENABLE); 173 } 174 175 void 176 ixp425_md_pci_conf_interrupt(pci_chipset_tag_t pc, int bus, int dev, int pin, 177 int swiz, int *ilinep) 178 { 179 180 if (bus == 0) 181 *ilinep = ((swiz + (dev + pin - 1)) & 3); 182 else 183 panic("ixp425_md_pci_conf_interrupt: unsupported bus number"); 184 } 185 186 #define IXP425_MAX_DEV 4 187 #define IXP425_MAX_LINE 4 188 static int 189 ixdp425_pci_intr_map(struct pci_attach_args *pa, pci_intr_handle_t *ihp) 190 { 191 static int ixp425_pci_table[IXP425_MAX_DEV][IXP425_MAX_LINE] = 192 { 193 {PCI_INT_A, PCI_INT_B, PCI_INT_C, PCI_INT_D}, 194 {PCI_INT_B, PCI_INT_C, PCI_INT_D, PCI_INT_A}, 195 {PCI_INT_C, PCI_INT_D, PCI_INT_A, PCI_INT_B}, 196 {PCI_INT_D, PCI_INT_A, PCI_INT_B, PCI_INT_C}, 197 }; 198 199 int pin = pa->pa_intrpin; 200 int dev = pa->pa_device; 201 202 #ifdef PCI_DEBUG 203 void *v = pa->pa_pc; 204 int line = pa->pa_intrline; 205 pcitag_t intrtag = pa->pa_intrtag; 206 207 printf("ixdp425_pci_intr_map: v=%p, tag=%08lx intrpin=%d line=%d dev=%d\n", 208 v, intrtag, pin, line, dev); 209 #endif 210 211 if (pin >= 1 && pin <= IXP425_MAX_LINE && 212 dev >= 1 && dev <= IXP425_MAX_DEV) { 213 *ihp = ixp425_pci_table[dev - 1][pin - 1]; 214 return (0); 215 } else { 216 printf("ixdp425_pci_intr_map: no mapping for %d/%d/%d\n", 217 pa->pa_bus, pa->pa_device, pa->pa_function); 218 return (1); 219 } 220 } 221 222 static const char * 223 ixdp425_pci_intr_string(void *v, pci_intr_handle_t ih) 224 { 225 static char irqstr[IRQNAMESIZE]; 226 227 sprintf(irqstr, "ixp425 irq %ld", ih); 228 return (irqstr); 229 } 230 231 static const struct evcnt * 232 ixdp425_pci_intr_evcnt(void *v, pci_intr_handle_t ih) 233 { 234 return (NULL); 235 } 236 237 static void * 238 ixdp425_pci_intr_establish(void *v, pci_intr_handle_t ih, int ipl, 239 int (*func)(void *), void *arg) 240 { 241 #ifdef PCI_DEBUG 242 printf("ixdp425_pci_intr_establish(v=%p, irq=%d, ipl=%d, func=%p, arg=%p)\n", 243 v, (int) ih, ipl, func, arg); 244 #endif 245 246 return (ixp425_intr_establish(ih, ipl, func, arg)); 247 } 248 249 static void 250 ixdp425_pci_intr_disestablish(void *v, void *cookie) 251 { 252 #ifdef PCI_DEBUG 253 printf("ixdp425_pci_intr_disestablish(v=%p, cookie=%p)\n", 254 v, cookie); 255 #endif 256 257 ixp425_intr_disestablish(cookie); 258 } 259
Indexes created Fri Sep 26 20:09:58 GMT 2025