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ixm1200_machdep.c revision 1.14
      1  1.14  thorpej /*	$NetBSD: ixm1200_machdep.c,v 1.14 2003/04/02 03:49:26 thorpej Exp $ */
      2   1.1   ichiro #undef DEBUG_BEFOREMMU
      3   1.1   ichiro /*
      4  1.12      igy  * Copyright (c) 2002, 2003
      5   1.1   ichiro  *	Ichiro FUKUHARA <ichiro (at) ichiro.org>.
      6   1.1   ichiro  * All rights reserved.
      7   1.1   ichiro  *
      8   1.1   ichiro  * Redistribution and use in source and binary forms, with or without
      9   1.1   ichiro  * modification, are permitted provided that the following conditions
     10   1.1   ichiro  * are met:
     11   1.1   ichiro  * 1. Redistributions of source code must retain the above copyright
     12   1.1   ichiro  *    notice, this list of conditions and the following disclaimer.
     13   1.1   ichiro  * 2. Redistributions in binary form must reproduce the above copyright
     14   1.1   ichiro  *    notice, this list of conditions and the following disclaimer in the
     15   1.1   ichiro  *    documentation and/or other materials provided with the distribution.
     16   1.1   ichiro  * 3. All advertising materials mentioning features or use of this software
     17   1.1   ichiro  *    must display the following acknowledgement:
     18   1.1   ichiro  *	This product includes software developed by Ichiro FUKUHARA.
     19   1.1   ichiro  * 4. The name of the company nor the name of the author may be used to
     20   1.1   ichiro  *    endorse or promote products derived from this software without specific
     21   1.1   ichiro  *    prior written permission.
     22   1.1   ichiro  *
     23   1.1   ichiro  * THIS SOFTWARE IS PROVIDED BY ICHIRO FUKUHARA ``AS IS'' AND ANY EXPRESS OR
     24   1.1   ichiro  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
     25   1.1   ichiro  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
     26   1.1   ichiro  * IN NO EVENT SHALL ICHIRO FUKUHARA OR THE VOICES IN HIS HEAD BE LIABLE FOR
     27   1.1   ichiro  * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
     28   1.1   ichiro  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
     29   1.1   ichiro  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
     30   1.1   ichiro  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
     31   1.1   ichiro  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
     32   1.1   ichiro  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
     33   1.1   ichiro  * SUCH DAMAGE.
     34   1.1   ichiro  */
     35   1.1   ichiro /*
     36   1.1   ichiro  * Copyright (c) 1997,1998 Mark Brinicombe.
     37   1.1   ichiro  * Copyright (c) 1997,1998 Causality Limited.
     38   1.1   ichiro  * All rights reserved.
     39   1.1   ichiro  *
     40   1.1   ichiro  * Redistribution and use in source and binary forms, with or without
     41   1.1   ichiro  * modification, are permitted provided that the following conditions
     42   1.1   ichiro  * are met:
     43   1.1   ichiro  * 1. Redistributions of source code must retain the above copyright
     44   1.1   ichiro  *    notice, this list of conditions and the following disclaimer.
     45   1.1   ichiro  * 2. Redistributions in binary form must reproduce the above copyright
     46   1.1   ichiro  *    notice, this list of conditions and the following disclaimer in the
     47   1.1   ichiro  *    documentation and/or other materials provided with the distribution.
     48   1.1   ichiro  * 3. All advertising materials mentioning features or use of this software
     49   1.1   ichiro  *    must display the following acknowledgement:
     50   1.1   ichiro  *      This product includes software developed by Mark Brinicombe
     51   1.1   ichiro  *      for the NetBSD Project.
     52   1.1   ichiro  * 4. The name of the company nor the name of the author may be used to
     53   1.1   ichiro  *    endorse or promote products derived from this software without specific
     54   1.1   ichiro  *    prior written permission.
     55   1.1   ichiro  *
     56   1.1   ichiro  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
     57   1.1   ichiro  * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
     58   1.1   ichiro  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
     59   1.1   ichiro  * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
     60   1.1   ichiro  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
     61   1.1   ichiro  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
     62   1.1   ichiro  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
     63   1.1   ichiro  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
     64   1.1   ichiro  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
     65   1.1   ichiro  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
     66   1.1   ichiro  * SUCH DAMAGE.
     67   1.1   ichiro  */
     68  1.13      igy 
     69  1.13      igy #include <sys/cdefs.h>
     70  1.14  thorpej __KERNEL_RCSID(0, "$NetBSD: ixm1200_machdep.c,v 1.14 2003/04/02 03:49:26 thorpej Exp $");
     71   1.1   ichiro 
     72   1.1   ichiro #include "opt_ddb.h"
     73   1.1   ichiro #include "opt_pmap_debug.h"
     74   1.1   ichiro 
     75   1.1   ichiro #include <sys/param.h>
     76   1.1   ichiro #include <sys/device.h>
     77   1.1   ichiro #include <sys/systm.h>
     78   1.1   ichiro #include <sys/kernel.h>
     79   1.1   ichiro #include <sys/exec.h>
     80   1.1   ichiro #include <sys/proc.h>
     81   1.1   ichiro #include <sys/msgbuf.h>
     82   1.1   ichiro #include <sys/reboot.h>
     83   1.1   ichiro #include <sys/termios.h>
     84   1.1   ichiro 
     85  1.14  thorpej #include <uvm/uvm_extern.h>
     86  1.14  thorpej 
     87   1.1   ichiro #include <dev/cons.h>
     88   1.1   ichiro 
     89   1.1   ichiro #ifdef DDB
     90   1.1   ichiro #include <machine/db_machdep.h>
     91   1.1   ichiro #include <ddb/db_sym.h>
     92   1.1   ichiro #include <ddb/db_extern.h>
     93   1.1   ichiro #ifndef DB_ELFSIZE
     94   1.1   ichiro #error Must define DB_ELFSIZE!
     95   1.1   ichiro #endif
     96   1.1   ichiro #define ELFSIZE	DB_ELFSIZE
     97   1.1   ichiro #include <sys/exec_elf.h>
     98   1.1   ichiro #endif
     99   1.1   ichiro 
    100   1.1   ichiro #include <machine/bootconfig.h>
    101   1.1   ichiro #include <machine/bus.h>
    102   1.1   ichiro #include <machine/cpu.h>
    103   1.1   ichiro #include <machine/frame.h>
    104   1.1   ichiro #include <arm/undefined.h>
    105   1.1   ichiro 
    106   1.1   ichiro #include <arm/arm32/machdep.h>
    107   1.1   ichiro 
    108   1.1   ichiro #include <arm/ixp12x0/ixp12x0reg.h>
    109   1.1   ichiro #include <arm/ixp12x0/ixp12x0var.h>
    110   1.1   ichiro #include <arm/ixp12x0/ixp12x0_comreg.h>
    111   1.1   ichiro #include <arm/ixp12x0/ixp12x0_comvar.h>
    112   1.1   ichiro #include <arm/ixp12x0/ixp12x0_pcireg.h>
    113   1.1   ichiro 
    114   1.1   ichiro #include <evbarm/ixm1200/ixm1200reg.h>
    115   1.1   ichiro #include <evbarm/ixm1200/ixm1200var.h>
    116   1.1   ichiro 
    117   1.1   ichiro #include "opt_ipkdb.h"
    118   1.1   ichiro 
    119   1.1   ichiro /* XXX for consinit related hacks */
    120   1.1   ichiro #include <sys/conf.h>
    121   1.1   ichiro 
    122   1.1   ichiro void ixp12x0_reset(void) __attribute__((noreturn));
    123   1.1   ichiro 
    124   1.1   ichiro /*
    125   1.1   ichiro  * Address to call from cpu_reset() to reset the machine.
    126   1.1   ichiro  * This is machine architecture dependant as it varies depending
    127   1.1   ichiro  * on where the ROM appears when you turn the MMU off.
    128   1.1   ichiro  */
    129   1.1   ichiro 
    130   1.1   ichiro u_int cpu_reset_address = (u_int) ixp12x0_reset;
    131   1.1   ichiro 
    132   1.1   ichiro /*
    133   1.1   ichiro  * Define the default console speed for the board.
    134   1.1   ichiro  */
    135   1.1   ichiro #ifndef CONMODE
    136   1.1   ichiro #define CONMODE ((TTYDEF_CFLAG & ~(CSIZE | CSTOPB)) | CS8) /* 8N1 */
    137   1.1   ichiro #endif
    138   1.1   ichiro #ifndef CONSPEED
    139   1.1   ichiro #define CONSPEED B38400
    140   1.1   ichiro #endif
    141   1.1   ichiro #ifndef CONADDR
    142   1.1   ichiro #define CONADDR IXPCOM_UART_BASE
    143   1.1   ichiro #endif
    144   1.1   ichiro 
    145   1.1   ichiro cons_decl(com);
    146   1.1   ichiro cons_decl(ixpcom);
    147   1.1   ichiro 
    148   1.1   ichiro struct consdev constab[] = {
    149   1.1   ichiro #if (NIXPCOM > 0)
    150   1.1   ichiro 	cons_init(ixpcom),
    151   1.1   ichiro #endif
    152   1.1   ichiro 	{ 0 },
    153   1.1   ichiro };
    154   1.1   ichiro 
    155   1.1   ichiro /* Define various stack sizes in pages */
    156   1.1   ichiro #define IRQ_STACK_SIZE  1
    157   1.1   ichiro #define ABT_STACK_SIZE  1
    158   1.1   ichiro #ifdef IPKDB
    159   1.1   ichiro #define UND_STACK_SIZE  2
    160   1.1   ichiro #else
    161   1.1   ichiro #define UND_STACK_SIZE  1
    162   1.1   ichiro #endif
    163   1.1   ichiro 
    164   1.1   ichiro BootConfig bootconfig;          /* Boot config storage */
    165   1.1   ichiro char *boot_args = NULL;
    166   1.1   ichiro char *boot_file = NULL;
    167   1.1   ichiro 
    168   1.1   ichiro vm_offset_t physical_start;
    169   1.1   ichiro vm_offset_t physical_freestart;
    170   1.1   ichiro vm_offset_t physical_freeend;
    171   1.1   ichiro vm_offset_t physical_end;
    172   1.1   ichiro u_int free_pages;
    173   1.1   ichiro vm_offset_t pagetables_start;
    174   1.1   ichiro int physmem = 0;
    175   1.1   ichiro 
    176   1.1   ichiro /*int debug_flags;*/
    177   1.1   ichiro #ifndef PMAP_STATIC_L1S
    178   1.1   ichiro int max_processes = 64;                 /* Default number */
    179   1.1   ichiro #endif  /* !PMAP_STATIC_L1S */
    180   1.1   ichiro 
    181   1.1   ichiro /* Physical and virtual addresses for some global pages */
    182   1.1   ichiro pv_addr_t systempage;
    183   1.1   ichiro pv_addr_t irqstack;
    184   1.1   ichiro pv_addr_t undstack;
    185   1.1   ichiro pv_addr_t abtstack;
    186   1.1   ichiro pv_addr_t kernelstack;
    187   1.1   ichiro 
    188   1.1   ichiro vm_offset_t msgbufphys;
    189   1.1   ichiro 
    190   1.1   ichiro extern u_int data_abort_handler_address;
    191   1.1   ichiro extern u_int prefetch_abort_handler_address;
    192   1.1   ichiro extern u_int undefined_handler_address;
    193   1.1   ichiro extern int end;
    194   1.1   ichiro 
    195   1.1   ichiro #ifdef PMAP_DEBUG
    196   1.1   ichiro extern int pmap_debug_level;
    197   1.1   ichiro #endif  /* PMAP_DEBUG */
    198   1.1   ichiro 
    199   1.1   ichiro #define KERNEL_PT_SYS		0	/* Page table for mapping proc0 zero page */
    200   1.1   ichiro #define KERNEL_PT_KERNEL	1	/* Page table for mapping kernel */
    201   1.1   ichiro #define KERNEL_PT_KERNEL_NUM	2
    202   1.1   ichiro #define KERNEL_PT_IO		(KERNEL_PT_KERNEL + KERNEL_PT_KERNEL_NUM)
    203   1.1   ichiro 					/* Page table for mapping IO */
    204   1.1   ichiro #define KERNEL_PT_VMDATA	(KERNEL_PT_IO + 1)
    205   1.1   ichiro 					/* Page tables for mapping kernel VM */
    206   1.1   ichiro #define KERNEL_PT_VMDATA_NUM	4	/* start with 16MB of KVM */
    207   1.1   ichiro #define NUM_KERNEL_PTS		(KERNEL_PT_VMDATA + KERNEL_PT_VMDATA_NUM)
    208   1.1   ichiro 
    209   1.1   ichiro pv_addr_t kernel_pt_table[NUM_KERNEL_PTS];
    210   1.1   ichiro 
    211   1.1   ichiro struct user *proc0paddr;
    212   1.1   ichiro 
    213   1.1   ichiro #ifdef CPU_IXP12X0
    214   1.1   ichiro #define CPU_IXP12X0_CACHE_CLEAN_SIZE (0x4000 * 2)
    215   1.1   ichiro extern unsigned int ixp12x0_cache_clean_addr;
    216   1.1   ichiro extern unsigned int ixp12x0_cache_clean_size;
    217   1.1   ichiro static vaddr_t ixp12x0_cc_base;
    218   1.1   ichiro #endif  /* CPU_IXP12X0 */
    219   1.1   ichiro 
    220   1.1   ichiro /* Prototypes */
    221   1.1   ichiro 
    222   1.1   ichiro void consinit		__P((void));
    223   1.1   ichiro u_int cpu_get_control	__P((void));
    224   1.1   ichiro 
    225   1.1   ichiro void ixdp_ixp12x0_cc_setup(void);
    226   1.1   ichiro 
    227   1.1   ichiro #ifdef DEBUG_BEFOREMMU
    228   1.1   ichiro static void fakecninit();
    229   1.1   ichiro #endif
    230   1.1   ichiro 
    231   1.9  thorpej extern int db_trapper(u_int, u_int, trapframe_t *, int);
    232   1.1   ichiro 
    233   1.1   ichiro /*
    234   1.1   ichiro  * void cpu_reboot(int howto, char *bootstr)
    235   1.1   ichiro  *
    236   1.1   ichiro  * Reboots the system
    237   1.1   ichiro  *
    238   1.1   ichiro  * Deal with any syncing, unmounting, dumping and shutdown hooks,
    239   1.1   ichiro  * then reset the CPU.
    240   1.1   ichiro  */
    241   1.1   ichiro 
    242   1.1   ichiro void
    243   1.1   ichiro cpu_reboot(howto, bootstr)
    244   1.1   ichiro 	int howto;
    245   1.1   ichiro 	char *bootstr;
    246   1.1   ichiro {
    247   1.1   ichiro 	/*
    248   1.1   ichiro 	 * If we are still cold then hit the air brakes
    249   1.1   ichiro 	 * and crash to earth fast
    250   1.1   ichiro 	 */
    251   1.1   ichiro 	if (cold) {
    252   1.1   ichiro 		doshutdownhooks();
    253   1.1   ichiro 		printf("Halted while still in the ICE age.\n");
    254   1.1   ichiro 		printf("The operating system has halted.\n");
    255   1.1   ichiro 		printf("Please press any key to reboot.\n\n");
    256   1.1   ichiro 		cngetc();
    257   1.1   ichiro 		printf("rebooting...\n");
    258   1.1   ichiro 		ixp12x0_reset();
    259   1.1   ichiro 	}
    260   1.1   ichiro 
    261   1.1   ichiro 	/* Disable console buffering */
    262   1.1   ichiro 	cnpollc(1);
    263   1.1   ichiro 
    264   1.1   ichiro 	/*
    265   1.1   ichiro 	 * If RB_NOSYNC was not specified sync the discs.
    266   1.1   ichiro 	 * Note: Unless cold is set to 1 here, syslogd will die during the unmount.
    267   1.1   ichiro 	 * It looks like syslogd is getting woken up only to find that it cannot
    268   1.1   ichiro 	 * page part of the binary in as the filesystem has been unmounted.
    269   1.1   ichiro 	 */
    270   1.1   ichiro 	if (!(howto & RB_NOSYNC))
    271   1.1   ichiro 		bootsync();
    272   1.1   ichiro 
    273   1.1   ichiro 	/* Say NO to interrupts */
    274   1.1   ichiro 	splhigh();
    275   1.1   ichiro 
    276   1.1   ichiro 	/* Do a dump if requested. */
    277   1.1   ichiro 	if ((howto & (RB_DUMP | RB_HALT)) == RB_DUMP)
    278   1.1   ichiro 		dumpsys();
    279   1.1   ichiro 
    280   1.1   ichiro 	/* Run any shutdown hooks */
    281   1.1   ichiro 	doshutdownhooks();
    282   1.1   ichiro 
    283   1.1   ichiro 	/* Make sure IRQ's are disabled */
    284   1.1   ichiro 	IRQdisable;
    285   1.1   ichiro 
    286   1.1   ichiro 	if (howto & RB_HALT) {
    287   1.1   ichiro 		printf("The operating system has halted.\n");
    288   1.1   ichiro 		printf("Please press any key to reboot.\n\n");
    289   1.1   ichiro 		cngetc();
    290   1.1   ichiro 	}
    291   1.1   ichiro 
    292   1.1   ichiro 	printf("rebooting...\n");
    293   1.1   ichiro 
    294   1.1   ichiro 	/* all interrupts are disabled */
    295   1.1   ichiro 	disable_interrupts(I32_bit);
    296   1.1   ichiro 
    297   1.1   ichiro 	ixp12x0_reset();
    298   1.1   ichiro 
    299   1.1   ichiro 	/* ...and if that didn't work, just croak. */
    300   1.1   ichiro 	printf("RESET FAILED!\n");
    301   1.1   ichiro 	for (;;);
    302   1.1   ichiro }
    303   1.1   ichiro 
    304   1.1   ichiro /*
    305   1.1   ichiro  * Initial entry point on startup. This gets called before main() is
    306   1.1   ichiro  * entered.
    307   1.1   ichiro  * It should be responsible for setting up everything that must be
    308   1.1   ichiro  * in place when main is called.
    309   1.1   ichiro  * This includes
    310   1.1   ichiro  *   Taking a copy of the boot configuration structure.
    311   1.1   ichiro  *   Initialising the physical console so characters can be printed.
    312   1.1   ichiro  *   Setting up page tables for the kernel
    313   1.1   ichiro  *   Relocating the kernel to the bottom of physical memory
    314   1.1   ichiro  */
    315   1.1   ichiro u_int
    316   1.1   ichiro initarm(void *arg)
    317   1.1   ichiro {
    318   1.1   ichiro         int loop;
    319   1.1   ichiro 	int loop1;
    320   1.1   ichiro 	u_int kerneldatasize, symbolsize;
    321   1.1   ichiro 	vaddr_t l1pagetable;
    322   1.1   ichiro 	vaddr_t freemempos;
    323   1.1   ichiro 	pv_addr_t kernel_l1pt;
    324   1.1   ichiro 	pv_addr_t kernel_ptpt;
    325   1.1   ichiro #ifdef DDB
    326   1.1   ichiro         Elf_Shdr *sh;
    327   1.1   ichiro #endif
    328   1.1   ichiro 
    329   1.1   ichiro #ifdef DEBUG_BEFOREMMU
    330   1.1   ichiro 	/*
    331   1.1   ichiro 	 * At this point, we cannot call real consinit().
    332   1.1   ichiro 	 * Just call a faked up version of consinit(), which does the thing
    333   1.1   ichiro 	 * with MMU disabled.
    334   1.1   ichiro 	 */
    335   1.1   ichiro 	fakecninit();
    336   1.1   ichiro #endif
    337   1.1   ichiro         /*
    338   1.1   ichiro          * Since we map v0xf0000000 == p0x90000000, it's possible for
    339   1.1   ichiro          * us to initialize the console now.
    340   1.1   ichiro          */
    341   1.1   ichiro 	consinit();
    342   1.1   ichiro 
    343   1.1   ichiro 	/* Talk to the user */
    344   1.1   ichiro 	printf("\nNetBSD/evbarm (IXM1200) booting ...\n");
    345   1.1   ichiro 
    346   1.1   ichiro 	/*
    347   1.1   ichiro 	 * Heads up ... Setup the CPU / MMU / TLB functions
    348   1.1   ichiro 	 */
    349   1.1   ichiro 	if (set_cpufuncs())
    350   1.1   ichiro 		panic("cpu not recognized!");
    351   1.1   ichiro 
    352   1.1   ichiro 	/* XXX overwrite bootconfig to hardcoded values */
    353   1.1   ichiro 	bootconfig.dram[0].address = 0xc0000000;
    354  1.14  thorpej 	bootconfig.dram[0].pages   = 0x10000000 / PAGE_SIZE; /* SDRAM 256MB */
    355   1.1   ichiro 	bootconfig.dramblocks = 1;
    356   1.1   ichiro 
    357   1.1   ichiro 	kerneldatasize = (u_int32_t)&end - (u_int32_t)KERNEL_TEXT_BASE;
    358   1.1   ichiro 
    359   1.1   ichiro 	symbolsize = 0;
    360  1.10   ichiro 
    361  1.10   ichiro #ifdef PMAP_DEBUG
    362  1.10   ichiro 	pmap_debug(-1);
    363  1.10   ichiro #endif
    364  1.10   ichiro 
    365   1.1   ichiro #ifdef DDB
    366   1.1   ichiro         if (! memcmp(&end, "\177ELF", 4)) {
    367   1.1   ichiro                 sh = (Elf_Shdr *)((char *)&end + ((Elf_Ehdr *)&end)->e_shoff);
    368   1.1   ichiro                 loop = ((Elf_Ehdr *)&end)->e_shnum;
    369   1.1   ichiro                 for(; loop; loop--, sh++)
    370   1.1   ichiro                         if (sh->sh_offset > 0 &&
    371   1.1   ichiro                             (sh->sh_offset + sh->sh_size) > symbolsize)
    372   1.1   ichiro                                 symbolsize = sh->sh_offset + sh->sh_size;
    373   1.1   ichiro         }
    374   1.1   ichiro #endif
    375   1.1   ichiro 	printf("kernsize=0x%x\n", kerneldatasize);
    376   1.1   ichiro 	kerneldatasize += symbolsize;
    377  1.14  thorpej 	kerneldatasize = ((kerneldatasize - 1) & ~(PAGE_SIZE * 4 - 1)) + PAGE_SIZE * 8;
    378   1.1   ichiro 
    379   1.1   ichiro 	/*
    380   1.1   ichiro 	 * Set up the variables that define the availablilty of physcial
    381   1.1   ichiro 	 * memory
    382   1.1   ichiro 	 */
    383   1.1   ichiro 	physical_start = bootconfig.dram[0].address;
    384  1.14  thorpej 	physical_end = physical_start + (bootconfig.dram[0].pages * PAGE_SIZE);
    385   1.1   ichiro 
    386   1.1   ichiro 	physical_freestart = physical_start
    387   1.1   ichiro 		+ (KERNEL_TEXT_BASE - KERNEL_BASE) + kerneldatasize;
    388   1.1   ichiro 	physical_freeend = physical_end;
    389   1.1   ichiro 
    390  1.14  thorpej 	physmem = (physical_end - physical_start) / PAGE_SIZE;
    391   1.1   ichiro 
    392   1.1   ichiro 	freemempos = 0xc0000000;
    393   1.1   ichiro 
    394   1.1   ichiro #ifdef VERBOSE_INIT_ARM
    395   1.1   ichiro 	printf("Allocating page tables\n");
    396   1.1   ichiro #endif
    397  1.14  thorpej 	free_pages = (physical_freeend - physical_freestart) / PAGE_SIZE;
    398   1.1   ichiro 
    399   1.1   ichiro #ifdef VERBOSE_INIT_ARM
    400   1.1   ichiro 	printf("CP15 Register1 = 0x%08x\n", cpu_get_control());
    401   1.1   ichiro 	printf("freestart = 0x%08lx, free_pages = %d (0x%08x)\n",
    402   1.1   ichiro 		physical_freestart, free_pages, free_pages);
    403   1.1   ichiro 	printf("physical_start = 0x%08lx, physical_end = 0x%08lx\n",
    404   1.1   ichiro 		physical_start, physical_end);
    405   1.1   ichiro #endif
    406   1.1   ichiro 
    407   1.1   ichiro 	/* Define a macro to simplify memory allocation */
    408   1.1   ichiro #define valloc_pages(var, np)			\
    409   1.1   ichiro 	alloc_pages((var).pv_pa, (np));		\
    410   1.1   ichiro 	(var).pv_va = KERNEL_BASE + (var).pv_pa - physical_start;
    411   1.1   ichiro #define alloc_pages(var, np)				\
    412   1.1   ichiro 	(var) = freemempos;				\
    413  1.14  thorpej 	memset((char *)(var), 0, ((np) * PAGE_SIZE));	\
    414  1.14  thorpej 	freemempos += (np) * PAGE_SIZE;
    415   1.1   ichiro 
    416   1.1   ichiro 	loop1 = 0;
    417   1.1   ichiro 	kernel_l1pt.pv_pa = 0;
    418   1.1   ichiro 	for (loop = 0; loop <= NUM_KERNEL_PTS; ++loop) {
    419   1.1   ichiro 		/* Are we 16KB aligned for an L1 ? */
    420   1.1   ichiro 		if (((physical_freeend - L1_TABLE_SIZE) & (L1_TABLE_SIZE - 1)) == 0
    421   1.1   ichiro 		    && kernel_l1pt.pv_pa == 0) {
    422  1.14  thorpej 			valloc_pages(kernel_l1pt, L1_TABLE_SIZE / PAGE_SIZE);
    423   1.1   ichiro 		} else {
    424   1.1   ichiro 			alloc_pages(kernel_pt_table[loop1].pv_pa,
    425  1.14  thorpej 			    L2_TABLE_SIZE / PAGE_SIZE);
    426   1.1   ichiro 			kernel_pt_table[loop1].pv_va =
    427   1.1   ichiro 			    kernel_pt_table[loop1].pv_pa;
    428   1.1   ichiro 			++loop1;
    429   1.1   ichiro 		}
    430   1.1   ichiro 	}
    431   1.1   ichiro 
    432   1.1   ichiro #ifdef DIAGNOSTIC
    433   1.1   ichiro 	/* This should never be able to happen but better confirm that. */
    434   1.1   ichiro 	if (!kernel_l1pt.pv_pa || (kernel_l1pt.pv_pa & (L1_TABLE_SIZE-1)) != 0)
    435   1.8   provos 		panic("initarm: Failed to align the kernel page directory");
    436   1.1   ichiro #endif
    437   1.1   ichiro 
    438   1.1   ichiro 	/*
    439   1.1   ichiro 	 * Allocate a page for the system page mapped to V0x00000000
    440   1.1   ichiro 	 * This page will just contain the system vectors and can be
    441   1.1   ichiro 	 * shared by all processes.
    442   1.1   ichiro 	 */
    443   1.1   ichiro 	alloc_pages(systempage.pv_pa, 1);
    444   1.1   ichiro 
    445   1.1   ichiro 	/* Allocate a page for the page table to map kernel page tables. */
    446  1.14  thorpej 	valloc_pages(kernel_ptpt, L2_TABLE_SIZE / PAGE_SIZE);
    447   1.1   ichiro 
    448   1.1   ichiro 	/* Allocate stacks for all modes */
    449   1.1   ichiro 	valloc_pages(irqstack, IRQ_STACK_SIZE);
    450   1.1   ichiro 	valloc_pages(abtstack, ABT_STACK_SIZE);
    451   1.1   ichiro 	valloc_pages(undstack, UND_STACK_SIZE);
    452   1.1   ichiro 	valloc_pages(kernelstack, UPAGES);
    453   1.1   ichiro 
    454   1.1   ichiro #ifdef VERBOSE_INIT_ARM
    455   1.1   ichiro 	printf("IRQ stack: p0x%08lx v0x%08lx\n", irqstack.pv_pa, irqstack.pv_va);
    456   1.1   ichiro 	printf("ABT stack: p0x%08lx v0x%08lx\n", abtstack.pv_pa, abtstack.pv_va);
    457   1.1   ichiro 	printf("UND stack: p0x%08lx v0x%08lx\n", undstack.pv_pa, undstack.pv_va);
    458   1.1   ichiro 	printf("SVC stack: p0x%08lx v0x%08lx\n", kernelstack.pv_pa, kernelstack.pv_va);
    459   1.1   ichiro #endif
    460   1.1   ichiro 
    461  1.14  thorpej 	alloc_pages(msgbufphys, round_page(MSGBUFSIZE) / PAGE_SIZE);
    462   1.1   ichiro 
    463   1.1   ichiro #ifdef CPU_IXP12X0
    464   1.1   ichiro         /*
    465   1.1   ichiro          * XXX totally stuffed hack to work round problems introduced
    466   1.1   ichiro          * in recent versions of the pmap code. Due to the calls used there
    467   1.1   ichiro          * we cannot allocate virtual memory during bootstrap.
    468   1.1   ichiro          */
    469   1.1   ichiro 	for(;;) {
    470   1.1   ichiro 		alloc_pages(ixp12x0_cc_base, 1);
    471   1.1   ichiro 		if (! (ixp12x0_cc_base & (CPU_IXP12X0_CACHE_CLEAN_SIZE - 1)))
    472   1.1   ichiro 			break;
    473   1.1   ichiro 	}
    474   1.1   ichiro 	{
    475   1.1   ichiro 		vaddr_t dummy;
    476  1.14  thorpej 		alloc_pages(dummy, CPU_IXP12X0_CACHE_CLEAN_SIZE / PAGE_SIZE - 1);
    477   1.1   ichiro 	}
    478   1.1   ichiro 	ixp12x0_cache_clean_addr = ixp12x0_cc_base;
    479   1.1   ichiro 	ixp12x0_cache_clean_size = CPU_IXP12X0_CACHE_CLEAN_SIZE / 2;
    480   1.1   ichiro #endif /* CPU_IXP12X0 */
    481   1.1   ichiro 
    482   1.1   ichiro #ifdef VERBOSE_INIT_ARM
    483   1.1   ichiro 	printf("Creating L1 page table at 0x%08lx\n", kernel_l1pt.pv_pa);
    484   1.1   ichiro #endif
    485   1.1   ichiro 
    486   1.1   ichiro 	/*
    487   1.1   ichiro 	 * Now we start construction of the L1 page table
    488   1.1   ichiro 	 * We start by mapping the L2 page tables into the L1.
    489   1.1   ichiro 	 * This means that we can replace L1 mappings later on if necessary
    490   1.1   ichiro 	 */
    491   1.1   ichiro 	l1pagetable = kernel_l1pt.pv_pa;
    492   1.1   ichiro 
    493   1.1   ichiro 	/* Map the L2 pages tables in the L1 page table */
    494   1.1   ichiro 	pmap_link_l2pt(l1pagetable, 0x00000000,
    495   1.1   ichiro 	    &kernel_pt_table[KERNEL_PT_SYS]);
    496   1.1   ichiro 
    497   1.1   ichiro 	for (loop = 0; loop < KERNEL_PT_KERNEL_NUM; loop++)
    498   1.1   ichiro 		pmap_link_l2pt(l1pagetable, KERNEL_BASE + loop * 0x00400000,
    499   1.1   ichiro 		    &kernel_pt_table[KERNEL_PT_KERNEL + loop]);
    500   1.1   ichiro 
    501   1.1   ichiro 	for (loop = 0; loop < KERNEL_PT_VMDATA_NUM; loop++)
    502   1.1   ichiro 		pmap_link_l2pt(l1pagetable, KERNEL_VM_BASE + loop * 0x00400000,
    503   1.1   ichiro 		    &kernel_pt_table[KERNEL_PT_VMDATA + loop]);
    504   1.1   ichiro 	pmap_link_l2pt(l1pagetable, PTE_BASE, &kernel_ptpt);
    505   1.1   ichiro 
    506   1.1   ichiro 	/* update the top of the kernel VM */
    507   1.1   ichiro 	pmap_curmaxkvaddr =
    508   1.1   ichiro 	    KERNEL_VM_BASE + (KERNEL_PT_VMDATA_NUM * 0x00400000);
    509   1.1   ichiro 
    510   1.1   ichiro 	pmap_link_l2pt(l1pagetable, IXP12X0_IO_VBASE,
    511   1.1   ichiro 	    &kernel_pt_table[KERNEL_PT_IO]);
    512   1.1   ichiro 
    513   1.1   ichiro #ifdef VERBOSE_INIT_ARM
    514   1.1   ichiro 	printf("Mapping kernel\n");
    515   1.1   ichiro #endif
    516   1.1   ichiro 
    517   1.1   ichiro #if XXX
    518   1.1   ichiro 	/* Now we fill in the L2 pagetable for the kernel code/data */
    519   1.1   ichiro 	{
    520   1.1   ichiro 		extern char etext[], _end[];
    521   1.1   ichiro 		size_t textsize = (uintptr_t) etext - KERNEL_TEXT_BASE;
    522   1.1   ichiro 		size_t totalsize = (uintptr_t) _end - KERNEL_TEXT_BASE;
    523   1.1   ichiro 		u_int logical;
    524   1.1   ichiro 
    525   1.1   ichiro 		textsize = (textsize + PGOFSET) & ~PGOFSET;
    526   1.1   ichiro 		totalsize = (totalsize + PGOFSET) & ~PGOFSET;
    527   1.1   ichiro 
    528   1.1   ichiro 		logical = 0x00200000;   /* offset of kernel in RAM */
    529   1.1   ichiro 
    530   1.1   ichiro 		logical += pmap_map_chunk(l1pagetable, KERNEL_BASE + logical,
    531   1.1   ichiro 		    physical_start + logical, textsize,
    532   1.1   ichiro 		    VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE);
    533   1.1   ichiro 		logical += pmap_map_chunk(l1pagetable, KERNEL_BASE + logical,
    534   1.1   ichiro 		    physical_start + logical, totalsize - textsize,
    535   1.1   ichiro 		    VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE);
    536   1.1   ichiro 	}
    537   1.1   ichiro #else
    538   1.1   ichiro 	{
    539   1.1   ichiro 		pmap_map_chunk(l1pagetable, KERNEL_TEXT_BASE,
    540   1.1   ichiro                     KERNEL_TEXT_BASE, kerneldatasize,
    541   1.1   ichiro                     VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE);
    542   1.1   ichiro 	}
    543   1.1   ichiro #endif
    544   1.1   ichiro 
    545   1.1   ichiro #ifdef VERBOSE_INIT_ARM
    546   1.1   ichiro         printf("Constructing L2 page tables\n");
    547   1.1   ichiro #endif
    548   1.1   ichiro 
    549   1.1   ichiro 	/* Map the stack pages */
    550   1.1   ichiro 	pmap_map_chunk(l1pagetable, irqstack.pv_va, irqstack.pv_pa,
    551  1.14  thorpej 	    IRQ_STACK_SIZE * PAGE_SIZE, VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE);
    552   1.1   ichiro 	pmap_map_chunk(l1pagetable, abtstack.pv_va, abtstack.pv_pa,
    553  1.14  thorpej 	    ABT_STACK_SIZE * PAGE_SIZE, VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE);
    554   1.1   ichiro 	pmap_map_chunk(l1pagetable, undstack.pv_va, undstack.pv_pa,
    555  1.14  thorpej 	    UND_STACK_SIZE * PAGE_SIZE, VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE);
    556   1.1   ichiro 	pmap_map_chunk(l1pagetable, kernelstack.pv_va, kernelstack.pv_pa,
    557  1.14  thorpej 	    UPAGES * PAGE_SIZE, VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE);
    558   1.1   ichiro 
    559   1.1   ichiro 	pmap_map_chunk(l1pagetable, kernel_l1pt.pv_va, kernel_l1pt.pv_pa,
    560   1.5  thorpej 	    L1_TABLE_SIZE, VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE);
    561   1.1   ichiro 
    562   1.1   ichiro 	/* Map the page table that maps the kernel pages */
    563   1.1   ichiro 	pmap_map_entry(l1pagetable, kernel_ptpt.pv_va, kernel_ptpt.pv_pa,
    564   1.1   ichiro 	    VM_PROT_READ|VM_PROT_WRITE, PTE_NOCACHE);
    565   1.1   ichiro 
    566   1.1   ichiro 	/*
    567   1.1   ichiro 	 * Map entries in the page table used to map PTE's
    568   1.1   ichiro 	 * Basically every kernel page table gets mapped here
    569   1.1   ichiro 	 */
    570   1.1   ichiro 	/* The -2 is slightly bogus, it should be -log2(sizeof(pt_entry_t)) */
    571   1.1   ichiro 	pmap_map_entry(l1pagetable,
    572   1.1   ichiro 	    PTE_BASE + (0x00000000 >> (PGSHIFT-2)),
    573   1.1   ichiro 	    kernel_pt_table[KERNEL_PT_SYS].pv_pa,
    574   1.7  thorpej 	    VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE);
    575   1.1   ichiro 
    576   1.1   ichiro 	for (loop = 0; loop < KERNEL_PT_KERNEL_NUM; loop++)
    577   1.1   ichiro 		pmap_map_entry(l1pagetable,
    578   1.1   ichiro 		    PTE_BASE + ((KERNEL_BASE +
    579   1.1   ichiro 		    (loop * 0x00400000)) >> (PGSHIFT-2)),
    580   1.1   ichiro 		    kernel_pt_table[KERNEL_PT_KERNEL + loop].pv_pa,
    581   1.7  thorpej 		    VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE);
    582   1.1   ichiro 
    583   1.1   ichiro 	for (loop = 0; loop < KERNEL_PT_VMDATA_NUM; loop++)
    584   1.1   ichiro 		pmap_map_entry(l1pagetable,
    585   1.1   ichiro 		    PTE_BASE + ((KERNEL_VM_BASE +
    586   1.1   ichiro 		    (loop * 0x00400000)) >> (PGSHIFT-2)),
    587   1.1   ichiro 		    kernel_pt_table[KERNEL_PT_VMDATA + loop].pv_pa,
    588   1.7  thorpej 		    VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE);
    589   1.1   ichiro 
    590   1.1   ichiro 	pmap_map_entry(l1pagetable,
    591   1.1   ichiro 	    PTE_BASE + (PTE_BASE >> (PGSHIFT-2)),
    592   1.1   ichiro 	    kernel_ptpt.pv_pa, VM_PROT_READ|VM_PROT_WRITE, PTE_NOCACHE);
    593   1.1   ichiro 
    594   1.1   ichiro 	/* Map the vector page. */
    595   1.1   ichiro 	pmap_map_entry(l1pagetable, vector_page, systempage.pv_pa,
    596   1.1   ichiro 	    VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE);
    597   1.1   ichiro 
    598   1.1   ichiro #ifdef VERBOSE_INIT_ARM
    599   1.1   ichiro 	printf("systempage (vector page): p0x%08lx v0x%08lx\n",
    600   1.1   ichiro 	       systempage.pv_pa, vector_page);
    601   1.1   ichiro #endif
    602   1.1   ichiro 
    603   1.1   ichiro 	/*
    604   1.1   ichiro 	 * Map the PCI I/O spaces and IXP12x0 registers
    605   1.1   ichiro 	 */
    606   1.1   ichiro 
    607   1.1   ichiro 	ixp12x0_pmap_io_reg(l1pagetable);
    608   1.1   ichiro 
    609   1.1   ichiro 	printf("done.\n");
    610   1.1   ichiro 
    611   1.1   ichiro 	/*
    612   1.1   ichiro 	 * Map the Dcache Flush page.
    613   1.1   ichiro 	 * Hw Ref Manual 3.2.4.5 Software Dcache Flush
    614   1.1   ichiro 	 */
    615   1.1   ichiro 	pmap_map_chunk(l1pagetable, ixp12x0_cache_clean_addr, 0xe0000000,
    616   1.1   ichiro 	    CPU_IXP12X0_CACHE_CLEAN_SIZE, VM_PROT_READ, PTE_CACHE);
    617   1.1   ichiro 
    618   1.1   ichiro 	/*
    619   1.1   ichiro 	 * Now we have the real page tables in place so we can switch to them.
    620   1.1   ichiro 	 * Once this is done we will be running with the REAL kernel page
    621   1.1   ichiro 	 * tables.
    622   1.1   ichiro 	 */
    623   1.1   ichiro 
    624   1.1   ichiro 	/* Switch tables */
    625   1.1   ichiro 	setttb(kernel_l1pt.pv_pa);
    626   1.1   ichiro 	cpu_tlb_flushID();
    627   1.1   ichiro 
    628   1.1   ichiro 	/*
    629   1.1   ichiro 	 * We must now clean the cache again....
    630   1.1   ichiro 	 * Cleaning may be done by reading new data to displace any
    631   1.1   ichiro 	 * dirty data in the cache. This will have happened in setttb()
    632   1.1   ichiro 	 * but since we are boot strapping the addresses used for the read
    633   1.1   ichiro 	 * may have just been remapped and thus the cache could be out
    634   1.1   ichiro 	 * of sync. A re-clean after the switch will cure this.
    635   1.1   ichiro 	 * After booting there are no gross reloations of the kernel thus
    636   1.1   ichiro 	 * this problem will not occur after initarm().
    637   1.1   ichiro 	 */
    638   1.1   ichiro 	cpu_idcache_wbinv_all();
    639   1.1   ichiro 
    640   1.1   ichiro 	arm32_vector_init(ARM_VECTORS_LOW, ARM_VEC_ALL);
    641   1.1   ichiro 
    642   1.1   ichiro 	/*
    643   1.1   ichiro 	 * Pages were allocated during the secondary bootstrap for the
    644   1.1   ichiro 	 * stacks for different CPU modes.
    645   1.1   ichiro 	 * We must now set the r13 registers in the different CPU modes to
    646   1.1   ichiro 	 * point to these stacks.
    647   1.1   ichiro 	 * Since the ARM stacks use STMFD etc. we must set r13 to the top end
    648   1.1   ichiro 	 * of the stack memory.
    649   1.1   ichiro 	 */
    650   1.1   ichiro 	printf("init subsystems: stacks ");
    651   1.1   ichiro 
    652  1.14  thorpej 	set_stackptr(PSR_IRQ32_MODE,
    653  1.14  thorpej 	    irqstack.pv_va + IRQ_STACK_SIZE * PAGE_SIZE);
    654  1.14  thorpej 	set_stackptr(PSR_ABT32_MODE,
    655  1.14  thorpej 	    abtstack.pv_va + ABT_STACK_SIZE * PAGE_SIZE);
    656  1.14  thorpej 	set_stackptr(PSR_UND32_MODE,
    657  1.14  thorpej 	    undstack.pv_va + UND_STACK_SIZE * PAGE_SIZE);
    658   1.1   ichiro #ifdef PMAP_DEBUG
    659   1.1   ichiro 	if (pmap_debug_level >= 0)
    660   1.1   ichiro 		printf("kstack V%08lx P%08lx\n", kernelstack.pv_va,
    661   1.1   ichiro 		    kernelstack.pv_pa);
    662   1.1   ichiro #endif  /* PMAP_DEBUG */
    663   1.1   ichiro 
    664   1.1   ichiro 	/*
    665   1.1   ichiro 	 * Well we should set a data abort handler.
    666   1.1   ichiro 	 * Once things get going this will change as we will need a proper
    667   1.1   ichiro 	 * handler. Until then we will use a handler that just panics but
    668   1.1   ichiro 	 * tells us why.
    669   1.1   ichiro 	 * Initialisation of the vetcors will just panic on a data abort.
    670   1.1   ichiro 	 * This just fills in a slighly better one.
    671   1.1   ichiro 	 */
    672   1.1   ichiro 	printf("vectors ");
    673   1.1   ichiro 	data_abort_handler_address = (u_int)data_abort_handler;
    674   1.1   ichiro 	prefetch_abort_handler_address = (u_int)prefetch_abort_handler;
    675   1.1   ichiro 	undefined_handler_address = (u_int)undefinedinstruction_bounce;
    676   1.1   ichiro 	printf("\ndata_abort_handler_address = %08x\n", data_abort_handler_address);
    677   1.1   ichiro 	printf("prefetch_abort_handler_address = %08x\n", prefetch_abort_handler_address);
    678   1.1   ichiro 	printf("undefined_handler_address = %08x\n", undefined_handler_address);
    679   1.1   ichiro 
    680   1.1   ichiro 	/* Initialise the undefined instruction handlers */
    681   1.1   ichiro 	printf("undefined ");
    682   1.1   ichiro 	undefined_init();
    683   1.1   ichiro 
    684   1.4  thorpej 	/* Load memory into UVM. */
    685   1.4  thorpej 	printf("page ");
    686   1.4  thorpej 	uvm_setpagesize();	/* initialize PAGE_SIZE-dependent variables */
    687   1.4  thorpej 	uvm_page_physload(atop(physical_freestart), atop(physical_freeend),
    688   1.4  thorpej 	    atop(physical_freestart), atop(physical_freeend),
    689   1.4  thorpej 	    VM_FREELIST_DEFAULT);
    690   1.4  thorpej 
    691   1.1   ichiro 	/* Boot strap pmap telling it where the kernel page table is */
    692   1.1   ichiro 	printf("pmap ");
    693   1.1   ichiro 	pmap_bootstrap((pd_entry_t *)kernel_l1pt.pv_va, kernel_ptpt);
    694   1.1   ichiro 
    695   1.1   ichiro 	/* Setup the IRQ system */
    696   1.1   ichiro 	printf("irq ");
    697   1.1   ichiro 	ixp12x0_intr_init();
    698   1.1   ichiro 	printf("done.\n");
    699   1.1   ichiro 
    700   1.1   ichiro #ifdef VERBOSE_INIT_ARM
    701   1.1   ichiro 	printf("freestart = 0x%08lx, free_pages = %d (0x%x)\n",
    702   1.1   ichiro 		physical_freestart, free_pages, free_pages);
    703   1.1   ichiro 	printf("freemempos=%08lx\n", freemempos);
    704   1.1   ichiro 	printf("switching to new L1 page table  @%#lx... \n", kernel_l1pt.pv_pa);
    705   1.1   ichiro #endif
    706   1.1   ichiro 
    707   1.1   ichiro 	consinit();
    708   1.1   ichiro 	printf("consinit \n");
    709   1.1   ichiro 
    710   1.1   ichiro 	ixdp_ixp12x0_cc_setup();
    711   1.1   ichiro 
    712   1.1   ichiro 	printf("bootstrap done.\n");
    713   1.1   ichiro 
    714   1.1   ichiro #ifdef IPKDB
    715   1.1   ichiro 	/* Initialise ipkdb */
    716   1.1   ichiro 	ipkdb_init();
    717   1.1   ichiro 	if (boothowto & RB_KDB)
    718   1.1   ichiro 		ipkdb_connect(0);
    719   1.1   ichiro #endif  /* NIPKDB */
    720   1.1   ichiro 
    721   1.1   ichiro #ifdef DDB
    722   1.1   ichiro 	{
    723   1.1   ichiro 		static struct undefined_handler uh;
    724   1.1   ichiro 
    725   1.1   ichiro 		uh.uh_handler = db_trapper;
    726   1.1   ichiro 		install_coproc_handler_static(0, &uh);
    727   1.1   ichiro 	}
    728   1.1   ichiro 	ddb_init(symbolsize, ((int *)&end), ((char *)&end) + symbolsize);
    729   1.1   ichiro 
    730   1.1   ichiro 	if (boothowto & RB_KDB)
    731   1.1   ichiro 		Debugger();
    732   1.1   ichiro #endif
    733   1.1   ichiro 
    734   1.1   ichiro 	/* We return the new stack pointer address */
    735   1.1   ichiro 	return(kernelstack.pv_va + USPACE_SVC_STACK_TOP);
    736   1.1   ichiro }
    737   1.1   ichiro 
    738   1.1   ichiro void
    739   1.1   ichiro consinit(void)
    740   1.1   ichiro {
    741   1.1   ichiro 	extern struct bus_space ixpsip_bs_tag;
    742   1.1   ichiro 	static int consinit_called = 0;
    743   1.1   ichiro 
    744   1.1   ichiro 	if (consinit_called != 0)
    745   1.1   ichiro 		return;
    746   1.1   ichiro 
    747   1.1   ichiro 	consinit_called = 1;
    748   1.1   ichiro 
    749  1.12      igy 	if (ixpcomcnattach(&ixpsip_bs_tag,
    750  1.12      igy 			   IXPCOM_UART_HWBASE, IXPCOM_UART_VBASE,
    751   1.1   ichiro 			   CONSPEED, CONMODE))
    752  1.12      igy 		panic("can't init serial console @%lx", IXPCOM_UART_HWBASE);
    753   1.1   ichiro }
    754   1.1   ichiro 
    755   1.1   ichiro #ifdef DEBUG_BEFOREMMU
    756   1.1   ichiro cons_decl(ixpcom);
    757   1.1   ichiro void
    758   1.1   ichiro fakecninit()
    759   1.1   ichiro {
    760   1.1   ichiro 	static struct consdev fakecntab = cons_init(ixpcom);
    761   1.1   ichiro 	cn_tab = &fakecntab;
    762   1.1   ichiro 
    763   1.1   ichiro 	(*cn_tab->cn_init)(0);
    764   1.1   ichiro 	cn_tab->cn_pri = CN_REMOTE;
    765   1.1   ichiro }
    766   1.1   ichiro #endif
    767   1.1   ichiro 
    768   1.1   ichiro /*
    769   1.1   ichiro  * For optimal cache cleaning we need two 16K banks of
    770   1.1   ichiro  * virtual address space that NOTHING else will access
    771   1.1   ichiro  * and then we alternate the cache cleaning between the
    772   1.1   ichiro  * two banks.
    773   1.1   ichiro  * The cache cleaning code requires requires 2 banks aligned
    774   1.1   ichiro  * on total size boundry so the banks can be alternated by
    775   1.1   ichiro  * eorring the size bit (assumes the bank size is a power of 2)
    776   1.1   ichiro  */
    777   1.1   ichiro void
    778   1.1   ichiro ixdp_ixp12x0_cc_setup(void)
    779   1.1   ichiro {
    780   1.1   ichiro 	int loop;
    781   1.1   ichiro 	paddr_t kaddr;
    782   1.1   ichiro 	pt_entry_t *pte;
    783   1.1   ichiro 
    784   1.1   ichiro 	(void) pmap_extract(pmap_kernel(), KERNEL_TEXT_BASE, &kaddr);
    785  1.14  thorpej 	for (loop = 0; loop < CPU_IXP12X0_CACHE_CLEAN_SIZE; loop += PAGE_SIZE) {
    786   1.1   ichiro                 pte = vtopte(ixp12x0_cc_base + loop);
    787   1.1   ichiro                 *pte = L2_S_PROTO | kaddr |
    788   1.1   ichiro                     L2_S_PROT(PTE_KERNEL, VM_PROT_READ) | pte_l2_s_cache_mode;
    789   1.6  thorpej 		PTE_SYNC(pte);
    790   1.1   ichiro         }
    791   1.1   ichiro 	ixp12x0_cache_clean_addr = ixp12x0_cc_base;
    792   1.1   ichiro 	ixp12x0_cache_clean_size = CPU_IXP12X0_CACHE_CLEAN_SIZE / 2;
    793   1.1   ichiro }
    794