ixm1200_machdep.c revision 1.35 1 1.35 dyoung /* $NetBSD: ixm1200_machdep.c,v 1.35 2008/11/11 06:46:41 dyoung Exp $ */
2 1.22 igy
3 1.1 ichiro /*
4 1.12 igy * Copyright (c) 2002, 2003
5 1.1 ichiro * Ichiro FUKUHARA <ichiro (at) ichiro.org>.
6 1.1 ichiro * All rights reserved.
7 1.1 ichiro *
8 1.1 ichiro * Redistribution and use in source and binary forms, with or without
9 1.1 ichiro * modification, are permitted provided that the following conditions
10 1.1 ichiro * are met:
11 1.1 ichiro * 1. Redistributions of source code must retain the above copyright
12 1.1 ichiro * notice, this list of conditions and the following disclaimer.
13 1.1 ichiro * 2. Redistributions in binary form must reproduce the above copyright
14 1.1 ichiro * notice, this list of conditions and the following disclaimer in the
15 1.1 ichiro * documentation and/or other materials provided with the distribution.
16 1.1 ichiro * 3. All advertising materials mentioning features or use of this software
17 1.1 ichiro * must display the following acknowledgement:
18 1.1 ichiro * This product includes software developed by Ichiro FUKUHARA.
19 1.1 ichiro * 4. The name of the company nor the name of the author may be used to
20 1.1 ichiro * endorse or promote products derived from this software without specific
21 1.1 ichiro * prior written permission.
22 1.1 ichiro *
23 1.1 ichiro * THIS SOFTWARE IS PROVIDED BY ICHIRO FUKUHARA ``AS IS'' AND ANY EXPRESS OR
24 1.1 ichiro * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
25 1.1 ichiro * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
26 1.1 ichiro * IN NO EVENT SHALL ICHIRO FUKUHARA OR THE VOICES IN HIS HEAD BE LIABLE FOR
27 1.1 ichiro * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
28 1.1 ichiro * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
29 1.1 ichiro * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
30 1.1 ichiro * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
31 1.1 ichiro * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
32 1.1 ichiro * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
33 1.1 ichiro * SUCH DAMAGE.
34 1.1 ichiro */
35 1.1 ichiro /*
36 1.1 ichiro * Copyright (c) 1997,1998 Mark Brinicombe.
37 1.1 ichiro * Copyright (c) 1997,1998 Causality Limited.
38 1.1 ichiro * All rights reserved.
39 1.1 ichiro *
40 1.1 ichiro * Redistribution and use in source and binary forms, with or without
41 1.1 ichiro * modification, are permitted provided that the following conditions
42 1.1 ichiro * are met:
43 1.1 ichiro * 1. Redistributions of source code must retain the above copyright
44 1.1 ichiro * notice, this list of conditions and the following disclaimer.
45 1.1 ichiro * 2. Redistributions in binary form must reproduce the above copyright
46 1.1 ichiro * notice, this list of conditions and the following disclaimer in the
47 1.1 ichiro * documentation and/or other materials provided with the distribution.
48 1.1 ichiro * 3. All advertising materials mentioning features or use of this software
49 1.1 ichiro * must display the following acknowledgement:
50 1.1 ichiro * This product includes software developed by Mark Brinicombe
51 1.1 ichiro * for the NetBSD Project.
52 1.1 ichiro * 4. The name of the company nor the name of the author may be used to
53 1.1 ichiro * endorse or promote products derived from this software without specific
54 1.1 ichiro * prior written permission.
55 1.1 ichiro *
56 1.1 ichiro * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
57 1.1 ichiro * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
58 1.1 ichiro * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
59 1.1 ichiro * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
60 1.1 ichiro * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
61 1.1 ichiro * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
62 1.1 ichiro * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
63 1.1 ichiro * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
64 1.1 ichiro * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
65 1.1 ichiro * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
66 1.1 ichiro * SUCH DAMAGE.
67 1.1 ichiro */
68 1.13 igy
69 1.13 igy #include <sys/cdefs.h>
70 1.35 dyoung __KERNEL_RCSID(0, "$NetBSD: ixm1200_machdep.c,v 1.35 2008/11/11 06:46:41 dyoung Exp $");
71 1.1 ichiro
72 1.1 ichiro #include "opt_ddb.h"
73 1.1 ichiro #include "opt_pmap_debug.h"
74 1.1 ichiro
75 1.1 ichiro #include <sys/param.h>
76 1.1 ichiro #include <sys/device.h>
77 1.1 ichiro #include <sys/systm.h>
78 1.1 ichiro #include <sys/kernel.h>
79 1.1 ichiro #include <sys/exec.h>
80 1.1 ichiro #include <sys/proc.h>
81 1.1 ichiro #include <sys/msgbuf.h>
82 1.1 ichiro #include <sys/reboot.h>
83 1.1 ichiro #include <sys/termios.h>
84 1.15 ragge #include <sys/ksyms.h>
85 1.1 ichiro
86 1.14 thorpej #include <uvm/uvm_extern.h>
87 1.14 thorpej
88 1.1 ichiro #include <dev/cons.h>
89 1.1 ichiro
90 1.15 ragge #include "ksyms.h"
91 1.15 ragge
92 1.15 ragge #if NKSYMS || defined(DDB) || defined(LKM)
93 1.1 ichiro #include <machine/db_machdep.h>
94 1.1 ichiro #include <ddb/db_sym.h>
95 1.1 ichiro #include <ddb/db_extern.h>
96 1.1 ichiro #ifndef DB_ELFSIZE
97 1.1 ichiro #error Must define DB_ELFSIZE!
98 1.1 ichiro #endif
99 1.1 ichiro #define ELFSIZE DB_ELFSIZE
100 1.1 ichiro #include <sys/exec_elf.h>
101 1.1 ichiro #endif
102 1.1 ichiro
103 1.1 ichiro #include <machine/bootconfig.h>
104 1.1 ichiro #include <machine/bus.h>
105 1.1 ichiro #include <machine/cpu.h>
106 1.1 ichiro #include <machine/frame.h>
107 1.1 ichiro #include <arm/undefined.h>
108 1.1 ichiro
109 1.1 ichiro #include <arm/arm32/machdep.h>
110 1.1 ichiro
111 1.1 ichiro #include <arm/ixp12x0/ixp12x0reg.h>
112 1.1 ichiro #include <arm/ixp12x0/ixp12x0var.h>
113 1.1 ichiro #include <arm/ixp12x0/ixp12x0_comreg.h>
114 1.1 ichiro #include <arm/ixp12x0/ixp12x0_comvar.h>
115 1.1 ichiro #include <arm/ixp12x0/ixp12x0_pcireg.h>
116 1.1 ichiro
117 1.1 ichiro #include <evbarm/ixm1200/ixm1200reg.h>
118 1.1 ichiro #include <evbarm/ixm1200/ixm1200var.h>
119 1.1 ichiro
120 1.1 ichiro /* XXX for consinit related hacks */
121 1.1 ichiro #include <sys/conf.h>
122 1.1 ichiro
123 1.1 ichiro void ixp12x0_reset(void) __attribute__((noreturn));
124 1.20 thorpej
125 1.20 thorpej /* Kernel text starts 2MB in from the bottom of the kernel address space. */
126 1.20 thorpej #define KERNEL_TEXT_BASE (KERNEL_BASE + 0x00200000)
127 1.24 thorpej #define KERNEL_VM_BASE (KERNEL_BASE + 0x01000000)
128 1.25 thorpej
129 1.25 thorpej /*
130 1.25 thorpej * The range 0xc1000000 - 0xccffffff is available for kernel VM space
131 1.25 thorpej * Core-logic registers and I/O mappings occupy 0xfd000000 - 0xffffffff
132 1.25 thorpej */
133 1.25 thorpej #define KERNEL_VM_SIZE 0x0C000000
134 1.1 ichiro
135 1.1 ichiro /*
136 1.1 ichiro * Address to call from cpu_reset() to reset the machine.
137 1.1 ichiro * This is machine architecture dependant as it varies depending
138 1.1 ichiro * on where the ROM appears when you turn the MMU off.
139 1.1 ichiro */
140 1.1 ichiro
141 1.1 ichiro u_int cpu_reset_address = (u_int) ixp12x0_reset;
142 1.1 ichiro
143 1.1 ichiro /*
144 1.1 ichiro * Define the default console speed for the board.
145 1.1 ichiro */
146 1.1 ichiro #ifndef CONMODE
147 1.1 ichiro #define CONMODE ((TTYDEF_CFLAG & ~(CSIZE | CSTOPB)) | CS8) /* 8N1 */
148 1.1 ichiro #endif
149 1.1 ichiro #ifndef CONSPEED
150 1.1 ichiro #define CONSPEED B38400
151 1.1 ichiro #endif
152 1.1 ichiro #ifndef CONADDR
153 1.1 ichiro #define CONADDR IXPCOM_UART_BASE
154 1.1 ichiro #endif
155 1.1 ichiro
156 1.1 ichiro /* Define various stack sizes in pages */
157 1.1 ichiro #define IRQ_STACK_SIZE 1
158 1.1 ichiro #define ABT_STACK_SIZE 1
159 1.1 ichiro #define UND_STACK_SIZE 1
160 1.1 ichiro
161 1.1 ichiro BootConfig bootconfig; /* Boot config storage */
162 1.1 ichiro char *boot_args = NULL;
163 1.1 ichiro char *boot_file = NULL;
164 1.1 ichiro
165 1.1 ichiro vm_offset_t physical_start;
166 1.1 ichiro vm_offset_t physical_freestart;
167 1.1 ichiro vm_offset_t physical_freeend;
168 1.1 ichiro vm_offset_t physical_end;
169 1.1 ichiro u_int free_pages;
170 1.1 ichiro vm_offset_t pagetables_start;
171 1.1 ichiro int physmem = 0;
172 1.1 ichiro
173 1.1 ichiro /*int debug_flags;*/
174 1.1 ichiro #ifndef PMAP_STATIC_L1S
175 1.1 ichiro int max_processes = 64; /* Default number */
176 1.1 ichiro #endif /* !PMAP_STATIC_L1S */
177 1.1 ichiro
178 1.1 ichiro /* Physical and virtual addresses for some global pages */
179 1.1 ichiro pv_addr_t irqstack;
180 1.1 ichiro pv_addr_t undstack;
181 1.1 ichiro pv_addr_t abtstack;
182 1.1 ichiro pv_addr_t kernelstack;
183 1.1 ichiro
184 1.1 ichiro vm_offset_t msgbufphys;
185 1.1 ichiro
186 1.1 ichiro extern u_int data_abort_handler_address;
187 1.1 ichiro extern u_int prefetch_abort_handler_address;
188 1.1 ichiro extern u_int undefined_handler_address;
189 1.1 ichiro extern int end;
190 1.1 ichiro
191 1.1 ichiro #ifdef PMAP_DEBUG
192 1.1 ichiro extern int pmap_debug_level;
193 1.1 ichiro #endif /* PMAP_DEBUG */
194 1.1 ichiro
195 1.1 ichiro #define KERNEL_PT_SYS 0 /* Page table for mapping proc0 zero page */
196 1.1 ichiro #define KERNEL_PT_KERNEL 1 /* Page table for mapping kernel */
197 1.1 ichiro #define KERNEL_PT_KERNEL_NUM 2
198 1.1 ichiro #define KERNEL_PT_IO (KERNEL_PT_KERNEL + KERNEL_PT_KERNEL_NUM)
199 1.1 ichiro /* Page table for mapping IO */
200 1.1 ichiro #define KERNEL_PT_VMDATA (KERNEL_PT_IO + 1)
201 1.1 ichiro /* Page tables for mapping kernel VM */
202 1.1 ichiro #define KERNEL_PT_VMDATA_NUM 4 /* start with 16MB of KVM */
203 1.1 ichiro #define NUM_KERNEL_PTS (KERNEL_PT_VMDATA + KERNEL_PT_VMDATA_NUM)
204 1.1 ichiro
205 1.1 ichiro pv_addr_t kernel_pt_table[NUM_KERNEL_PTS];
206 1.1 ichiro
207 1.1 ichiro struct user *proc0paddr;
208 1.1 ichiro
209 1.1 ichiro #ifdef CPU_IXP12X0
210 1.1 ichiro #define CPU_IXP12X0_CACHE_CLEAN_SIZE (0x4000 * 2)
211 1.1 ichiro extern unsigned int ixp12x0_cache_clean_addr;
212 1.1 ichiro extern unsigned int ixp12x0_cache_clean_size;
213 1.1 ichiro static vaddr_t ixp12x0_cc_base;
214 1.1 ichiro #endif /* CPU_IXP12X0 */
215 1.1 ichiro
216 1.1 ichiro /* Prototypes */
217 1.1 ichiro
218 1.1 ichiro void consinit __P((void));
219 1.1 ichiro u_int cpu_get_control __P((void));
220 1.1 ichiro
221 1.1 ichiro void ixdp_ixp12x0_cc_setup(void);
222 1.1 ichiro
223 1.1 ichiro /*
224 1.1 ichiro * void cpu_reboot(int howto, char *bootstr)
225 1.1 ichiro *
226 1.1 ichiro * Reboots the system
227 1.1 ichiro *
228 1.1 ichiro * Deal with any syncing, unmounting, dumping and shutdown hooks,
229 1.1 ichiro * then reset the CPU.
230 1.1 ichiro */
231 1.1 ichiro
232 1.1 ichiro void
233 1.1 ichiro cpu_reboot(howto, bootstr)
234 1.1 ichiro int howto;
235 1.1 ichiro char *bootstr;
236 1.1 ichiro {
237 1.1 ichiro /*
238 1.1 ichiro * If we are still cold then hit the air brakes
239 1.1 ichiro * and crash to earth fast
240 1.1 ichiro */
241 1.1 ichiro if (cold) {
242 1.1 ichiro doshutdownhooks();
243 1.35 dyoung pmf_system_shutdown(boothowto);
244 1.1 ichiro printf("Halted while still in the ICE age.\n");
245 1.1 ichiro printf("The operating system has halted.\n");
246 1.1 ichiro printf("Please press any key to reboot.\n\n");
247 1.1 ichiro cngetc();
248 1.1 ichiro printf("rebooting...\n");
249 1.1 ichiro ixp12x0_reset();
250 1.1 ichiro }
251 1.1 ichiro
252 1.1 ichiro /* Disable console buffering */
253 1.1 ichiro cnpollc(1);
254 1.1 ichiro
255 1.1 ichiro /*
256 1.1 ichiro * If RB_NOSYNC was not specified sync the discs.
257 1.1 ichiro * Note: Unless cold is set to 1 here, syslogd will die during the unmount.
258 1.1 ichiro * It looks like syslogd is getting woken up only to find that it cannot
259 1.1 ichiro * page part of the binary in as the filesystem has been unmounted.
260 1.1 ichiro */
261 1.1 ichiro if (!(howto & RB_NOSYNC))
262 1.1 ichiro bootsync();
263 1.1 ichiro
264 1.1 ichiro /* Say NO to interrupts */
265 1.1 ichiro splhigh();
266 1.1 ichiro
267 1.1 ichiro /* Do a dump if requested. */
268 1.1 ichiro if ((howto & (RB_DUMP | RB_HALT)) == RB_DUMP)
269 1.1 ichiro dumpsys();
270 1.1 ichiro
271 1.1 ichiro /* Run any shutdown hooks */
272 1.1 ichiro doshutdownhooks();
273 1.1 ichiro
274 1.35 dyoung pmf_system_shutdown(boothowto);
275 1.35 dyoung
276 1.1 ichiro /* Make sure IRQ's are disabled */
277 1.1 ichiro IRQdisable;
278 1.1 ichiro
279 1.1 ichiro if (howto & RB_HALT) {
280 1.1 ichiro printf("The operating system has halted.\n");
281 1.1 ichiro printf("Please press any key to reboot.\n\n");
282 1.1 ichiro cngetc();
283 1.1 ichiro }
284 1.1 ichiro
285 1.1 ichiro printf("rebooting...\n");
286 1.1 ichiro
287 1.1 ichiro /* all interrupts are disabled */
288 1.1 ichiro disable_interrupts(I32_bit);
289 1.1 ichiro
290 1.1 ichiro ixp12x0_reset();
291 1.1 ichiro
292 1.1 ichiro /* ...and if that didn't work, just croak. */
293 1.1 ichiro printf("RESET FAILED!\n");
294 1.1 ichiro for (;;);
295 1.1 ichiro }
296 1.1 ichiro
297 1.26 igy /* Static device mappings. */
298 1.26 igy static const struct pmap_devmap ixm1200_devmap[] = {
299 1.26 igy /* StrongARM System and Peripheral Registers */
300 1.26 igy {
301 1.26 igy IXP12X0_SYS_VBASE,
302 1.26 igy IXP12X0_SYS_HWBASE,
303 1.26 igy IXP12X0_SYS_SIZE,
304 1.26 igy VM_PROT_READ|VM_PROT_WRITE,
305 1.26 igy PTE_NOCACHE,
306 1.26 igy },
307 1.26 igy /* PCI Registers Accessible Through StrongARM Core */
308 1.26 igy {
309 1.26 igy IXP12X0_PCI_VBASE, IXP12X0_PCI_HWBASE,
310 1.26 igy IXP12X0_PCI_SIZE,
311 1.26 igy VM_PROT_READ|VM_PROT_WRITE,
312 1.26 igy PTE_NOCACHE,
313 1.26 igy },
314 1.26 igy /* PCI Registers Accessible Through I/O Cycle Access */
315 1.26 igy {
316 1.26 igy IXP12X0_PCI_IO_VBASE, IXP12X0_PCI_IO_HWBASE,
317 1.26 igy IXP12X0_PCI_IO_SIZE,
318 1.26 igy VM_PROT_READ|VM_PROT_WRITE,
319 1.26 igy PTE_NOCACHE,
320 1.26 igy },
321 1.26 igy /* PCI Type0 Configuration Space */
322 1.26 igy {
323 1.26 igy IXP12X0_PCI_TYPE0_VBASE, IXP12X0_PCI_TYPE0_HWBASE,
324 1.26 igy IXP12X0_PCI_TYPE0_SIZE,
325 1.26 igy VM_PROT_READ|VM_PROT_WRITE,
326 1.26 igy PTE_NOCACHE,
327 1.26 igy },
328 1.26 igy /* PCI Type1 Configuration Space */
329 1.26 igy {
330 1.26 igy IXP12X0_PCI_TYPE1_VBASE, IXP12X0_PCI_TYPE1_HWBASE,
331 1.26 igy IXP12X0_PCI_TYPE1_SIZE,
332 1.26 igy VM_PROT_READ|VM_PROT_WRITE,
333 1.26 igy PTE_NOCACHE,
334 1.26 igy },
335 1.26 igy {
336 1.26 igy 0,
337 1.26 igy 0,
338 1.26 igy 0,
339 1.26 igy 0,
340 1.26 igy 0
341 1.26 igy },
342 1.26 igy };
343 1.26 igy
344 1.1 ichiro /*
345 1.1 ichiro * Initial entry point on startup. This gets called before main() is
346 1.1 ichiro * entered.
347 1.1 ichiro * It should be responsible for setting up everything that must be
348 1.1 ichiro * in place when main is called.
349 1.1 ichiro * This includes
350 1.1 ichiro * Taking a copy of the boot configuration structure.
351 1.1 ichiro * Initialising the physical console so characters can be printed.
352 1.1 ichiro * Setting up page tables for the kernel
353 1.1 ichiro * Relocating the kernel to the bottom of physical memory
354 1.1 ichiro */
355 1.1 ichiro u_int
356 1.1 ichiro initarm(void *arg)
357 1.1 ichiro {
358 1.1 ichiro int loop;
359 1.1 ichiro int loop1;
360 1.1 ichiro u_int kerneldatasize, symbolsize;
361 1.1 ichiro vaddr_t l1pagetable;
362 1.1 ichiro vaddr_t freemempos;
363 1.15 ragge #if NKSYMS || defined(DDB) || defined(LKM)
364 1.1 ichiro Elf_Shdr *sh;
365 1.1 ichiro #endif
366 1.1 ichiro
367 1.1 ichiro /*
368 1.1 ichiro * Since we map v0xf0000000 == p0x90000000, it's possible for
369 1.1 ichiro * us to initialize the console now.
370 1.1 ichiro */
371 1.1 ichiro consinit();
372 1.1 ichiro
373 1.23 thorpej #ifdef VERBOSE_INIT_ARM
374 1.1 ichiro /* Talk to the user */
375 1.1 ichiro printf("\nNetBSD/evbarm (IXM1200) booting ...\n");
376 1.23 thorpej #endif
377 1.1 ichiro
378 1.1 ichiro /*
379 1.1 ichiro * Heads up ... Setup the CPU / MMU / TLB functions
380 1.1 ichiro */
381 1.1 ichiro if (set_cpufuncs())
382 1.28 wiz panic("CPU not recognized!");
383 1.1 ichiro
384 1.1 ichiro /* XXX overwrite bootconfig to hardcoded values */
385 1.1 ichiro bootconfig.dram[0].address = 0xc0000000;
386 1.14 thorpej bootconfig.dram[0].pages = 0x10000000 / PAGE_SIZE; /* SDRAM 256MB */
387 1.1 ichiro bootconfig.dramblocks = 1;
388 1.1 ichiro
389 1.1 ichiro kerneldatasize = (u_int32_t)&end - (u_int32_t)KERNEL_TEXT_BASE;
390 1.1 ichiro
391 1.1 ichiro symbolsize = 0;
392 1.10 ichiro
393 1.10 ichiro #ifdef PMAP_DEBUG
394 1.10 ichiro pmap_debug(-1);
395 1.10 ichiro #endif
396 1.10 ichiro
397 1.15 ragge #if NKSYMS || defined(DDB) || defined(LKM)
398 1.1 ichiro if (! memcmp(&end, "\177ELF", 4)) {
399 1.1 ichiro sh = (Elf_Shdr *)((char *)&end + ((Elf_Ehdr *)&end)->e_shoff);
400 1.1 ichiro loop = ((Elf_Ehdr *)&end)->e_shnum;
401 1.1 ichiro for(; loop; loop--, sh++)
402 1.1 ichiro if (sh->sh_offset > 0 &&
403 1.1 ichiro (sh->sh_offset + sh->sh_size) > symbolsize)
404 1.1 ichiro symbolsize = sh->sh_offset + sh->sh_size;
405 1.1 ichiro }
406 1.1 ichiro #endif
407 1.23 thorpej #ifdef VERBOSE_INIT_ARM
408 1.1 ichiro printf("kernsize=0x%x\n", kerneldatasize);
409 1.23 thorpej #endif
410 1.1 ichiro kerneldatasize += symbolsize;
411 1.14 thorpej kerneldatasize = ((kerneldatasize - 1) & ~(PAGE_SIZE * 4 - 1)) + PAGE_SIZE * 8;
412 1.1 ichiro
413 1.1 ichiro /*
414 1.1 ichiro * Set up the variables that define the availablilty of physcial
415 1.1 ichiro * memory
416 1.1 ichiro */
417 1.1 ichiro physical_start = bootconfig.dram[0].address;
418 1.14 thorpej physical_end = physical_start + (bootconfig.dram[0].pages * PAGE_SIZE);
419 1.1 ichiro
420 1.1 ichiro physical_freestart = physical_start
421 1.1 ichiro + (KERNEL_TEXT_BASE - KERNEL_BASE) + kerneldatasize;
422 1.1 ichiro physical_freeend = physical_end;
423 1.1 ichiro
424 1.14 thorpej physmem = (physical_end - physical_start) / PAGE_SIZE;
425 1.1 ichiro
426 1.1 ichiro freemempos = 0xc0000000;
427 1.1 ichiro
428 1.1 ichiro #ifdef VERBOSE_INIT_ARM
429 1.1 ichiro printf("Allocating page tables\n");
430 1.1 ichiro #endif
431 1.14 thorpej free_pages = (physical_freeend - physical_freestart) / PAGE_SIZE;
432 1.1 ichiro
433 1.1 ichiro #ifdef VERBOSE_INIT_ARM
434 1.1 ichiro printf("CP15 Register1 = 0x%08x\n", cpu_get_control());
435 1.1 ichiro printf("freestart = 0x%08lx, free_pages = %d (0x%08x)\n",
436 1.1 ichiro physical_freestart, free_pages, free_pages);
437 1.1 ichiro printf("physical_start = 0x%08lx, physical_end = 0x%08lx\n",
438 1.1 ichiro physical_start, physical_end);
439 1.1 ichiro #endif
440 1.1 ichiro
441 1.1 ichiro /* Define a macro to simplify memory allocation */
442 1.1 ichiro #define valloc_pages(var, np) \
443 1.1 ichiro alloc_pages((var).pv_pa, (np)); \
444 1.1 ichiro (var).pv_va = KERNEL_BASE + (var).pv_pa - physical_start;
445 1.1 ichiro #define alloc_pages(var, np) \
446 1.1 ichiro (var) = freemempos; \
447 1.14 thorpej memset((char *)(var), 0, ((np) * PAGE_SIZE)); \
448 1.14 thorpej freemempos += (np) * PAGE_SIZE;
449 1.1 ichiro
450 1.1 ichiro loop1 = 0;
451 1.1 ichiro for (loop = 0; loop <= NUM_KERNEL_PTS; ++loop) {
452 1.1 ichiro /* Are we 16KB aligned for an L1 ? */
453 1.1 ichiro if (((physical_freeend - L1_TABLE_SIZE) & (L1_TABLE_SIZE - 1)) == 0
454 1.1 ichiro && kernel_l1pt.pv_pa == 0) {
455 1.14 thorpej valloc_pages(kernel_l1pt, L1_TABLE_SIZE / PAGE_SIZE);
456 1.1 ichiro } else {
457 1.17 thorpej valloc_pages(kernel_pt_table[loop1],
458 1.17 thorpej L2_TABLE_SIZE / PAGE_SIZE);
459 1.1 ichiro ++loop1;
460 1.1 ichiro }
461 1.1 ichiro }
462 1.1 ichiro
463 1.1 ichiro #ifdef DIAGNOSTIC
464 1.1 ichiro /* This should never be able to happen but better confirm that. */
465 1.1 ichiro if (!kernel_l1pt.pv_pa || (kernel_l1pt.pv_pa & (L1_TABLE_SIZE-1)) != 0)
466 1.8 provos panic("initarm: Failed to align the kernel page directory");
467 1.1 ichiro #endif
468 1.1 ichiro
469 1.1 ichiro /*
470 1.1 ichiro * Allocate a page for the system page mapped to V0x00000000
471 1.1 ichiro * This page will just contain the system vectors and can be
472 1.1 ichiro * shared by all processes.
473 1.1 ichiro */
474 1.1 ichiro alloc_pages(systempage.pv_pa, 1);
475 1.1 ichiro
476 1.1 ichiro /* Allocate stacks for all modes */
477 1.1 ichiro valloc_pages(irqstack, IRQ_STACK_SIZE);
478 1.1 ichiro valloc_pages(abtstack, ABT_STACK_SIZE);
479 1.1 ichiro valloc_pages(undstack, UND_STACK_SIZE);
480 1.1 ichiro valloc_pages(kernelstack, UPAGES);
481 1.1 ichiro
482 1.1 ichiro #ifdef VERBOSE_INIT_ARM
483 1.1 ichiro printf("IRQ stack: p0x%08lx v0x%08lx\n", irqstack.pv_pa, irqstack.pv_va);
484 1.1 ichiro printf("ABT stack: p0x%08lx v0x%08lx\n", abtstack.pv_pa, abtstack.pv_va);
485 1.1 ichiro printf("UND stack: p0x%08lx v0x%08lx\n", undstack.pv_pa, undstack.pv_va);
486 1.1 ichiro printf("SVC stack: p0x%08lx v0x%08lx\n", kernelstack.pv_pa, kernelstack.pv_va);
487 1.1 ichiro #endif
488 1.1 ichiro
489 1.14 thorpej alloc_pages(msgbufphys, round_page(MSGBUFSIZE) / PAGE_SIZE);
490 1.1 ichiro
491 1.1 ichiro #ifdef CPU_IXP12X0
492 1.1 ichiro /*
493 1.1 ichiro * XXX totally stuffed hack to work round problems introduced
494 1.1 ichiro * in recent versions of the pmap code. Due to the calls used there
495 1.1 ichiro * we cannot allocate virtual memory during bootstrap.
496 1.1 ichiro */
497 1.1 ichiro for(;;) {
498 1.1 ichiro alloc_pages(ixp12x0_cc_base, 1);
499 1.1 ichiro if (! (ixp12x0_cc_base & (CPU_IXP12X0_CACHE_CLEAN_SIZE - 1)))
500 1.1 ichiro break;
501 1.1 ichiro }
502 1.1 ichiro {
503 1.1 ichiro vaddr_t dummy;
504 1.14 thorpej alloc_pages(dummy, CPU_IXP12X0_CACHE_CLEAN_SIZE / PAGE_SIZE - 1);
505 1.1 ichiro }
506 1.1 ichiro ixp12x0_cache_clean_addr = ixp12x0_cc_base;
507 1.1 ichiro ixp12x0_cache_clean_size = CPU_IXP12X0_CACHE_CLEAN_SIZE / 2;
508 1.1 ichiro #endif /* CPU_IXP12X0 */
509 1.1 ichiro
510 1.1 ichiro #ifdef VERBOSE_INIT_ARM
511 1.1 ichiro printf("Creating L1 page table at 0x%08lx\n", kernel_l1pt.pv_pa);
512 1.1 ichiro #endif
513 1.1 ichiro
514 1.1 ichiro /*
515 1.1 ichiro * Now we start construction of the L1 page table
516 1.1 ichiro * We start by mapping the L2 page tables into the L1.
517 1.1 ichiro * This means that we can replace L1 mappings later on if necessary
518 1.1 ichiro */
519 1.1 ichiro l1pagetable = kernel_l1pt.pv_pa;
520 1.1 ichiro
521 1.1 ichiro /* Map the L2 pages tables in the L1 page table */
522 1.21 igy pmap_link_l2pt(l1pagetable, ARM_VECTORS_HIGH & ~(0x00400000 - 1),
523 1.1 ichiro &kernel_pt_table[KERNEL_PT_SYS]);
524 1.1 ichiro
525 1.1 ichiro for (loop = 0; loop < KERNEL_PT_KERNEL_NUM; loop++)
526 1.1 ichiro pmap_link_l2pt(l1pagetable, KERNEL_BASE + loop * 0x00400000,
527 1.1 ichiro &kernel_pt_table[KERNEL_PT_KERNEL + loop]);
528 1.1 ichiro
529 1.1 ichiro for (loop = 0; loop < KERNEL_PT_VMDATA_NUM; loop++)
530 1.1 ichiro pmap_link_l2pt(l1pagetable, KERNEL_VM_BASE + loop * 0x00400000,
531 1.1 ichiro &kernel_pt_table[KERNEL_PT_VMDATA + loop]);
532 1.1 ichiro
533 1.1 ichiro /* update the top of the kernel VM */
534 1.1 ichiro pmap_curmaxkvaddr =
535 1.1 ichiro KERNEL_VM_BASE + (KERNEL_PT_VMDATA_NUM * 0x00400000);
536 1.1 ichiro
537 1.1 ichiro pmap_link_l2pt(l1pagetable, IXP12X0_IO_VBASE,
538 1.1 ichiro &kernel_pt_table[KERNEL_PT_IO]);
539 1.1 ichiro
540 1.1 ichiro #ifdef VERBOSE_INIT_ARM
541 1.1 ichiro printf("Mapping kernel\n");
542 1.1 ichiro #endif
543 1.1 ichiro
544 1.1 ichiro #if XXX
545 1.1 ichiro /* Now we fill in the L2 pagetable for the kernel code/data */
546 1.1 ichiro {
547 1.1 ichiro extern char etext[], _end[];
548 1.1 ichiro size_t textsize = (uintptr_t) etext - KERNEL_TEXT_BASE;
549 1.1 ichiro size_t totalsize = (uintptr_t) _end - KERNEL_TEXT_BASE;
550 1.1 ichiro u_int logical;
551 1.1 ichiro
552 1.1 ichiro textsize = (textsize + PGOFSET) & ~PGOFSET;
553 1.1 ichiro totalsize = (totalsize + PGOFSET) & ~PGOFSET;
554 1.1 ichiro
555 1.1 ichiro logical = 0x00200000; /* offset of kernel in RAM */
556 1.1 ichiro
557 1.1 ichiro logical += pmap_map_chunk(l1pagetable, KERNEL_BASE + logical,
558 1.1 ichiro physical_start + logical, textsize,
559 1.1 ichiro VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE);
560 1.1 ichiro logical += pmap_map_chunk(l1pagetable, KERNEL_BASE + logical,
561 1.1 ichiro physical_start + logical, totalsize - textsize,
562 1.1 ichiro VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE);
563 1.1 ichiro }
564 1.1 ichiro #else
565 1.1 ichiro {
566 1.1 ichiro pmap_map_chunk(l1pagetable, KERNEL_TEXT_BASE,
567 1.1 ichiro KERNEL_TEXT_BASE, kerneldatasize,
568 1.1 ichiro VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE);
569 1.1 ichiro }
570 1.1 ichiro #endif
571 1.1 ichiro
572 1.1 ichiro #ifdef VERBOSE_INIT_ARM
573 1.1 ichiro printf("Constructing L2 page tables\n");
574 1.1 ichiro #endif
575 1.1 ichiro
576 1.1 ichiro /* Map the stack pages */
577 1.1 ichiro pmap_map_chunk(l1pagetable, irqstack.pv_va, irqstack.pv_pa,
578 1.14 thorpej IRQ_STACK_SIZE * PAGE_SIZE, VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE);
579 1.1 ichiro pmap_map_chunk(l1pagetable, abtstack.pv_va, abtstack.pv_pa,
580 1.14 thorpej ABT_STACK_SIZE * PAGE_SIZE, VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE);
581 1.1 ichiro pmap_map_chunk(l1pagetable, undstack.pv_va, undstack.pv_pa,
582 1.14 thorpej UND_STACK_SIZE * PAGE_SIZE, VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE);
583 1.1 ichiro pmap_map_chunk(l1pagetable, kernelstack.pv_va, kernelstack.pv_pa,
584 1.14 thorpej UPAGES * PAGE_SIZE, VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE);
585 1.1 ichiro
586 1.17 thorpej pmap_map_chunk(l1pagetable, kernel_l1pt.pv_va, kernel_l1pt.pv_pa,
587 1.17 thorpej L1_TABLE_SIZE, VM_PROT_READ|VM_PROT_WRITE, PTE_PAGETABLE);
588 1.1 ichiro
589 1.17 thorpej for (loop = 0; loop < NUM_KERNEL_PTS; ++loop) {
590 1.17 thorpej pmap_map_chunk(l1pagetable, kernel_pt_table[loop].pv_va,
591 1.17 thorpej kernel_pt_table[loop].pv_pa, L2_TABLE_SIZE,
592 1.17 thorpej VM_PROT_READ|VM_PROT_WRITE, PTE_PAGETABLE);
593 1.17 thorpej }
594 1.1 ichiro
595 1.1 ichiro /* Map the vector page. */
596 1.21 igy pmap_map_entry(l1pagetable, ARM_VECTORS_HIGH, systempage.pv_pa,
597 1.1 ichiro VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE);
598 1.1 ichiro
599 1.1 ichiro #ifdef VERBOSE_INIT_ARM
600 1.1 ichiro printf("systempage (vector page): p0x%08lx v0x%08lx\n",
601 1.1 ichiro systempage.pv_pa, vector_page);
602 1.1 ichiro #endif
603 1.1 ichiro
604 1.26 igy /* Map the statically mapped devices. */
605 1.26 igy pmap_devmap_bootstrap(l1pagetable, ixm1200_devmap);
606 1.1 ichiro
607 1.23 thorpej #ifdef VERBOSE_INIT_ARM
608 1.1 ichiro printf("done.\n");
609 1.23 thorpej #endif
610 1.1 ichiro
611 1.1 ichiro /*
612 1.1 ichiro * Map the Dcache Flush page.
613 1.1 ichiro * Hw Ref Manual 3.2.4.5 Software Dcache Flush
614 1.1 ichiro */
615 1.1 ichiro pmap_map_chunk(l1pagetable, ixp12x0_cache_clean_addr, 0xe0000000,
616 1.1 ichiro CPU_IXP12X0_CACHE_CLEAN_SIZE, VM_PROT_READ, PTE_CACHE);
617 1.1 ichiro
618 1.1 ichiro /*
619 1.1 ichiro * Now we have the real page tables in place so we can switch to them.
620 1.1 ichiro * Once this is done we will be running with the REAL kernel page
621 1.1 ichiro * tables.
622 1.1 ichiro */
623 1.1 ichiro
624 1.1 ichiro /* Switch tables */
625 1.17 thorpej cpu_domains((DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL*2)) | DOMAIN_CLIENT);
626 1.1 ichiro setttb(kernel_l1pt.pv_pa);
627 1.1 ichiro cpu_tlb_flushID();
628 1.17 thorpej cpu_domains(DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL*2));
629 1.17 thorpej
630 1.17 thorpej /*
631 1.17 thorpej * Moved here from cpu_startup() as data_abort_handler() references
632 1.17 thorpej * this during init
633 1.17 thorpej */
634 1.17 thorpej proc0paddr = (struct user *)kernelstack.pv_va;
635 1.17 thorpej lwp0.l_addr = proc0paddr;
636 1.1 ichiro
637 1.1 ichiro /*
638 1.1 ichiro * We must now clean the cache again....
639 1.1 ichiro * Cleaning may be done by reading new data to displace any
640 1.1 ichiro * dirty data in the cache. This will have happened in setttb()
641 1.1 ichiro * but since we are boot strapping the addresses used for the read
642 1.1 ichiro * may have just been remapped and thus the cache could be out
643 1.1 ichiro * of sync. A re-clean after the switch will cure this.
644 1.1 ichiro * After booting there are no gross reloations of the kernel thus
645 1.1 ichiro * this problem will not occur after initarm().
646 1.1 ichiro */
647 1.1 ichiro cpu_idcache_wbinv_all();
648 1.1 ichiro
649 1.21 igy arm32_vector_init(ARM_VECTORS_HIGH, ARM_VEC_ALL);
650 1.1 ichiro
651 1.1 ichiro /*
652 1.1 ichiro * Pages were allocated during the secondary bootstrap for the
653 1.1 ichiro * stacks for different CPU modes.
654 1.1 ichiro * We must now set the r13 registers in the different CPU modes to
655 1.1 ichiro * point to these stacks.
656 1.1 ichiro * Since the ARM stacks use STMFD etc. we must set r13 to the top end
657 1.1 ichiro * of the stack memory.
658 1.1 ichiro */
659 1.23 thorpej #ifdef VERBOSE_INIT_ARM
660 1.1 ichiro printf("init subsystems: stacks ");
661 1.23 thorpej #endif
662 1.1 ichiro
663 1.14 thorpej set_stackptr(PSR_IRQ32_MODE,
664 1.14 thorpej irqstack.pv_va + IRQ_STACK_SIZE * PAGE_SIZE);
665 1.14 thorpej set_stackptr(PSR_ABT32_MODE,
666 1.14 thorpej abtstack.pv_va + ABT_STACK_SIZE * PAGE_SIZE);
667 1.14 thorpej set_stackptr(PSR_UND32_MODE,
668 1.14 thorpej undstack.pv_va + UND_STACK_SIZE * PAGE_SIZE);
669 1.1 ichiro #ifdef PMAP_DEBUG
670 1.1 ichiro if (pmap_debug_level >= 0)
671 1.1 ichiro printf("kstack V%08lx P%08lx\n", kernelstack.pv_va,
672 1.1 ichiro kernelstack.pv_pa);
673 1.1 ichiro #endif /* PMAP_DEBUG */
674 1.1 ichiro
675 1.1 ichiro /*
676 1.1 ichiro * Well we should set a data abort handler.
677 1.1 ichiro * Once things get going this will change as we will need a proper
678 1.1 ichiro * handler. Until then we will use a handler that just panics but
679 1.1 ichiro * tells us why.
680 1.1 ichiro * Initialisation of the vetcors will just panic on a data abort.
681 1.30 abs * This just fills in a slightly better one.
682 1.1 ichiro */
683 1.23 thorpej #ifdef VERBOSE_INIT_ARM
684 1.1 ichiro printf("vectors ");
685 1.23 thorpej #endif
686 1.1 ichiro data_abort_handler_address = (u_int)data_abort_handler;
687 1.1 ichiro prefetch_abort_handler_address = (u_int)prefetch_abort_handler;
688 1.1 ichiro undefined_handler_address = (u_int)undefinedinstruction_bounce;
689 1.23 thorpej #ifdef VERBOSE_INIT_ARM
690 1.1 ichiro printf("\ndata_abort_handler_address = %08x\n", data_abort_handler_address);
691 1.1 ichiro printf("prefetch_abort_handler_address = %08x\n", prefetch_abort_handler_address);
692 1.1 ichiro printf("undefined_handler_address = %08x\n", undefined_handler_address);
693 1.23 thorpej #endif
694 1.1 ichiro
695 1.1 ichiro /* Initialise the undefined instruction handlers */
696 1.23 thorpej #ifdef VERBOSE_INIT_ARM
697 1.1 ichiro printf("undefined ");
698 1.23 thorpej #endif
699 1.1 ichiro undefined_init();
700 1.1 ichiro
701 1.4 thorpej /* Load memory into UVM. */
702 1.23 thorpej #ifdef VERBOSE_INIT_ARM
703 1.4 thorpej printf("page ");
704 1.23 thorpej #endif
705 1.4 thorpej uvm_setpagesize(); /* initialize PAGE_SIZE-dependent variables */
706 1.4 thorpej uvm_page_physload(atop(physical_freestart), atop(physical_freeend),
707 1.4 thorpej atop(physical_freestart), atop(physical_freeend),
708 1.4 thorpej VM_FREELIST_DEFAULT);
709 1.4 thorpej
710 1.1 ichiro /* Boot strap pmap telling it where the kernel page table is */
711 1.23 thorpej #ifdef VERBOSE_INIT_ARM
712 1.1 ichiro printf("pmap ");
713 1.23 thorpej #endif
714 1.34 matt pmap_bootstrap(KERNEL_VM_BASE, KERNEL_VM_BASE + KERNEL_VM_SIZE);
715 1.1 ichiro
716 1.1 ichiro /* Setup the IRQ system */
717 1.23 thorpej #ifdef VERBOSE_INIT_ARM
718 1.1 ichiro printf("irq ");
719 1.23 thorpej #endif
720 1.1 ichiro ixp12x0_intr_init();
721 1.23 thorpej
722 1.23 thorpej #ifdef VERBOSE_INIT_ARM
723 1.1 ichiro printf("done.\n");
724 1.23 thorpej #endif
725 1.1 ichiro
726 1.1 ichiro #ifdef VERBOSE_INIT_ARM
727 1.1 ichiro printf("freestart = 0x%08lx, free_pages = %d (0x%x)\n",
728 1.1 ichiro physical_freestart, free_pages, free_pages);
729 1.1 ichiro printf("freemempos=%08lx\n", freemempos);
730 1.1 ichiro printf("switching to new L1 page table @%#lx... \n", kernel_l1pt.pv_pa);
731 1.1 ichiro #endif
732 1.1 ichiro
733 1.1 ichiro consinit();
734 1.23 thorpej #ifdef VERBOSE_INIT_ARM
735 1.1 ichiro printf("consinit \n");
736 1.23 thorpej #endif
737 1.1 ichiro
738 1.1 ichiro ixdp_ixp12x0_cc_setup();
739 1.1 ichiro
740 1.23 thorpej #ifdef VERBOSE_INIT_ARM
741 1.1 ichiro printf("bootstrap done.\n");
742 1.23 thorpej #endif
743 1.1 ichiro
744 1.15 ragge #if NKSYMS || defined(DDB) || defined(LKM)
745 1.16 ragge ksyms_init(symbolsize, ((int *)&end), ((char *)&end) + symbolsize);
746 1.15 ragge #endif
747 1.15 ragge
748 1.1 ichiro #ifdef DDB
749 1.29 rearnsha db_machine_init();
750 1.1 ichiro if (boothowto & RB_KDB)
751 1.1 ichiro Debugger();
752 1.1 ichiro #endif
753 1.1 ichiro
754 1.1 ichiro /* We return the new stack pointer address */
755 1.1 ichiro return(kernelstack.pv_va + USPACE_SVC_STACK_TOP);
756 1.1 ichiro }
757 1.1 ichiro
758 1.1 ichiro void
759 1.1 ichiro consinit(void)
760 1.1 ichiro {
761 1.1 ichiro static int consinit_called = 0;
762 1.1 ichiro
763 1.1 ichiro if (consinit_called != 0)
764 1.1 ichiro return;
765 1.1 ichiro
766 1.1 ichiro consinit_called = 1;
767 1.26 igy
768 1.26 igy pmap_devmap_register(ixm1200_devmap);
769 1.1 ichiro
770 1.27 igy if (ixpcomcnattach(&ixp12x0_bs_tag,
771 1.12 igy IXPCOM_UART_HWBASE, IXPCOM_UART_VBASE,
772 1.1 ichiro CONSPEED, CONMODE))
773 1.12 igy panic("can't init serial console @%lx", IXPCOM_UART_HWBASE);
774 1.1 ichiro }
775 1.1 ichiro
776 1.1 ichiro /*
777 1.1 ichiro * For optimal cache cleaning we need two 16K banks of
778 1.1 ichiro * virtual address space that NOTHING else will access
779 1.1 ichiro * and then we alternate the cache cleaning between the
780 1.1 ichiro * two banks.
781 1.1 ichiro * The cache cleaning code requires requires 2 banks aligned
782 1.1 ichiro * on total size boundry so the banks can be alternated by
783 1.1 ichiro * eorring the size bit (assumes the bank size is a power of 2)
784 1.1 ichiro */
785 1.1 ichiro void
786 1.1 ichiro ixdp_ixp12x0_cc_setup(void)
787 1.1 ichiro {
788 1.1 ichiro int loop;
789 1.1 ichiro paddr_t kaddr;
790 1.1 ichiro pt_entry_t *pte;
791 1.1 ichiro
792 1.1 ichiro (void) pmap_extract(pmap_kernel(), KERNEL_TEXT_BASE, &kaddr);
793 1.14 thorpej for (loop = 0; loop < CPU_IXP12X0_CACHE_CLEAN_SIZE; loop += PAGE_SIZE) {
794 1.1 ichiro pte = vtopte(ixp12x0_cc_base + loop);
795 1.1 ichiro *pte = L2_S_PROTO | kaddr |
796 1.1 ichiro L2_S_PROT(PTE_KERNEL, VM_PROT_READ) | pte_l2_s_cache_mode;
797 1.6 thorpej PTE_SYNC(pte);
798 1.1 ichiro }
799 1.1 ichiro ixp12x0_cache_clean_addr = ixp12x0_cc_base;
800 1.1 ichiro ixp12x0_cache_clean_size = CPU_IXP12X0_CACHE_CLEAN_SIZE / 2;
801 1.1 ichiro }
802