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ixm1200_machdep.c revision 1.55
      1  1.55      matt /*	$NetBSD: ixm1200_machdep.c,v 1.55 2014/02/22 19:03:57 matt Exp $ */
      2  1.22       igy 
      3   1.1    ichiro /*
      4  1.12       igy  * Copyright (c) 2002, 2003
      5   1.1    ichiro  *	Ichiro FUKUHARA <ichiro (at) ichiro.org>.
      6   1.1    ichiro  * All rights reserved.
      7   1.1    ichiro  *
      8   1.1    ichiro  * Redistribution and use in source and binary forms, with or without
      9   1.1    ichiro  * modification, are permitted provided that the following conditions
     10   1.1    ichiro  * are met:
     11   1.1    ichiro  * 1. Redistributions of source code must retain the above copyright
     12   1.1    ichiro  *    notice, this list of conditions and the following disclaimer.
     13   1.1    ichiro  * 2. Redistributions in binary form must reproduce the above copyright
     14   1.1    ichiro  *    notice, this list of conditions and the following disclaimer in the
     15   1.1    ichiro  *    documentation and/or other materials provided with the distribution.
     16   1.1    ichiro  *
     17   1.1    ichiro  * THIS SOFTWARE IS PROVIDED BY ICHIRO FUKUHARA ``AS IS'' AND ANY EXPRESS OR
     18   1.1    ichiro  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
     19   1.1    ichiro  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
     20   1.1    ichiro  * IN NO EVENT SHALL ICHIRO FUKUHARA OR THE VOICES IN HIS HEAD BE LIABLE FOR
     21   1.1    ichiro  * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
     22   1.1    ichiro  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
     23   1.1    ichiro  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
     24   1.1    ichiro  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
     25   1.1    ichiro  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
     26   1.1    ichiro  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
     27   1.1    ichiro  * SUCH DAMAGE.
     28   1.1    ichiro  */
     29   1.1    ichiro /*
     30   1.1    ichiro  * Copyright (c) 1997,1998 Mark Brinicombe.
     31   1.1    ichiro  * Copyright (c) 1997,1998 Causality Limited.
     32   1.1    ichiro  * All rights reserved.
     33   1.1    ichiro  *
     34   1.1    ichiro  * Redistribution and use in source and binary forms, with or without
     35   1.1    ichiro  * modification, are permitted provided that the following conditions
     36   1.1    ichiro  * are met:
     37   1.1    ichiro  * 1. Redistributions of source code must retain the above copyright
     38   1.1    ichiro  *    notice, this list of conditions and the following disclaimer.
     39   1.1    ichiro  * 2. Redistributions in binary form must reproduce the above copyright
     40   1.1    ichiro  *    notice, this list of conditions and the following disclaimer in the
     41   1.1    ichiro  *    documentation and/or other materials provided with the distribution.
     42   1.1    ichiro  * 3. All advertising materials mentioning features or use of this software
     43   1.1    ichiro  *    must display the following acknowledgement:
     44   1.1    ichiro  *      This product includes software developed by Mark Brinicombe
     45   1.1    ichiro  *      for the NetBSD Project.
     46   1.1    ichiro  * 4. The name of the company nor the name of the author may be used to
     47   1.1    ichiro  *    endorse or promote products derived from this software without specific
     48   1.1    ichiro  *    prior written permission.
     49   1.1    ichiro  *
     50   1.1    ichiro  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
     51   1.1    ichiro  * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
     52   1.1    ichiro  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
     53   1.1    ichiro  * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
     54   1.1    ichiro  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
     55   1.1    ichiro  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
     56   1.1    ichiro  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
     57   1.1    ichiro  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
     58   1.1    ichiro  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
     59   1.1    ichiro  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
     60   1.1    ichiro  * SUCH DAMAGE.
     61   1.1    ichiro  */
     62  1.13       igy 
     63  1.13       igy #include <sys/cdefs.h>
     64  1.55      matt __KERNEL_RCSID(0, "$NetBSD: ixm1200_machdep.c,v 1.55 2014/02/22 19:03:57 matt Exp $");
     65   1.1    ichiro 
     66   1.1    ichiro #include "opt_ddb.h"
     67  1.38       apb #include "opt_modular.h"
     68   1.1    ichiro #include "opt_pmap_debug.h"
     69   1.1    ichiro 
     70   1.1    ichiro #include <sys/param.h>
     71   1.1    ichiro #include <sys/device.h>
     72   1.1    ichiro #include <sys/systm.h>
     73   1.1    ichiro #include <sys/kernel.h>
     74   1.1    ichiro #include <sys/exec.h>
     75   1.1    ichiro #include <sys/proc.h>
     76   1.1    ichiro #include <sys/msgbuf.h>
     77   1.1    ichiro #include <sys/reboot.h>
     78   1.1    ichiro #include <sys/termios.h>
     79  1.15     ragge #include <sys/ksyms.h>
     80  1.54      matt #include <sys/bus.h>
     81  1.54      matt #include <sys/cpu.h>
     82   1.1    ichiro 
     83  1.14   thorpej #include <uvm/uvm_extern.h>
     84  1.14   thorpej 
     85   1.1    ichiro #include <dev/cons.h>
     86   1.1    ichiro 
     87  1.15     ragge #include "ksyms.h"
     88  1.15     ragge 
     89  1.36        ad #if NKSYMS || defined(DDB) || defined(MODULAR)
     90   1.1    ichiro #include <machine/db_machdep.h>
     91   1.1    ichiro #include <ddb/db_sym.h>
     92   1.1    ichiro #include <ddb/db_extern.h>
     93   1.1    ichiro #ifndef DB_ELFSIZE
     94   1.1    ichiro #error Must define DB_ELFSIZE!
     95   1.1    ichiro #endif
     96   1.1    ichiro #define ELFSIZE	DB_ELFSIZE
     97   1.1    ichiro #include <sys/exec_elf.h>
     98   1.1    ichiro #endif
     99   1.1    ichiro 
    100   1.1    ichiro #include <machine/bootconfig.h>
    101  1.54      matt #include <arm/locore.h>
    102   1.1    ichiro #include <arm/undefined.h>
    103   1.1    ichiro 
    104   1.1    ichiro #include <arm/arm32/machdep.h>
    105   1.1    ichiro 
    106   1.1    ichiro #include <arm/ixp12x0/ixp12x0reg.h>
    107   1.1    ichiro #include <arm/ixp12x0/ixp12x0var.h>
    108   1.1    ichiro #include <arm/ixp12x0/ixp12x0_comreg.h>
    109   1.1    ichiro #include <arm/ixp12x0/ixp12x0_comvar.h>
    110   1.1    ichiro #include <arm/ixp12x0/ixp12x0_pcireg.h>
    111   1.1    ichiro 
    112   1.1    ichiro #include <evbarm/ixm1200/ixm1200reg.h>
    113   1.1    ichiro #include <evbarm/ixm1200/ixm1200var.h>
    114   1.1    ichiro 
    115   1.1    ichiro /* XXX for consinit related hacks */
    116   1.1    ichiro #include <sys/conf.h>
    117   1.1    ichiro 
    118   1.1    ichiro void ixp12x0_reset(void) __attribute__((noreturn));
    119  1.20   thorpej 
    120  1.20   thorpej /* Kernel text starts 2MB in from the bottom of the kernel address space. */
    121  1.20   thorpej #define	KERNEL_TEXT_BASE	(KERNEL_BASE + 0x00200000)
    122  1.24   thorpej #define	KERNEL_VM_BASE		(KERNEL_BASE + 0x01000000)
    123  1.25   thorpej 
    124  1.25   thorpej /*
    125  1.25   thorpej  * The range 0xc1000000 - 0xccffffff is available for kernel VM space
    126  1.25   thorpej  * Core-logic registers and I/O mappings occupy 0xfd000000 - 0xffffffff
    127  1.25   thorpej  */
    128  1.25   thorpej #define KERNEL_VM_SIZE		0x0C000000
    129   1.1    ichiro 
    130   1.1    ichiro /*
    131   1.1    ichiro  * Address to call from cpu_reset() to reset the machine.
    132  1.48       wiz  * This is machine architecture dependent as it varies depending
    133   1.1    ichiro  * on where the ROM appears when you turn the MMU off.
    134   1.1    ichiro  */
    135   1.1    ichiro 
    136   1.1    ichiro /*
    137   1.1    ichiro  * Define the default console speed for the board.
    138   1.1    ichiro  */
    139   1.1    ichiro #ifndef CONMODE
    140   1.1    ichiro #define CONMODE ((TTYDEF_CFLAG & ~(CSIZE | CSTOPB)) | CS8) /* 8N1 */
    141   1.1    ichiro #endif
    142   1.1    ichiro #ifndef CONSPEED
    143   1.1    ichiro #define CONSPEED B38400
    144   1.1    ichiro #endif
    145   1.1    ichiro #ifndef CONADDR
    146   1.1    ichiro #define CONADDR IXPCOM_UART_BASE
    147   1.1    ichiro #endif
    148   1.1    ichiro 
    149   1.1    ichiro BootConfig bootconfig;          /* Boot config storage */
    150   1.1    ichiro char *boot_args = NULL;
    151   1.1    ichiro char *boot_file = NULL;
    152   1.1    ichiro 
    153   1.1    ichiro vm_offset_t physical_start;
    154   1.1    ichiro vm_offset_t physical_freestart;
    155   1.1    ichiro vm_offset_t physical_freeend;
    156   1.1    ichiro vm_offset_t physical_end;
    157   1.1    ichiro u_int free_pages;
    158   1.1    ichiro 
    159   1.1    ichiro /*int debug_flags;*/
    160   1.1    ichiro #ifndef PMAP_STATIC_L1S
    161   1.1    ichiro int max_processes = 64;                 /* Default number */
    162   1.1    ichiro #endif  /* !PMAP_STATIC_L1S */
    163   1.1    ichiro 
    164   1.1    ichiro vm_offset_t msgbufphys;
    165   1.1    ichiro 
    166   1.1    ichiro extern int end;
    167   1.1    ichiro 
    168   1.1    ichiro #ifdef PMAP_DEBUG
    169   1.1    ichiro extern int pmap_debug_level;
    170   1.1    ichiro #endif  /* PMAP_DEBUG */
    171   1.1    ichiro 
    172   1.1    ichiro #define KERNEL_PT_SYS		0	/* Page table for mapping proc0 zero page */
    173   1.1    ichiro #define KERNEL_PT_KERNEL	1	/* Page table for mapping kernel */
    174   1.1    ichiro #define KERNEL_PT_KERNEL_NUM	2
    175   1.1    ichiro #define KERNEL_PT_IO		(KERNEL_PT_KERNEL + KERNEL_PT_KERNEL_NUM)
    176   1.1    ichiro 					/* Page table for mapping IO */
    177   1.1    ichiro #define KERNEL_PT_VMDATA	(KERNEL_PT_IO + 1)
    178   1.1    ichiro 					/* Page tables for mapping kernel VM */
    179   1.1    ichiro #define KERNEL_PT_VMDATA_NUM	4	/* start with 16MB of KVM */
    180   1.1    ichiro #define NUM_KERNEL_PTS		(KERNEL_PT_VMDATA + KERNEL_PT_VMDATA_NUM)
    181   1.1    ichiro 
    182   1.1    ichiro pv_addr_t kernel_pt_table[NUM_KERNEL_PTS];
    183   1.1    ichiro 
    184   1.1    ichiro #ifdef CPU_IXP12X0
    185   1.1    ichiro #define CPU_IXP12X0_CACHE_CLEAN_SIZE (0x4000 * 2)
    186   1.1    ichiro extern unsigned int ixp12x0_cache_clean_addr;
    187   1.1    ichiro extern unsigned int ixp12x0_cache_clean_size;
    188   1.1    ichiro static vaddr_t ixp12x0_cc_base;
    189   1.1    ichiro #endif  /* CPU_IXP12X0 */
    190   1.1    ichiro 
    191   1.1    ichiro /* Prototypes */
    192   1.1    ichiro 
    193  1.39       dsl void consinit(void);
    194  1.39       dsl u_int cpu_get_control(void);
    195   1.1    ichiro 
    196   1.1    ichiro void ixdp_ixp12x0_cc_setup(void);
    197   1.1    ichiro 
    198   1.1    ichiro /*
    199   1.1    ichiro  * void cpu_reboot(int howto, char *bootstr)
    200   1.1    ichiro  *
    201   1.1    ichiro  * Reboots the system
    202   1.1    ichiro  *
    203   1.1    ichiro  * Deal with any syncing, unmounting, dumping and shutdown hooks,
    204   1.1    ichiro  * then reset the CPU.
    205   1.1    ichiro  */
    206   1.1    ichiro 
    207   1.1    ichiro void
    208  1.40       dsl cpu_reboot(int howto, char *bootstr)
    209   1.1    ichiro {
    210   1.1    ichiro 	/*
    211   1.1    ichiro 	 * If we are still cold then hit the air brakes
    212   1.1    ichiro 	 * and crash to earth fast
    213   1.1    ichiro 	 */
    214   1.1    ichiro 	if (cold) {
    215   1.1    ichiro 		doshutdownhooks();
    216  1.35    dyoung 		pmf_system_shutdown(boothowto);
    217   1.1    ichiro 		printf("Halted while still in the ICE age.\n");
    218   1.1    ichiro 		printf("The operating system has halted.\n");
    219   1.1    ichiro 		printf("Please press any key to reboot.\n\n");
    220   1.1    ichiro 		cngetc();
    221   1.1    ichiro 		printf("rebooting...\n");
    222   1.1    ichiro 		ixp12x0_reset();
    223   1.1    ichiro 	}
    224   1.1    ichiro 
    225   1.1    ichiro 	/* Disable console buffering */
    226   1.1    ichiro 	cnpollc(1);
    227   1.1    ichiro 
    228   1.1    ichiro 	/*
    229   1.1    ichiro 	 * If RB_NOSYNC was not specified sync the discs.
    230   1.1    ichiro 	 * Note: Unless cold is set to 1 here, syslogd will die during the unmount.
    231   1.1    ichiro 	 * It looks like syslogd is getting woken up only to find that it cannot
    232   1.1    ichiro 	 * page part of the binary in as the filesystem has been unmounted.
    233   1.1    ichiro 	 */
    234   1.1    ichiro 	if (!(howto & RB_NOSYNC))
    235   1.1    ichiro 		bootsync();
    236   1.1    ichiro 
    237   1.1    ichiro 	/* Say NO to interrupts */
    238   1.1    ichiro 	splhigh();
    239   1.1    ichiro 
    240   1.1    ichiro 	/* Do a dump if requested. */
    241   1.1    ichiro 	if ((howto & (RB_DUMP | RB_HALT)) == RB_DUMP)
    242   1.1    ichiro 		dumpsys();
    243   1.1    ichiro 
    244   1.1    ichiro 	/* Run any shutdown hooks */
    245   1.1    ichiro 	doshutdownhooks();
    246   1.1    ichiro 
    247  1.35    dyoung 	pmf_system_shutdown(boothowto);
    248  1.35    dyoung 
    249   1.1    ichiro 	/* Make sure IRQ's are disabled */
    250   1.1    ichiro 	IRQdisable;
    251   1.1    ichiro 
    252   1.1    ichiro 	if (howto & RB_HALT) {
    253   1.1    ichiro 		printf("The operating system has halted.\n");
    254   1.1    ichiro 		printf("Please press any key to reboot.\n\n");
    255   1.1    ichiro 		cngetc();
    256   1.1    ichiro 	}
    257   1.1    ichiro 
    258   1.1    ichiro 	printf("rebooting...\n");
    259   1.1    ichiro 
    260   1.1    ichiro 	/* all interrupts are disabled */
    261   1.1    ichiro 	disable_interrupts(I32_bit);
    262   1.1    ichiro 
    263   1.1    ichiro 	ixp12x0_reset();
    264   1.1    ichiro 
    265   1.1    ichiro 	/* ...and if that didn't work, just croak. */
    266   1.1    ichiro 	printf("RESET FAILED!\n");
    267   1.1    ichiro 	for (;;);
    268   1.1    ichiro }
    269   1.1    ichiro 
    270  1.26       igy /* Static device mappings. */
    271  1.26       igy static const struct pmap_devmap ixm1200_devmap[] = {
    272  1.26       igy 	/* StrongARM System and Peripheral Registers */
    273  1.26       igy 	{
    274  1.26       igy 		IXP12X0_SYS_VBASE,
    275  1.26       igy 		IXP12X0_SYS_HWBASE,
    276  1.26       igy 		IXP12X0_SYS_SIZE,
    277  1.26       igy 		VM_PROT_READ|VM_PROT_WRITE,
    278  1.26       igy 		PTE_NOCACHE,
    279  1.26       igy 	},
    280  1.26       igy 	/* PCI Registers Accessible Through StrongARM Core */
    281  1.26       igy 	{
    282  1.26       igy 		IXP12X0_PCI_VBASE, IXP12X0_PCI_HWBASE,
    283  1.26       igy 		IXP12X0_PCI_SIZE,
    284  1.26       igy 		VM_PROT_READ|VM_PROT_WRITE,
    285  1.26       igy 		PTE_NOCACHE,
    286  1.26       igy 	},
    287  1.26       igy 	/* PCI Registers Accessible Through I/O Cycle Access */
    288  1.26       igy 	{
    289  1.26       igy 		IXP12X0_PCI_IO_VBASE, IXP12X0_PCI_IO_HWBASE,
    290  1.26       igy 		IXP12X0_PCI_IO_SIZE,
    291  1.26       igy 		VM_PROT_READ|VM_PROT_WRITE,
    292  1.26       igy 		PTE_NOCACHE,
    293  1.26       igy 	},
    294  1.26       igy 	/* PCI Type0 Configuration Space */
    295  1.26       igy 	{
    296  1.26       igy 		IXP12X0_PCI_TYPE0_VBASE, IXP12X0_PCI_TYPE0_HWBASE,
    297  1.26       igy 		IXP12X0_PCI_TYPE0_SIZE,
    298  1.26       igy 		VM_PROT_READ|VM_PROT_WRITE,
    299  1.26       igy 		PTE_NOCACHE,
    300  1.26       igy 	},
    301  1.26       igy 	/* PCI Type1 Configuration Space */
    302  1.26       igy 	{
    303  1.26       igy 		IXP12X0_PCI_TYPE1_VBASE, IXP12X0_PCI_TYPE1_HWBASE,
    304  1.26       igy 		IXP12X0_PCI_TYPE1_SIZE,
    305  1.26       igy 		VM_PROT_READ|VM_PROT_WRITE,
    306  1.26       igy 		PTE_NOCACHE,
    307  1.26       igy 	},
    308  1.26       igy 	{
    309  1.26       igy 		0,
    310  1.26       igy 		0,
    311  1.26       igy 		0,
    312  1.26       igy 		0,
    313  1.26       igy 		0
    314  1.26       igy 	},
    315  1.26       igy };
    316  1.26       igy 
    317   1.1    ichiro /*
    318   1.1    ichiro  * Initial entry point on startup. This gets called before main() is
    319   1.1    ichiro  * entered.
    320   1.1    ichiro  * It should be responsible for setting up everything that must be
    321   1.1    ichiro  * in place when main is called.
    322   1.1    ichiro  * This includes
    323   1.1    ichiro  *   Taking a copy of the boot configuration structure.
    324   1.1    ichiro  *   Initialising the physical console so characters can be printed.
    325   1.1    ichiro  *   Setting up page tables for the kernel
    326   1.1    ichiro  *   Relocating the kernel to the bottom of physical memory
    327   1.1    ichiro  */
    328   1.1    ichiro u_int
    329   1.1    ichiro initarm(void *arg)
    330   1.1    ichiro {
    331   1.1    ichiro         int loop;
    332   1.1    ichiro 	int loop1;
    333   1.1    ichiro 	u_int kerneldatasize, symbolsize;
    334   1.1    ichiro 	vaddr_t l1pagetable;
    335   1.1    ichiro 	vaddr_t freemempos;
    336  1.36        ad #if NKSYMS || defined(DDB) || defined(MODULAR)
    337   1.1    ichiro         Elf_Shdr *sh;
    338   1.1    ichiro #endif
    339   1.1    ichiro 
    340  1.51      matt 	cpu_reset_address = ixp12x0_reset;
    341  1.51      matt 
    342   1.1    ichiro         /*
    343   1.1    ichiro          * Since we map v0xf0000000 == p0x90000000, it's possible for
    344   1.1    ichiro          * us to initialize the console now.
    345   1.1    ichiro          */
    346   1.1    ichiro 	consinit();
    347   1.1    ichiro 
    348  1.23   thorpej #ifdef VERBOSE_INIT_ARM
    349   1.1    ichiro 	/* Talk to the user */
    350   1.1    ichiro 	printf("\nNetBSD/evbarm (IXM1200) booting ...\n");
    351  1.23   thorpej #endif
    352   1.1    ichiro 
    353   1.1    ichiro 	/*
    354   1.1    ichiro 	 * Heads up ... Setup the CPU / MMU / TLB functions
    355   1.1    ichiro 	 */
    356   1.1    ichiro 	if (set_cpufuncs())
    357  1.28       wiz 		panic("CPU not recognized!");
    358   1.1    ichiro 
    359   1.1    ichiro 	/* XXX overwrite bootconfig to hardcoded values */
    360   1.1    ichiro 	bootconfig.dram[0].address = 0xc0000000;
    361  1.14   thorpej 	bootconfig.dram[0].pages   = 0x10000000 / PAGE_SIZE; /* SDRAM 256MB */
    362   1.1    ichiro 	bootconfig.dramblocks = 1;
    363   1.1    ichiro 
    364  1.53     skrll 	kerneldatasize = (uint32_t)&end - (uint32_t)KERNEL_TEXT_BASE;
    365   1.1    ichiro 
    366   1.1    ichiro 	symbolsize = 0;
    367  1.10    ichiro 
    368  1.10    ichiro #ifdef PMAP_DEBUG
    369  1.10    ichiro 	pmap_debug(-1);
    370  1.10    ichiro #endif
    371  1.10    ichiro 
    372  1.36        ad #if NKSYMS || defined(DDB) || defined(MODULAR)
    373   1.1    ichiro         if (! memcmp(&end, "\177ELF", 4)) {
    374   1.1    ichiro                 sh = (Elf_Shdr *)((char *)&end + ((Elf_Ehdr *)&end)->e_shoff);
    375   1.1    ichiro                 loop = ((Elf_Ehdr *)&end)->e_shnum;
    376   1.1    ichiro                 for(; loop; loop--, sh++)
    377   1.1    ichiro                         if (sh->sh_offset > 0 &&
    378   1.1    ichiro                             (sh->sh_offset + sh->sh_size) > symbolsize)
    379   1.1    ichiro                                 symbolsize = sh->sh_offset + sh->sh_size;
    380   1.1    ichiro         }
    381   1.1    ichiro #endif
    382  1.23   thorpej #ifdef VERBOSE_INIT_ARM
    383   1.1    ichiro 	printf("kernsize=0x%x\n", kerneldatasize);
    384  1.23   thorpej #endif
    385   1.1    ichiro 	kerneldatasize += symbolsize;
    386  1.14   thorpej 	kerneldatasize = ((kerneldatasize - 1) & ~(PAGE_SIZE * 4 - 1)) + PAGE_SIZE * 8;
    387   1.1    ichiro 
    388   1.1    ichiro 	/*
    389   1.1    ichiro 	 * Set up the variables that define the availablilty of physcial
    390   1.1    ichiro 	 * memory
    391   1.1    ichiro 	 */
    392   1.1    ichiro 	physical_start = bootconfig.dram[0].address;
    393  1.14   thorpej 	physical_end = physical_start + (bootconfig.dram[0].pages * PAGE_SIZE);
    394   1.1    ichiro 
    395   1.1    ichiro 	physical_freestart = physical_start
    396   1.1    ichiro 		+ (KERNEL_TEXT_BASE - KERNEL_BASE) + kerneldatasize;
    397   1.1    ichiro 	physical_freeend = physical_end;
    398   1.1    ichiro 
    399  1.14   thorpej 	physmem = (physical_end - physical_start) / PAGE_SIZE;
    400   1.1    ichiro 
    401   1.1    ichiro 	freemempos = 0xc0000000;
    402   1.1    ichiro 
    403   1.1    ichiro #ifdef VERBOSE_INIT_ARM
    404   1.1    ichiro 	printf("Allocating page tables\n");
    405   1.1    ichiro #endif
    406  1.14   thorpej 	free_pages = (physical_freeend - physical_freestart) / PAGE_SIZE;
    407   1.1    ichiro 
    408   1.1    ichiro #ifdef VERBOSE_INIT_ARM
    409   1.1    ichiro 	printf("CP15 Register1 = 0x%08x\n", cpu_get_control());
    410   1.1    ichiro 	printf("freestart = 0x%08lx, free_pages = %d (0x%08x)\n",
    411   1.1    ichiro 		physical_freestart, free_pages, free_pages);
    412   1.1    ichiro 	printf("physical_start = 0x%08lx, physical_end = 0x%08lx\n",
    413   1.1    ichiro 		physical_start, physical_end);
    414   1.1    ichiro #endif
    415   1.1    ichiro 
    416   1.1    ichiro 	/* Define a macro to simplify memory allocation */
    417   1.1    ichiro #define valloc_pages(var, np)			\
    418   1.1    ichiro 	alloc_pages((var).pv_pa, (np));		\
    419   1.1    ichiro 	(var).pv_va = KERNEL_BASE + (var).pv_pa - physical_start;
    420   1.1    ichiro #define alloc_pages(var, np)				\
    421   1.1    ichiro 	(var) = freemempos;				\
    422  1.14   thorpej 	memset((char *)(var), 0, ((np) * PAGE_SIZE));	\
    423  1.14   thorpej 	freemempos += (np) * PAGE_SIZE;
    424   1.1    ichiro 
    425   1.1    ichiro 	loop1 = 0;
    426   1.1    ichiro 	for (loop = 0; loop <= NUM_KERNEL_PTS; ++loop) {
    427   1.1    ichiro 		/* Are we 16KB aligned for an L1 ? */
    428   1.1    ichiro 		if (((physical_freeend - L1_TABLE_SIZE) & (L1_TABLE_SIZE - 1)) == 0
    429   1.1    ichiro 		    && kernel_l1pt.pv_pa == 0) {
    430  1.14   thorpej 			valloc_pages(kernel_l1pt, L1_TABLE_SIZE / PAGE_SIZE);
    431   1.1    ichiro 		} else {
    432  1.17   thorpej 			valloc_pages(kernel_pt_table[loop1],
    433  1.17   thorpej 			    L2_TABLE_SIZE / PAGE_SIZE);
    434   1.1    ichiro 			++loop1;
    435   1.1    ichiro 		}
    436   1.1    ichiro 	}
    437   1.1    ichiro 
    438   1.1    ichiro #ifdef DIAGNOSTIC
    439   1.1    ichiro 	/* This should never be able to happen but better confirm that. */
    440   1.1    ichiro 	if (!kernel_l1pt.pv_pa || (kernel_l1pt.pv_pa & (L1_TABLE_SIZE-1)) != 0)
    441   1.8    provos 		panic("initarm: Failed to align the kernel page directory");
    442   1.1    ichiro #endif
    443   1.1    ichiro 
    444   1.1    ichiro 	/*
    445   1.1    ichiro 	 * Allocate a page for the system page mapped to V0x00000000
    446   1.1    ichiro 	 * This page will just contain the system vectors and can be
    447   1.1    ichiro 	 * shared by all processes.
    448   1.1    ichiro 	 */
    449   1.1    ichiro 	alloc_pages(systempage.pv_pa, 1);
    450   1.1    ichiro 
    451   1.1    ichiro 	/* Allocate stacks for all modes */
    452   1.1    ichiro 	valloc_pages(irqstack, IRQ_STACK_SIZE);
    453   1.1    ichiro 	valloc_pages(abtstack, ABT_STACK_SIZE);
    454   1.1    ichiro 	valloc_pages(undstack, UND_STACK_SIZE);
    455   1.1    ichiro 	valloc_pages(kernelstack, UPAGES);
    456   1.1    ichiro 
    457   1.1    ichiro #ifdef VERBOSE_INIT_ARM
    458   1.1    ichiro 	printf("IRQ stack: p0x%08lx v0x%08lx\n", irqstack.pv_pa, irqstack.pv_va);
    459   1.1    ichiro 	printf("ABT stack: p0x%08lx v0x%08lx\n", abtstack.pv_pa, abtstack.pv_va);
    460   1.1    ichiro 	printf("UND stack: p0x%08lx v0x%08lx\n", undstack.pv_pa, undstack.pv_va);
    461   1.1    ichiro 	printf("SVC stack: p0x%08lx v0x%08lx\n", kernelstack.pv_pa, kernelstack.pv_va);
    462   1.1    ichiro #endif
    463   1.1    ichiro 
    464  1.14   thorpej 	alloc_pages(msgbufphys, round_page(MSGBUFSIZE) / PAGE_SIZE);
    465   1.1    ichiro 
    466   1.1    ichiro #ifdef CPU_IXP12X0
    467   1.1    ichiro         /*
    468   1.1    ichiro          * XXX totally stuffed hack to work round problems introduced
    469   1.1    ichiro          * in recent versions of the pmap code. Due to the calls used there
    470   1.1    ichiro          * we cannot allocate virtual memory during bootstrap.
    471   1.1    ichiro          */
    472   1.1    ichiro 	for(;;) {
    473   1.1    ichiro 		alloc_pages(ixp12x0_cc_base, 1);
    474   1.1    ichiro 		if (! (ixp12x0_cc_base & (CPU_IXP12X0_CACHE_CLEAN_SIZE - 1)))
    475   1.1    ichiro 			break;
    476   1.1    ichiro 	}
    477   1.1    ichiro 	{
    478   1.1    ichiro 		vaddr_t dummy;
    479  1.14   thorpej 		alloc_pages(dummy, CPU_IXP12X0_CACHE_CLEAN_SIZE / PAGE_SIZE - 1);
    480   1.1    ichiro 	}
    481   1.1    ichiro 	ixp12x0_cache_clean_addr = ixp12x0_cc_base;
    482   1.1    ichiro 	ixp12x0_cache_clean_size = CPU_IXP12X0_CACHE_CLEAN_SIZE / 2;
    483   1.1    ichiro #endif /* CPU_IXP12X0 */
    484   1.1    ichiro 
    485   1.1    ichiro #ifdef VERBOSE_INIT_ARM
    486   1.1    ichiro 	printf("Creating L1 page table at 0x%08lx\n", kernel_l1pt.pv_pa);
    487   1.1    ichiro #endif
    488   1.1    ichiro 
    489   1.1    ichiro 	/*
    490   1.1    ichiro 	 * Now we start construction of the L1 page table
    491   1.1    ichiro 	 * We start by mapping the L2 page tables into the L1.
    492   1.1    ichiro 	 * This means that we can replace L1 mappings later on if necessary
    493   1.1    ichiro 	 */
    494   1.1    ichiro 	l1pagetable = kernel_l1pt.pv_pa;
    495   1.1    ichiro 
    496   1.1    ichiro 	/* Map the L2 pages tables in the L1 page table */
    497  1.21       igy 	pmap_link_l2pt(l1pagetable, ARM_VECTORS_HIGH & ~(0x00400000 - 1),
    498   1.1    ichiro 	    &kernel_pt_table[KERNEL_PT_SYS]);
    499   1.1    ichiro 
    500   1.1    ichiro 	for (loop = 0; loop < KERNEL_PT_KERNEL_NUM; loop++)
    501   1.1    ichiro 		pmap_link_l2pt(l1pagetable, KERNEL_BASE + loop * 0x00400000,
    502   1.1    ichiro 		    &kernel_pt_table[KERNEL_PT_KERNEL + loop]);
    503   1.1    ichiro 
    504   1.1    ichiro 	for (loop = 0; loop < KERNEL_PT_VMDATA_NUM; loop++)
    505   1.1    ichiro 		pmap_link_l2pt(l1pagetable, KERNEL_VM_BASE + loop * 0x00400000,
    506   1.1    ichiro 		    &kernel_pt_table[KERNEL_PT_VMDATA + loop]);
    507   1.1    ichiro 
    508   1.1    ichiro 	/* update the top of the kernel VM */
    509   1.1    ichiro 	pmap_curmaxkvaddr =
    510   1.1    ichiro 	    KERNEL_VM_BASE + (KERNEL_PT_VMDATA_NUM * 0x00400000);
    511   1.1    ichiro 
    512   1.1    ichiro 	pmap_link_l2pt(l1pagetable, IXP12X0_IO_VBASE,
    513   1.1    ichiro 	    &kernel_pt_table[KERNEL_PT_IO]);
    514   1.1    ichiro 
    515   1.1    ichiro #ifdef VERBOSE_INIT_ARM
    516   1.1    ichiro 	printf("Mapping kernel\n");
    517   1.1    ichiro #endif
    518   1.1    ichiro 
    519   1.1    ichiro #if XXX
    520   1.1    ichiro 	/* Now we fill in the L2 pagetable for the kernel code/data */
    521   1.1    ichiro 	{
    522   1.1    ichiro 		extern char etext[], _end[];
    523   1.1    ichiro 		size_t textsize = (uintptr_t) etext - KERNEL_TEXT_BASE;
    524   1.1    ichiro 		size_t totalsize = (uintptr_t) _end - KERNEL_TEXT_BASE;
    525   1.1    ichiro 		u_int logical;
    526   1.1    ichiro 
    527   1.1    ichiro 		textsize = (textsize + PGOFSET) & ~PGOFSET;
    528   1.1    ichiro 		totalsize = (totalsize + PGOFSET) & ~PGOFSET;
    529   1.1    ichiro 
    530   1.1    ichiro 		logical = 0x00200000;   /* offset of kernel in RAM */
    531   1.1    ichiro 
    532   1.1    ichiro 		logical += pmap_map_chunk(l1pagetable, KERNEL_BASE + logical,
    533   1.1    ichiro 		    physical_start + logical, textsize,
    534   1.1    ichiro 		    VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE);
    535   1.1    ichiro 		logical += pmap_map_chunk(l1pagetable, KERNEL_BASE + logical,
    536   1.1    ichiro 		    physical_start + logical, totalsize - textsize,
    537   1.1    ichiro 		    VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE);
    538   1.1    ichiro 	}
    539   1.1    ichiro #else
    540   1.1    ichiro 	{
    541   1.1    ichiro 		pmap_map_chunk(l1pagetable, KERNEL_TEXT_BASE,
    542   1.1    ichiro                     KERNEL_TEXT_BASE, kerneldatasize,
    543   1.1    ichiro                     VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE);
    544   1.1    ichiro 	}
    545   1.1    ichiro #endif
    546   1.1    ichiro 
    547   1.1    ichiro #ifdef VERBOSE_INIT_ARM
    548   1.1    ichiro         printf("Constructing L2 page tables\n");
    549   1.1    ichiro #endif
    550   1.1    ichiro 
    551   1.1    ichiro 	/* Map the stack pages */
    552   1.1    ichiro 	pmap_map_chunk(l1pagetable, irqstack.pv_va, irqstack.pv_pa,
    553  1.14   thorpej 	    IRQ_STACK_SIZE * PAGE_SIZE, VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE);
    554   1.1    ichiro 	pmap_map_chunk(l1pagetable, abtstack.pv_va, abtstack.pv_pa,
    555  1.14   thorpej 	    ABT_STACK_SIZE * PAGE_SIZE, VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE);
    556   1.1    ichiro 	pmap_map_chunk(l1pagetable, undstack.pv_va, undstack.pv_pa,
    557  1.14   thorpej 	    UND_STACK_SIZE * PAGE_SIZE, VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE);
    558   1.1    ichiro 	pmap_map_chunk(l1pagetable, kernelstack.pv_va, kernelstack.pv_pa,
    559  1.14   thorpej 	    UPAGES * PAGE_SIZE, VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE);
    560   1.1    ichiro 
    561  1.17   thorpej 	pmap_map_chunk(l1pagetable, kernel_l1pt.pv_va, kernel_l1pt.pv_pa,
    562  1.17   thorpej 	    L1_TABLE_SIZE, VM_PROT_READ|VM_PROT_WRITE, PTE_PAGETABLE);
    563   1.1    ichiro 
    564  1.17   thorpej 	for (loop = 0; loop < NUM_KERNEL_PTS; ++loop) {
    565  1.17   thorpej 		pmap_map_chunk(l1pagetable, kernel_pt_table[loop].pv_va,
    566  1.17   thorpej 		    kernel_pt_table[loop].pv_pa, L2_TABLE_SIZE,
    567  1.17   thorpej 		    VM_PROT_READ|VM_PROT_WRITE, PTE_PAGETABLE);
    568  1.17   thorpej 	}
    569   1.1    ichiro 
    570   1.1    ichiro 	/* Map the vector page. */
    571  1.21       igy 	pmap_map_entry(l1pagetable, ARM_VECTORS_HIGH, systempage.pv_pa,
    572   1.1    ichiro 	    VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE);
    573   1.1    ichiro 
    574   1.1    ichiro #ifdef VERBOSE_INIT_ARM
    575   1.1    ichiro 	printf("systempage (vector page): p0x%08lx v0x%08lx\n",
    576   1.1    ichiro 	       systempage.pv_pa, vector_page);
    577   1.1    ichiro #endif
    578   1.1    ichiro 
    579  1.26       igy 	/* Map the statically mapped devices. */
    580  1.26       igy 	pmap_devmap_bootstrap(l1pagetable, ixm1200_devmap);
    581   1.1    ichiro 
    582  1.23   thorpej #ifdef VERBOSE_INIT_ARM
    583   1.1    ichiro 	printf("done.\n");
    584  1.23   thorpej #endif
    585   1.1    ichiro 
    586   1.1    ichiro 	/*
    587   1.1    ichiro 	 * Map the Dcache Flush page.
    588   1.1    ichiro 	 * Hw Ref Manual 3.2.4.5 Software Dcache Flush
    589   1.1    ichiro 	 */
    590   1.1    ichiro 	pmap_map_chunk(l1pagetable, ixp12x0_cache_clean_addr, 0xe0000000,
    591   1.1    ichiro 	    CPU_IXP12X0_CACHE_CLEAN_SIZE, VM_PROT_READ, PTE_CACHE);
    592   1.1    ichiro 
    593   1.1    ichiro 	/*
    594   1.1    ichiro 	 * Now we have the real page tables in place so we can switch to them.
    595   1.1    ichiro 	 * Once this is done we will be running with the REAL kernel page
    596   1.1    ichiro 	 * tables.
    597   1.1    ichiro 	 */
    598   1.1    ichiro 
    599   1.1    ichiro 	/* Switch tables */
    600  1.17   thorpej 	cpu_domains((DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL*2)) | DOMAIN_CLIENT);
    601  1.52      matt 	cpu_setttb(kernel_l1pt.pv_pa, true);
    602   1.1    ichiro 	cpu_tlb_flushID();
    603  1.17   thorpej 	cpu_domains(DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL*2));
    604  1.17   thorpej 
    605  1.17   thorpej 	/*
    606  1.17   thorpej 	 * Moved here from cpu_startup() as data_abort_handler() references
    607  1.17   thorpej 	 * this during init
    608  1.17   thorpej 	 */
    609  1.44     rmind 	uvm_lwp_setuarea(&lwp0, kernelstack.pv_va);
    610   1.1    ichiro 
    611   1.1    ichiro 	/*
    612   1.1    ichiro 	 * We must now clean the cache again....
    613   1.1    ichiro 	 * Cleaning may be done by reading new data to displace any
    614  1.47  uebayasi 	 * dirty data in the cache. This will have happened in cpu_setttb()
    615   1.1    ichiro 	 * but since we are boot strapping the addresses used for the read
    616   1.1    ichiro 	 * may have just been remapped and thus the cache could be out
    617   1.1    ichiro 	 * of sync. A re-clean after the switch will cure this.
    618   1.1    ichiro 	 * After booting there are no gross reloations of the kernel thus
    619   1.1    ichiro 	 * this problem will not occur after initarm().
    620   1.1    ichiro 	 */
    621   1.1    ichiro 	cpu_idcache_wbinv_all();
    622   1.1    ichiro 
    623  1.21       igy 	arm32_vector_init(ARM_VECTORS_HIGH, ARM_VEC_ALL);
    624   1.1    ichiro 
    625   1.1    ichiro 	/*
    626   1.1    ichiro 	 * Pages were allocated during the secondary bootstrap for the
    627   1.1    ichiro 	 * stacks for different CPU modes.
    628   1.1    ichiro 	 * We must now set the r13 registers in the different CPU modes to
    629   1.1    ichiro 	 * point to these stacks.
    630   1.1    ichiro 	 * Since the ARM stacks use STMFD etc. we must set r13 to the top end
    631   1.1    ichiro 	 * of the stack memory.
    632   1.1    ichiro 	 */
    633  1.23   thorpej #ifdef VERBOSE_INIT_ARM
    634   1.1    ichiro 	printf("init subsystems: stacks ");
    635  1.23   thorpej #endif
    636   1.1    ichiro 
    637  1.14   thorpej 	set_stackptr(PSR_IRQ32_MODE,
    638  1.14   thorpej 	    irqstack.pv_va + IRQ_STACK_SIZE * PAGE_SIZE);
    639  1.14   thorpej 	set_stackptr(PSR_ABT32_MODE,
    640  1.14   thorpej 	    abtstack.pv_va + ABT_STACK_SIZE * PAGE_SIZE);
    641  1.14   thorpej 	set_stackptr(PSR_UND32_MODE,
    642  1.14   thorpej 	    undstack.pv_va + UND_STACK_SIZE * PAGE_SIZE);
    643   1.1    ichiro #ifdef PMAP_DEBUG
    644   1.1    ichiro 	if (pmap_debug_level >= 0)
    645   1.1    ichiro 		printf("kstack V%08lx P%08lx\n", kernelstack.pv_va,
    646   1.1    ichiro 		    kernelstack.pv_pa);
    647   1.1    ichiro #endif  /* PMAP_DEBUG */
    648   1.1    ichiro 
    649   1.1    ichiro 	/*
    650   1.1    ichiro 	 * Well we should set a data abort handler.
    651   1.1    ichiro 	 * Once things get going this will change as we will need a proper
    652   1.1    ichiro 	 * handler. Until then we will use a handler that just panics but
    653   1.1    ichiro 	 * tells us why.
    654   1.1    ichiro 	 * Initialisation of the vetcors will just panic on a data abort.
    655  1.30       abs 	 * This just fills in a slightly better one.
    656   1.1    ichiro 	 */
    657  1.23   thorpej #ifdef VERBOSE_INIT_ARM
    658   1.1    ichiro 	printf("vectors ");
    659  1.23   thorpej #endif
    660   1.1    ichiro 	data_abort_handler_address = (u_int)data_abort_handler;
    661   1.1    ichiro 	prefetch_abort_handler_address = (u_int)prefetch_abort_handler;
    662   1.1    ichiro 	undefined_handler_address = (u_int)undefinedinstruction_bounce;
    663  1.23   thorpej #ifdef VERBOSE_INIT_ARM
    664   1.1    ichiro 	printf("\ndata_abort_handler_address = %08x\n", data_abort_handler_address);
    665   1.1    ichiro 	printf("prefetch_abort_handler_address = %08x\n", prefetch_abort_handler_address);
    666   1.1    ichiro 	printf("undefined_handler_address = %08x\n", undefined_handler_address);
    667  1.23   thorpej #endif
    668   1.1    ichiro 
    669   1.1    ichiro 	/* Initialise the undefined instruction handlers */
    670  1.23   thorpej #ifdef VERBOSE_INIT_ARM
    671   1.1    ichiro 	printf("undefined ");
    672  1.23   thorpej #endif
    673   1.1    ichiro 	undefined_init();
    674   1.1    ichiro 
    675   1.4   thorpej 	/* Load memory into UVM. */
    676  1.23   thorpej #ifdef VERBOSE_INIT_ARM
    677   1.4   thorpej 	printf("page ");
    678  1.23   thorpej #endif
    679   1.4   thorpej 	uvm_setpagesize();	/* initialize PAGE_SIZE-dependent variables */
    680   1.4   thorpej 	uvm_page_physload(atop(physical_freestart), atop(physical_freeend),
    681   1.4   thorpej 	    atop(physical_freestart), atop(physical_freeend),
    682   1.4   thorpej 	    VM_FREELIST_DEFAULT);
    683   1.4   thorpej 
    684   1.1    ichiro 	/* Boot strap pmap telling it where the kernel page table is */
    685  1.23   thorpej #ifdef VERBOSE_INIT_ARM
    686   1.1    ichiro 	printf("pmap ");
    687  1.23   thorpej #endif
    688  1.34      matt 	pmap_bootstrap(KERNEL_VM_BASE, KERNEL_VM_BASE + KERNEL_VM_SIZE);
    689   1.1    ichiro 
    690   1.1    ichiro 	/* Setup the IRQ system */
    691  1.23   thorpej #ifdef VERBOSE_INIT_ARM
    692   1.1    ichiro 	printf("irq ");
    693  1.23   thorpej #endif
    694   1.1    ichiro 	ixp12x0_intr_init();
    695  1.23   thorpej 
    696  1.23   thorpej #ifdef VERBOSE_INIT_ARM
    697   1.1    ichiro 	printf("done.\n");
    698  1.23   thorpej #endif
    699   1.1    ichiro 
    700   1.1    ichiro #ifdef VERBOSE_INIT_ARM
    701   1.1    ichiro 	printf("freestart = 0x%08lx, free_pages = %d (0x%x)\n",
    702   1.1    ichiro 		physical_freestart, free_pages, free_pages);
    703   1.1    ichiro 	printf("freemempos=%08lx\n", freemempos);
    704   1.1    ichiro 	printf("switching to new L1 page table  @%#lx... \n", kernel_l1pt.pv_pa);
    705   1.1    ichiro #endif
    706   1.1    ichiro 
    707   1.1    ichiro 	consinit();
    708  1.23   thorpej #ifdef VERBOSE_INIT_ARM
    709   1.1    ichiro 	printf("consinit \n");
    710  1.23   thorpej #endif
    711   1.1    ichiro 
    712   1.1    ichiro 	ixdp_ixp12x0_cc_setup();
    713   1.1    ichiro 
    714  1.23   thorpej #ifdef VERBOSE_INIT_ARM
    715   1.1    ichiro 	printf("bootstrap done.\n");
    716  1.23   thorpej #endif
    717   1.1    ichiro 
    718  1.36        ad #if NKSYMS || defined(DDB) || defined(MODULAR)
    719  1.37    martin 	ksyms_addsyms_elf(symbolsize, ((int *)&end), ((char *)&end) + symbolsize);
    720  1.15     ragge #endif
    721  1.15     ragge 
    722   1.1    ichiro #ifdef DDB
    723  1.29  rearnsha 	db_machine_init();
    724   1.1    ichiro 	if (boothowto & RB_KDB)
    725   1.1    ichiro 		Debugger();
    726   1.1    ichiro #endif
    727   1.1    ichiro 
    728   1.1    ichiro 	/* We return the new stack pointer address */
    729   1.1    ichiro 	return(kernelstack.pv_va + USPACE_SVC_STACK_TOP);
    730   1.1    ichiro }
    731   1.1    ichiro 
    732   1.1    ichiro void
    733   1.1    ichiro consinit(void)
    734   1.1    ichiro {
    735   1.1    ichiro 	static int consinit_called = 0;
    736   1.1    ichiro 
    737   1.1    ichiro 	if (consinit_called != 0)
    738   1.1    ichiro 		return;
    739   1.1    ichiro 
    740   1.1    ichiro 	consinit_called = 1;
    741  1.26       igy 
    742  1.26       igy 	pmap_devmap_register(ixm1200_devmap);
    743   1.1    ichiro 
    744  1.27       igy 	if (ixpcomcnattach(&ixp12x0_bs_tag,
    745  1.12       igy 			   IXPCOM_UART_HWBASE, IXPCOM_UART_VBASE,
    746   1.1    ichiro 			   CONSPEED, CONMODE))
    747  1.12       igy 		panic("can't init serial console @%lx", IXPCOM_UART_HWBASE);
    748   1.1    ichiro }
    749   1.1    ichiro 
    750   1.1    ichiro /*
    751   1.1    ichiro  * For optimal cache cleaning we need two 16K banks of
    752   1.1    ichiro  * virtual address space that NOTHING else will access
    753   1.1    ichiro  * and then we alternate the cache cleaning between the
    754   1.1    ichiro  * two banks.
    755   1.1    ichiro  * The cache cleaning code requires requires 2 banks aligned
    756   1.1    ichiro  * on total size boundry so the banks can be alternated by
    757   1.1    ichiro  * eorring the size bit (assumes the bank size is a power of 2)
    758   1.1    ichiro  */
    759   1.1    ichiro void
    760   1.1    ichiro ixdp_ixp12x0_cc_setup(void)
    761   1.1    ichiro {
    762   1.1    ichiro 	int loop;
    763   1.1    ichiro 	paddr_t kaddr;
    764   1.1    ichiro 
    765   1.1    ichiro 	(void) pmap_extract(pmap_kernel(), KERNEL_TEXT_BASE, &kaddr);
    766  1.14   thorpej 	for (loop = 0; loop < CPU_IXP12X0_CACHE_CLEAN_SIZE; loop += PAGE_SIZE) {
    767  1.55      matt 		pt_entry_t * const ptep = vtopte(ixp12x0_cc_base + loop);
    768  1.55      matt 		const pt_entry_t npte = L2_S_PROTO | kaddr |
    769   1.1    ichiro                     L2_S_PROT(PTE_KERNEL, VM_PROT_READ) | pte_l2_s_cache_mode;
    770  1.55      matt 		l2pte_set(ptep, npte, 0);
    771  1.55      matt 		PTE_SYNC(ptep);
    772   1.1    ichiro         }
    773   1.1    ichiro 	ixp12x0_cache_clean_addr = ixp12x0_cc_base;
    774   1.1    ichiro 	ixp12x0_cache_clean_size = CPU_IXP12X0_CACHE_CLEAN_SIZE / 2;
    775   1.1    ichiro }
    776