ixm1200_machdep.c revision 1.8 1 1.8 provos /* $NetBSD: ixm1200_machdep.c,v 1.8 2002/09/27 15:36:01 provos Exp $ */
2 1.1 ichiro #undef DEBUG_BEFOREMMU
3 1.1 ichiro /*
4 1.1 ichiro * Copyright (c) 2002
5 1.1 ichiro * Ichiro FUKUHARA <ichiro (at) ichiro.org>.
6 1.1 ichiro * All rights reserved.
7 1.1 ichiro *
8 1.1 ichiro * Redistribution and use in source and binary forms, with or without
9 1.1 ichiro * modification, are permitted provided that the following conditions
10 1.1 ichiro * are met:
11 1.1 ichiro * 1. Redistributions of source code must retain the above copyright
12 1.1 ichiro * notice, this list of conditions and the following disclaimer.
13 1.1 ichiro * 2. Redistributions in binary form must reproduce the above copyright
14 1.1 ichiro * notice, this list of conditions and the following disclaimer in the
15 1.1 ichiro * documentation and/or other materials provided with the distribution.
16 1.1 ichiro * 3. All advertising materials mentioning features or use of this software
17 1.1 ichiro * must display the following acknowledgement:
18 1.1 ichiro * This product includes software developed by Ichiro FUKUHARA.
19 1.1 ichiro * 4. The name of the company nor the name of the author may be used to
20 1.1 ichiro * endorse or promote products derived from this software without specific
21 1.1 ichiro * prior written permission.
22 1.1 ichiro *
23 1.1 ichiro * THIS SOFTWARE IS PROVIDED BY ICHIRO FUKUHARA ``AS IS'' AND ANY EXPRESS OR
24 1.1 ichiro * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
25 1.1 ichiro * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
26 1.1 ichiro * IN NO EVENT SHALL ICHIRO FUKUHARA OR THE VOICES IN HIS HEAD BE LIABLE FOR
27 1.1 ichiro * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
28 1.1 ichiro * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
29 1.1 ichiro * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
30 1.1 ichiro * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
31 1.1 ichiro * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
32 1.1 ichiro * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
33 1.1 ichiro * SUCH DAMAGE.
34 1.1 ichiro */
35 1.1 ichiro /*
36 1.1 ichiro * Copyright (c) 1997,1998 Mark Brinicombe.
37 1.1 ichiro * Copyright (c) 1997,1998 Causality Limited.
38 1.1 ichiro * All rights reserved.
39 1.1 ichiro *
40 1.1 ichiro * Redistribution and use in source and binary forms, with or without
41 1.1 ichiro * modification, are permitted provided that the following conditions
42 1.1 ichiro * are met:
43 1.1 ichiro * 1. Redistributions of source code must retain the above copyright
44 1.1 ichiro * notice, this list of conditions and the following disclaimer.
45 1.1 ichiro * 2. Redistributions in binary form must reproduce the above copyright
46 1.1 ichiro * notice, this list of conditions and the following disclaimer in the
47 1.1 ichiro * documentation and/or other materials provided with the distribution.
48 1.1 ichiro * 3. All advertising materials mentioning features or use of this software
49 1.1 ichiro * must display the following acknowledgement:
50 1.1 ichiro * This product includes software developed by Mark Brinicombe
51 1.1 ichiro * for the NetBSD Project.
52 1.1 ichiro * 4. The name of the company nor the name of the author may be used to
53 1.1 ichiro * endorse or promote products derived from this software without specific
54 1.1 ichiro * prior written permission.
55 1.1 ichiro *
56 1.1 ichiro * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
57 1.1 ichiro * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
58 1.1 ichiro * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
59 1.1 ichiro * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
60 1.1 ichiro * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
61 1.1 ichiro * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
62 1.1 ichiro * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
63 1.1 ichiro * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
64 1.1 ichiro * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
65 1.1 ichiro * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
66 1.1 ichiro * SUCH DAMAGE.
67 1.1 ichiro */
68 1.1 ichiro
69 1.1 ichiro #include "opt_ddb.h"
70 1.1 ichiro #include "opt_pmap_debug.h"
71 1.1 ichiro
72 1.1 ichiro #include <sys/param.h>
73 1.1 ichiro #include <sys/device.h>
74 1.1 ichiro #include <sys/systm.h>
75 1.1 ichiro #include <sys/kernel.h>
76 1.1 ichiro #include <sys/exec.h>
77 1.1 ichiro #include <sys/proc.h>
78 1.1 ichiro #include <sys/msgbuf.h>
79 1.1 ichiro #include <sys/reboot.h>
80 1.1 ichiro #include <sys/termios.h>
81 1.1 ichiro
82 1.1 ichiro #include <dev/cons.h>
83 1.1 ichiro
84 1.1 ichiro #ifdef DDB
85 1.1 ichiro #include <machine/db_machdep.h>
86 1.1 ichiro #include <ddb/db_sym.h>
87 1.1 ichiro #include <ddb/db_extern.h>
88 1.1 ichiro #ifndef DB_ELFSIZE
89 1.1 ichiro #error Must define DB_ELFSIZE!
90 1.1 ichiro #endif
91 1.1 ichiro #define ELFSIZE DB_ELFSIZE
92 1.1 ichiro #include <sys/exec_elf.h>
93 1.1 ichiro #endif
94 1.1 ichiro
95 1.1 ichiro #include <machine/bootconfig.h>
96 1.1 ichiro #include <machine/bus.h>
97 1.1 ichiro #include <machine/cpu.h>
98 1.1 ichiro #include <machine/frame.h>
99 1.1 ichiro #include <arm/undefined.h>
100 1.1 ichiro
101 1.1 ichiro #include <arm/arm32/machdep.h>
102 1.1 ichiro
103 1.1 ichiro #include <arm/ixp12x0/ixp12x0reg.h>
104 1.1 ichiro #include <arm/ixp12x0/ixp12x0var.h>
105 1.1 ichiro #include <arm/ixp12x0/ixp12x0_comreg.h>
106 1.1 ichiro #include <arm/ixp12x0/ixp12x0_comvar.h>
107 1.1 ichiro #include <arm/ixp12x0/ixp12x0_pcireg.h>
108 1.1 ichiro
109 1.1 ichiro #include <evbarm/ixm1200/ixm1200reg.h>
110 1.1 ichiro #include <evbarm/ixm1200/ixm1200var.h>
111 1.1 ichiro
112 1.1 ichiro #include "opt_ipkdb.h"
113 1.1 ichiro
114 1.1 ichiro /* XXX for consinit related hacks */
115 1.1 ichiro #include <sys/conf.h>
116 1.1 ichiro
117 1.1 ichiro void ixp12x0_reset(void) __attribute__((noreturn));
118 1.1 ichiro
119 1.1 ichiro /*
120 1.1 ichiro * Address to call from cpu_reset() to reset the machine.
121 1.1 ichiro * This is machine architecture dependant as it varies depending
122 1.1 ichiro * on where the ROM appears when you turn the MMU off.
123 1.1 ichiro */
124 1.1 ichiro
125 1.1 ichiro u_int cpu_reset_address = (u_int) ixp12x0_reset;
126 1.1 ichiro
127 1.1 ichiro /*
128 1.1 ichiro * Define the default console speed for the board.
129 1.1 ichiro */
130 1.1 ichiro #ifndef CONMODE
131 1.1 ichiro #define CONMODE ((TTYDEF_CFLAG & ~(CSIZE | CSTOPB)) | CS8) /* 8N1 */
132 1.1 ichiro #endif
133 1.1 ichiro #ifndef CONSPEED
134 1.1 ichiro #define CONSPEED B38400
135 1.1 ichiro #endif
136 1.1 ichiro #ifndef CONADDR
137 1.1 ichiro #define CONADDR IXPCOM_UART_BASE
138 1.1 ichiro #endif
139 1.1 ichiro
140 1.1 ichiro cons_decl(com);
141 1.1 ichiro cons_decl(ixpcom);
142 1.1 ichiro
143 1.1 ichiro struct consdev constab[] = {
144 1.1 ichiro #if (NIXPCOM > 0)
145 1.1 ichiro cons_init(ixpcom),
146 1.1 ichiro #endif
147 1.1 ichiro { 0 },
148 1.1 ichiro };
149 1.1 ichiro
150 1.1 ichiro /* Define various stack sizes in pages */
151 1.1 ichiro #define IRQ_STACK_SIZE 1
152 1.1 ichiro #define ABT_STACK_SIZE 1
153 1.1 ichiro #ifdef IPKDB
154 1.1 ichiro #define UND_STACK_SIZE 2
155 1.1 ichiro #else
156 1.1 ichiro #define UND_STACK_SIZE 1
157 1.1 ichiro #endif
158 1.1 ichiro
159 1.1 ichiro BootConfig bootconfig; /* Boot config storage */
160 1.1 ichiro char *boot_args = NULL;
161 1.1 ichiro char *boot_file = NULL;
162 1.1 ichiro
163 1.1 ichiro vm_offset_t physical_start;
164 1.1 ichiro vm_offset_t physical_freestart;
165 1.1 ichiro vm_offset_t physical_freeend;
166 1.1 ichiro vm_offset_t physical_end;
167 1.1 ichiro u_int free_pages;
168 1.1 ichiro vm_offset_t pagetables_start;
169 1.1 ichiro int physmem = 0;
170 1.1 ichiro
171 1.1 ichiro /*int debug_flags;*/
172 1.1 ichiro #ifndef PMAP_STATIC_L1S
173 1.1 ichiro int max_processes = 64; /* Default number */
174 1.1 ichiro #endif /* !PMAP_STATIC_L1S */
175 1.1 ichiro
176 1.1 ichiro /* Physical and virtual addresses for some global pages */
177 1.1 ichiro pv_addr_t systempage;
178 1.1 ichiro pv_addr_t irqstack;
179 1.1 ichiro pv_addr_t undstack;
180 1.1 ichiro pv_addr_t abtstack;
181 1.1 ichiro pv_addr_t kernelstack;
182 1.1 ichiro
183 1.1 ichiro vm_offset_t msgbufphys;
184 1.1 ichiro
185 1.1 ichiro extern u_int data_abort_handler_address;
186 1.1 ichiro extern u_int prefetch_abort_handler_address;
187 1.1 ichiro extern u_int undefined_handler_address;
188 1.1 ichiro extern int end;
189 1.1 ichiro
190 1.1 ichiro #ifdef PMAP_DEBUG
191 1.1 ichiro extern int pmap_debug_level;
192 1.1 ichiro #endif /* PMAP_DEBUG */
193 1.1 ichiro
194 1.1 ichiro #define KERNEL_PT_SYS 0 /* Page table for mapping proc0 zero page */
195 1.1 ichiro #define KERNEL_PT_KERNEL 1 /* Page table for mapping kernel */
196 1.1 ichiro #define KERNEL_PT_KERNEL_NUM 2
197 1.1 ichiro #define KERNEL_PT_IO (KERNEL_PT_KERNEL + KERNEL_PT_KERNEL_NUM)
198 1.1 ichiro /* Page table for mapping IO */
199 1.1 ichiro #define KERNEL_PT_VMDATA (KERNEL_PT_IO + 1)
200 1.1 ichiro /* Page tables for mapping kernel VM */
201 1.1 ichiro #define KERNEL_PT_VMDATA_NUM 4 /* start with 16MB of KVM */
202 1.1 ichiro #define NUM_KERNEL_PTS (KERNEL_PT_VMDATA + KERNEL_PT_VMDATA_NUM)
203 1.1 ichiro
204 1.1 ichiro pv_addr_t kernel_pt_table[NUM_KERNEL_PTS];
205 1.1 ichiro
206 1.1 ichiro struct user *proc0paddr;
207 1.1 ichiro
208 1.1 ichiro #ifdef CPU_IXP12X0
209 1.1 ichiro #define CPU_IXP12X0_CACHE_CLEAN_SIZE (0x4000 * 2)
210 1.1 ichiro extern unsigned int ixp12x0_cache_clean_addr;
211 1.1 ichiro extern unsigned int ixp12x0_cache_clean_size;
212 1.1 ichiro static vaddr_t ixp12x0_cc_base;
213 1.1 ichiro #endif /* CPU_IXP12X0 */
214 1.1 ichiro
215 1.1 ichiro /* Prototypes */
216 1.1 ichiro
217 1.1 ichiro void consinit __P((void));
218 1.1 ichiro u_int cpu_get_control __P((void));
219 1.1 ichiro
220 1.1 ichiro void ixdp_ixp12x0_cc_setup(void);
221 1.1 ichiro
222 1.1 ichiro #ifdef DEBUG_BEFOREMMU
223 1.1 ichiro static void fakecninit();
224 1.1 ichiro #endif
225 1.1 ichiro
226 1.1 ichiro extern int db_trapper();
227 1.1 ichiro
228 1.1 ichiro /*
229 1.1 ichiro * void cpu_reboot(int howto, char *bootstr)
230 1.1 ichiro *
231 1.1 ichiro * Reboots the system
232 1.1 ichiro *
233 1.1 ichiro * Deal with any syncing, unmounting, dumping and shutdown hooks,
234 1.1 ichiro * then reset the CPU.
235 1.1 ichiro */
236 1.1 ichiro
237 1.1 ichiro void
238 1.1 ichiro cpu_reboot(howto, bootstr)
239 1.1 ichiro int howto;
240 1.1 ichiro char *bootstr;
241 1.1 ichiro {
242 1.1 ichiro /*
243 1.1 ichiro * If we are still cold then hit the air brakes
244 1.1 ichiro * and crash to earth fast
245 1.1 ichiro */
246 1.1 ichiro if (cold) {
247 1.1 ichiro doshutdownhooks();
248 1.1 ichiro printf("Halted while still in the ICE age.\n");
249 1.1 ichiro printf("The operating system has halted.\n");
250 1.1 ichiro printf("Please press any key to reboot.\n\n");
251 1.1 ichiro cngetc();
252 1.1 ichiro printf("rebooting...\n");
253 1.1 ichiro ixp12x0_reset();
254 1.1 ichiro }
255 1.1 ichiro
256 1.1 ichiro /* Disable console buffering */
257 1.1 ichiro cnpollc(1);
258 1.1 ichiro
259 1.1 ichiro /*
260 1.1 ichiro * If RB_NOSYNC was not specified sync the discs.
261 1.1 ichiro * Note: Unless cold is set to 1 here, syslogd will die during the unmount.
262 1.1 ichiro * It looks like syslogd is getting woken up only to find that it cannot
263 1.1 ichiro * page part of the binary in as the filesystem has been unmounted.
264 1.1 ichiro */
265 1.1 ichiro if (!(howto & RB_NOSYNC))
266 1.1 ichiro bootsync();
267 1.1 ichiro
268 1.1 ichiro /* Say NO to interrupts */
269 1.1 ichiro splhigh();
270 1.1 ichiro
271 1.1 ichiro /* Do a dump if requested. */
272 1.1 ichiro if ((howto & (RB_DUMP | RB_HALT)) == RB_DUMP)
273 1.1 ichiro dumpsys();
274 1.1 ichiro
275 1.1 ichiro /* Run any shutdown hooks */
276 1.1 ichiro doshutdownhooks();
277 1.1 ichiro
278 1.1 ichiro /* Make sure IRQ's are disabled */
279 1.1 ichiro IRQdisable;
280 1.1 ichiro
281 1.1 ichiro if (howto & RB_HALT) {
282 1.1 ichiro printf("The operating system has halted.\n");
283 1.1 ichiro printf("Please press any key to reboot.\n\n");
284 1.1 ichiro cngetc();
285 1.1 ichiro }
286 1.1 ichiro
287 1.1 ichiro printf("rebooting...\n");
288 1.1 ichiro
289 1.1 ichiro /* all interrupts are disabled */
290 1.1 ichiro disable_interrupts(I32_bit);
291 1.1 ichiro
292 1.1 ichiro ixp12x0_reset();
293 1.1 ichiro
294 1.1 ichiro /* ...and if that didn't work, just croak. */
295 1.1 ichiro printf("RESET FAILED!\n");
296 1.1 ichiro for (;;);
297 1.1 ichiro }
298 1.1 ichiro
299 1.1 ichiro /*
300 1.1 ichiro * pmap table
301 1.1 ichiro */
302 1.1 ichiro /*
303 1.1 ichiro * IXM1200 specific I/O registers mapping table
304 1.1 ichiro */
305 1.1 ichiro static struct pmap_ent map_tbl_ixm1200[] = {
306 1.1 ichiro { "IXM1200 SlowPort I/O Registers",
307 1.1 ichiro IXM1200_LED_VADDR, IXM1200_LED_ADDR,
308 1.1 ichiro IXM1200_LED_ADDR_SIZE,
309 1.1 ichiro VM_PROT_READ|VM_PROT_WRITE,
310 1.1 ichiro PTE_NOCACHE, },
311 1.1 ichiro
312 1.1 ichiro { NULL,
313 1.1 ichiro 0,
314 1.1 ichiro 0,
315 1.1 ichiro 0,
316 1.1 ichiro 0,
317 1.1 ichiro 0,
318 1.1 ichiro }
319 1.1 ichiro };
320 1.1 ichiro
321 1.1 ichiro /*
322 1.1 ichiro * Initial entry point on startup. This gets called before main() is
323 1.1 ichiro * entered.
324 1.1 ichiro * It should be responsible for setting up everything that must be
325 1.1 ichiro * in place when main is called.
326 1.1 ichiro * This includes
327 1.1 ichiro * Taking a copy of the boot configuration structure.
328 1.1 ichiro * Initialising the physical console so characters can be printed.
329 1.1 ichiro * Setting up page tables for the kernel
330 1.1 ichiro * Relocating the kernel to the bottom of physical memory
331 1.1 ichiro */
332 1.1 ichiro u_int
333 1.1 ichiro initarm(void *arg)
334 1.1 ichiro {
335 1.1 ichiro int loop;
336 1.1 ichiro int loop1;
337 1.1 ichiro u_int kerneldatasize, symbolsize;
338 1.1 ichiro vaddr_t l1pagetable;
339 1.1 ichiro vaddr_t freemempos;
340 1.1 ichiro pv_addr_t kernel_l1pt;
341 1.1 ichiro pv_addr_t kernel_ptpt;
342 1.1 ichiro #ifdef DDB
343 1.1 ichiro Elf_Shdr *sh;
344 1.1 ichiro #endif
345 1.1 ichiro
346 1.1 ichiro #ifdef PMAP_DEBUG
347 1.2 ichiro pmap_debug(-1);
348 1.1 ichiro #endif
349 1.1 ichiro
350 1.1 ichiro #ifdef DEBUG_BEFOREMMU
351 1.1 ichiro /*
352 1.1 ichiro * At this point, we cannot call real consinit().
353 1.1 ichiro * Just call a faked up version of consinit(), which does the thing
354 1.1 ichiro * with MMU disabled.
355 1.1 ichiro */
356 1.1 ichiro fakecninit();
357 1.1 ichiro #endif
358 1.1 ichiro /*
359 1.1 ichiro * Since we map v0xf0000000 == p0x90000000, it's possible for
360 1.1 ichiro * us to initialize the console now.
361 1.1 ichiro */
362 1.1 ichiro consinit();
363 1.1 ichiro
364 1.1 ichiro /* Talk to the user */
365 1.1 ichiro printf("\nNetBSD/evbarm (IXM1200) booting ...\n");
366 1.1 ichiro
367 1.1 ichiro /*
368 1.1 ichiro * Heads up ... Setup the CPU / MMU / TLB functions
369 1.1 ichiro */
370 1.1 ichiro if (set_cpufuncs())
371 1.1 ichiro panic("cpu not recognized!");
372 1.1 ichiro
373 1.1 ichiro /* XXX overwrite bootconfig to hardcoded values */
374 1.1 ichiro bootconfig.dram[0].address = 0xc0000000;
375 1.1 ichiro bootconfig.dram[0].pages = 0x10000000 / NBPG; /* SDRAM 256MB */
376 1.1 ichiro bootconfig.dramblocks = 1;
377 1.1 ichiro
378 1.1 ichiro kerneldatasize = (u_int32_t)&end - (u_int32_t)KERNEL_TEXT_BASE;
379 1.1 ichiro
380 1.1 ichiro symbolsize = 0;
381 1.1 ichiro #ifdef DDB
382 1.1 ichiro if (! memcmp(&end, "\177ELF", 4)) {
383 1.1 ichiro sh = (Elf_Shdr *)((char *)&end + ((Elf_Ehdr *)&end)->e_shoff);
384 1.1 ichiro loop = ((Elf_Ehdr *)&end)->e_shnum;
385 1.1 ichiro for(; loop; loop--, sh++)
386 1.1 ichiro if (sh->sh_offset > 0 &&
387 1.1 ichiro (sh->sh_offset + sh->sh_size) > symbolsize)
388 1.1 ichiro symbolsize = sh->sh_offset + sh->sh_size;
389 1.1 ichiro }
390 1.1 ichiro #endif
391 1.1 ichiro printf("kernsize=0x%x\n", kerneldatasize);
392 1.1 ichiro kerneldatasize += symbolsize;
393 1.1 ichiro kerneldatasize = ((kerneldatasize - 1) & ~(NBPG * 4 - 1)) + NBPG * 8;
394 1.1 ichiro
395 1.1 ichiro /*
396 1.1 ichiro * Set up the variables that define the availablilty of physcial
397 1.1 ichiro * memory
398 1.1 ichiro */
399 1.1 ichiro physical_start = bootconfig.dram[0].address;
400 1.1 ichiro physical_end = physical_start + (bootconfig.dram[0].pages * NBPG);
401 1.1 ichiro
402 1.1 ichiro physical_freestart = physical_start
403 1.1 ichiro + (KERNEL_TEXT_BASE - KERNEL_BASE) + kerneldatasize;
404 1.1 ichiro physical_freeend = physical_end;
405 1.1 ichiro
406 1.1 ichiro physmem = (physical_end - physical_start) / NBPG;
407 1.1 ichiro
408 1.1 ichiro freemempos = 0xc0000000;
409 1.1 ichiro
410 1.1 ichiro #ifdef VERBOSE_INIT_ARM
411 1.1 ichiro printf("Allocating page tables\n");
412 1.1 ichiro #endif
413 1.1 ichiro free_pages = (physical_freeend - physical_freestart) / NBPG;
414 1.1 ichiro
415 1.1 ichiro #ifdef VERBOSE_INIT_ARM
416 1.1 ichiro printf("CP15 Register1 = 0x%08x\n", cpu_get_control());
417 1.1 ichiro printf("freestart = 0x%08lx, free_pages = %d (0x%08x)\n",
418 1.1 ichiro physical_freestart, free_pages, free_pages);
419 1.1 ichiro printf("physical_start = 0x%08lx, physical_end = 0x%08lx\n",
420 1.1 ichiro physical_start, physical_end);
421 1.1 ichiro #endif
422 1.1 ichiro
423 1.1 ichiro /* Define a macro to simplify memory allocation */
424 1.1 ichiro #define valloc_pages(var, np) \
425 1.1 ichiro alloc_pages((var).pv_pa, (np)); \
426 1.1 ichiro (var).pv_va = KERNEL_BASE + (var).pv_pa - physical_start;
427 1.1 ichiro #define alloc_pages(var, np) \
428 1.1 ichiro (var) = freemempos; \
429 1.1 ichiro memset((char *)(var), 0, ((np) * NBPG)); \
430 1.1 ichiro freemempos += (np) * NBPG;
431 1.1 ichiro
432 1.1 ichiro loop1 = 0;
433 1.1 ichiro kernel_l1pt.pv_pa = 0;
434 1.1 ichiro for (loop = 0; loop <= NUM_KERNEL_PTS; ++loop) {
435 1.1 ichiro /* Are we 16KB aligned for an L1 ? */
436 1.1 ichiro if (((physical_freeend - L1_TABLE_SIZE) & (L1_TABLE_SIZE - 1)) == 0
437 1.1 ichiro && kernel_l1pt.pv_pa == 0) {
438 1.1 ichiro valloc_pages(kernel_l1pt, L1_TABLE_SIZE / NBPG);
439 1.1 ichiro } else {
440 1.1 ichiro alloc_pages(kernel_pt_table[loop1].pv_pa,
441 1.1 ichiro L2_TABLE_SIZE / NBPG);
442 1.1 ichiro kernel_pt_table[loop1].pv_va =
443 1.1 ichiro kernel_pt_table[loop1].pv_pa;
444 1.1 ichiro ++loop1;
445 1.1 ichiro }
446 1.1 ichiro }
447 1.1 ichiro
448 1.1 ichiro #ifdef DIAGNOSTIC
449 1.1 ichiro /* This should never be able to happen but better confirm that. */
450 1.1 ichiro if (!kernel_l1pt.pv_pa || (kernel_l1pt.pv_pa & (L1_TABLE_SIZE-1)) != 0)
451 1.8 provos panic("initarm: Failed to align the kernel page directory");
452 1.1 ichiro #endif
453 1.1 ichiro
454 1.1 ichiro /*
455 1.1 ichiro * Allocate a page for the system page mapped to V0x00000000
456 1.1 ichiro * This page will just contain the system vectors and can be
457 1.1 ichiro * shared by all processes.
458 1.1 ichiro */
459 1.1 ichiro alloc_pages(systempage.pv_pa, 1);
460 1.1 ichiro
461 1.1 ichiro /* Allocate a page for the page table to map kernel page tables. */
462 1.1 ichiro valloc_pages(kernel_ptpt, L2_TABLE_SIZE / NBPG);
463 1.1 ichiro
464 1.1 ichiro /* Allocate stacks for all modes */
465 1.1 ichiro valloc_pages(irqstack, IRQ_STACK_SIZE);
466 1.1 ichiro valloc_pages(abtstack, ABT_STACK_SIZE);
467 1.1 ichiro valloc_pages(undstack, UND_STACK_SIZE);
468 1.1 ichiro valloc_pages(kernelstack, UPAGES);
469 1.1 ichiro
470 1.1 ichiro #ifdef VERBOSE_INIT_ARM
471 1.1 ichiro printf("IRQ stack: p0x%08lx v0x%08lx\n", irqstack.pv_pa, irqstack.pv_va);
472 1.1 ichiro printf("ABT stack: p0x%08lx v0x%08lx\n", abtstack.pv_pa, abtstack.pv_va);
473 1.1 ichiro printf("UND stack: p0x%08lx v0x%08lx\n", undstack.pv_pa, undstack.pv_va);
474 1.1 ichiro printf("SVC stack: p0x%08lx v0x%08lx\n", kernelstack.pv_pa, kernelstack.pv_va);
475 1.1 ichiro #endif
476 1.1 ichiro
477 1.1 ichiro alloc_pages(msgbufphys, round_page(MSGBUFSIZE) / NBPG);
478 1.1 ichiro
479 1.1 ichiro #ifdef CPU_IXP12X0
480 1.1 ichiro /*
481 1.1 ichiro * XXX totally stuffed hack to work round problems introduced
482 1.1 ichiro * in recent versions of the pmap code. Due to the calls used there
483 1.1 ichiro * we cannot allocate virtual memory during bootstrap.
484 1.1 ichiro */
485 1.1 ichiro for(;;) {
486 1.1 ichiro alloc_pages(ixp12x0_cc_base, 1);
487 1.1 ichiro if (! (ixp12x0_cc_base & (CPU_IXP12X0_CACHE_CLEAN_SIZE - 1)))
488 1.1 ichiro break;
489 1.1 ichiro }
490 1.1 ichiro {
491 1.1 ichiro vaddr_t dummy;
492 1.1 ichiro alloc_pages(dummy, CPU_IXP12X0_CACHE_CLEAN_SIZE / NBPG - 1);
493 1.1 ichiro }
494 1.1 ichiro ixp12x0_cache_clean_addr = ixp12x0_cc_base;
495 1.1 ichiro ixp12x0_cache_clean_size = CPU_IXP12X0_CACHE_CLEAN_SIZE / 2;
496 1.1 ichiro #endif /* CPU_IXP12X0 */
497 1.1 ichiro
498 1.1 ichiro #ifdef VERBOSE_INIT_ARM
499 1.1 ichiro printf("Creating L1 page table at 0x%08lx\n", kernel_l1pt.pv_pa);
500 1.1 ichiro #endif
501 1.1 ichiro
502 1.1 ichiro /*
503 1.1 ichiro * Now we start construction of the L1 page table
504 1.1 ichiro * We start by mapping the L2 page tables into the L1.
505 1.1 ichiro * This means that we can replace L1 mappings later on if necessary
506 1.1 ichiro */
507 1.1 ichiro l1pagetable = kernel_l1pt.pv_pa;
508 1.1 ichiro
509 1.1 ichiro /* Map the L2 pages tables in the L1 page table */
510 1.1 ichiro pmap_link_l2pt(l1pagetable, 0x00000000,
511 1.1 ichiro &kernel_pt_table[KERNEL_PT_SYS]);
512 1.1 ichiro
513 1.1 ichiro for (loop = 0; loop < KERNEL_PT_KERNEL_NUM; loop++)
514 1.1 ichiro pmap_link_l2pt(l1pagetable, KERNEL_BASE + loop * 0x00400000,
515 1.1 ichiro &kernel_pt_table[KERNEL_PT_KERNEL + loop]);
516 1.1 ichiro
517 1.1 ichiro for (loop = 0; loop < KERNEL_PT_VMDATA_NUM; loop++)
518 1.1 ichiro pmap_link_l2pt(l1pagetable, KERNEL_VM_BASE + loop * 0x00400000,
519 1.1 ichiro &kernel_pt_table[KERNEL_PT_VMDATA + loop]);
520 1.1 ichiro pmap_link_l2pt(l1pagetable, PTE_BASE, &kernel_ptpt);
521 1.1 ichiro
522 1.1 ichiro /* update the top of the kernel VM */
523 1.1 ichiro pmap_curmaxkvaddr =
524 1.1 ichiro KERNEL_VM_BASE + (KERNEL_PT_VMDATA_NUM * 0x00400000);
525 1.1 ichiro
526 1.1 ichiro pmap_link_l2pt(l1pagetable, IXP12X0_IO_VBASE,
527 1.1 ichiro &kernel_pt_table[KERNEL_PT_IO]);
528 1.1 ichiro
529 1.1 ichiro #ifdef VERBOSE_INIT_ARM
530 1.1 ichiro printf("Mapping kernel\n");
531 1.1 ichiro #endif
532 1.1 ichiro
533 1.1 ichiro #if XXX
534 1.1 ichiro /* Now we fill in the L2 pagetable for the kernel code/data */
535 1.1 ichiro {
536 1.1 ichiro extern char etext[], _end[];
537 1.1 ichiro size_t textsize = (uintptr_t) etext - KERNEL_TEXT_BASE;
538 1.1 ichiro size_t totalsize = (uintptr_t) _end - KERNEL_TEXT_BASE;
539 1.1 ichiro u_int logical;
540 1.1 ichiro
541 1.1 ichiro textsize = (textsize + PGOFSET) & ~PGOFSET;
542 1.1 ichiro totalsize = (totalsize + PGOFSET) & ~PGOFSET;
543 1.1 ichiro
544 1.1 ichiro logical = 0x00200000; /* offset of kernel in RAM */
545 1.1 ichiro
546 1.1 ichiro logical += pmap_map_chunk(l1pagetable, KERNEL_BASE + logical,
547 1.1 ichiro physical_start + logical, textsize,
548 1.1 ichiro VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE);
549 1.1 ichiro logical += pmap_map_chunk(l1pagetable, KERNEL_BASE + logical,
550 1.1 ichiro physical_start + logical, totalsize - textsize,
551 1.1 ichiro VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE);
552 1.1 ichiro }
553 1.1 ichiro #else
554 1.1 ichiro {
555 1.1 ichiro pmap_map_chunk(l1pagetable, KERNEL_TEXT_BASE,
556 1.1 ichiro KERNEL_TEXT_BASE, kerneldatasize,
557 1.1 ichiro VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE);
558 1.1 ichiro }
559 1.1 ichiro #endif
560 1.1 ichiro
561 1.1 ichiro #ifdef VERBOSE_INIT_ARM
562 1.1 ichiro printf("Constructing L2 page tables\n");
563 1.1 ichiro #endif
564 1.1 ichiro
565 1.1 ichiro /* Map the stack pages */
566 1.1 ichiro pmap_map_chunk(l1pagetable, irqstack.pv_va, irqstack.pv_pa,
567 1.1 ichiro IRQ_STACK_SIZE * NBPG, VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE);
568 1.1 ichiro pmap_map_chunk(l1pagetable, abtstack.pv_va, abtstack.pv_pa,
569 1.1 ichiro ABT_STACK_SIZE * NBPG, VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE);
570 1.1 ichiro pmap_map_chunk(l1pagetable, undstack.pv_va, undstack.pv_pa,
571 1.1 ichiro UND_STACK_SIZE * NBPG, VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE);
572 1.1 ichiro pmap_map_chunk(l1pagetable, kernelstack.pv_va, kernelstack.pv_pa,
573 1.1 ichiro UPAGES * NBPG, VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE);
574 1.1 ichiro
575 1.1 ichiro pmap_map_chunk(l1pagetable, kernel_l1pt.pv_va, kernel_l1pt.pv_pa,
576 1.5 thorpej L1_TABLE_SIZE, VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE);
577 1.1 ichiro
578 1.1 ichiro /* Map the page table that maps the kernel pages */
579 1.1 ichiro pmap_map_entry(l1pagetable, kernel_ptpt.pv_va, kernel_ptpt.pv_pa,
580 1.1 ichiro VM_PROT_READ|VM_PROT_WRITE, PTE_NOCACHE);
581 1.1 ichiro
582 1.1 ichiro /*
583 1.1 ichiro * Map entries in the page table used to map PTE's
584 1.1 ichiro * Basically every kernel page table gets mapped here
585 1.1 ichiro */
586 1.1 ichiro /* The -2 is slightly bogus, it should be -log2(sizeof(pt_entry_t)) */
587 1.1 ichiro pmap_map_entry(l1pagetable,
588 1.1 ichiro PTE_BASE + (0x00000000 >> (PGSHIFT-2)),
589 1.1 ichiro kernel_pt_table[KERNEL_PT_SYS].pv_pa,
590 1.7 thorpej VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE);
591 1.1 ichiro
592 1.1 ichiro for (loop = 0; loop < KERNEL_PT_KERNEL_NUM; loop++)
593 1.1 ichiro pmap_map_entry(l1pagetable,
594 1.1 ichiro PTE_BASE + ((KERNEL_BASE +
595 1.1 ichiro (loop * 0x00400000)) >> (PGSHIFT-2)),
596 1.1 ichiro kernel_pt_table[KERNEL_PT_KERNEL + loop].pv_pa,
597 1.7 thorpej VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE);
598 1.1 ichiro
599 1.1 ichiro for (loop = 0; loop < KERNEL_PT_VMDATA_NUM; loop++)
600 1.1 ichiro pmap_map_entry(l1pagetable,
601 1.1 ichiro PTE_BASE + ((KERNEL_VM_BASE +
602 1.1 ichiro (loop * 0x00400000)) >> (PGSHIFT-2)),
603 1.1 ichiro kernel_pt_table[KERNEL_PT_VMDATA + loop].pv_pa,
604 1.7 thorpej VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE);
605 1.1 ichiro
606 1.1 ichiro pmap_map_entry(l1pagetable,
607 1.1 ichiro PTE_BASE + (PTE_BASE >> (PGSHIFT-2)),
608 1.1 ichiro kernel_ptpt.pv_pa, VM_PROT_READ|VM_PROT_WRITE, PTE_NOCACHE);
609 1.1 ichiro
610 1.1 ichiro /* Map the vector page. */
611 1.1 ichiro pmap_map_entry(l1pagetable, vector_page, systempage.pv_pa,
612 1.1 ichiro VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE);
613 1.1 ichiro
614 1.1 ichiro #ifdef VERBOSE_INIT_ARM
615 1.1 ichiro printf("systempage (vector page): p0x%08lx v0x%08lx\n",
616 1.1 ichiro systempage.pv_pa, vector_page);
617 1.1 ichiro #endif
618 1.1 ichiro
619 1.1 ichiro /*
620 1.1 ichiro * Map the PCI I/O spaces and IXP12x0 registers
621 1.1 ichiro */
622 1.1 ichiro
623 1.1 ichiro ixp12x0_pmap_io_reg(l1pagetable);
624 1.1 ichiro ixp12x0_pmap_chunk_table(l1pagetable, map_tbl_ixm1200);
625 1.1 ichiro
626 1.1 ichiro printf("done.\n");
627 1.1 ichiro
628 1.1 ichiro /*
629 1.1 ichiro * Map the Dcache Flush page.
630 1.1 ichiro * Hw Ref Manual 3.2.4.5 Software Dcache Flush
631 1.1 ichiro */
632 1.1 ichiro pmap_map_chunk(l1pagetable, ixp12x0_cache_clean_addr, 0xe0000000,
633 1.1 ichiro CPU_IXP12X0_CACHE_CLEAN_SIZE, VM_PROT_READ, PTE_CACHE);
634 1.1 ichiro
635 1.1 ichiro /*
636 1.1 ichiro * Now we have the real page tables in place so we can switch to them.
637 1.1 ichiro * Once this is done we will be running with the REAL kernel page
638 1.1 ichiro * tables.
639 1.1 ichiro */
640 1.1 ichiro
641 1.1 ichiro /* Switch tables */
642 1.1 ichiro setttb(kernel_l1pt.pv_pa);
643 1.1 ichiro cpu_tlb_flushID();
644 1.1 ichiro
645 1.1 ichiro /*
646 1.1 ichiro * We must now clean the cache again....
647 1.1 ichiro * Cleaning may be done by reading new data to displace any
648 1.1 ichiro * dirty data in the cache. This will have happened in setttb()
649 1.1 ichiro * but since we are boot strapping the addresses used for the read
650 1.1 ichiro * may have just been remapped and thus the cache could be out
651 1.1 ichiro * of sync. A re-clean after the switch will cure this.
652 1.1 ichiro * After booting there are no gross reloations of the kernel thus
653 1.1 ichiro * this problem will not occur after initarm().
654 1.1 ichiro */
655 1.1 ichiro cpu_idcache_wbinv_all();
656 1.1 ichiro
657 1.1 ichiro arm32_vector_init(ARM_VECTORS_LOW, ARM_VEC_ALL);
658 1.1 ichiro
659 1.1 ichiro /*
660 1.1 ichiro * Pages were allocated during the secondary bootstrap for the
661 1.1 ichiro * stacks for different CPU modes.
662 1.1 ichiro * We must now set the r13 registers in the different CPU modes to
663 1.1 ichiro * point to these stacks.
664 1.1 ichiro * Since the ARM stacks use STMFD etc. we must set r13 to the top end
665 1.1 ichiro * of the stack memory.
666 1.1 ichiro */
667 1.1 ichiro printf("init subsystems: stacks ");
668 1.1 ichiro
669 1.1 ichiro set_stackptr(PSR_IRQ32_MODE, irqstack.pv_va + IRQ_STACK_SIZE * NBPG);
670 1.1 ichiro set_stackptr(PSR_ABT32_MODE, abtstack.pv_va + ABT_STACK_SIZE * NBPG);
671 1.1 ichiro set_stackptr(PSR_UND32_MODE, undstack.pv_va + UND_STACK_SIZE * NBPG);
672 1.1 ichiro #ifdef PMAP_DEBUG
673 1.1 ichiro if (pmap_debug_level >= 0)
674 1.1 ichiro printf("kstack V%08lx P%08lx\n", kernelstack.pv_va,
675 1.1 ichiro kernelstack.pv_pa);
676 1.1 ichiro #endif /* PMAP_DEBUG */
677 1.1 ichiro
678 1.1 ichiro /*
679 1.1 ichiro * Well we should set a data abort handler.
680 1.1 ichiro * Once things get going this will change as we will need a proper
681 1.1 ichiro * handler. Until then we will use a handler that just panics but
682 1.1 ichiro * tells us why.
683 1.1 ichiro * Initialisation of the vetcors will just panic on a data abort.
684 1.1 ichiro * This just fills in a slighly better one.
685 1.1 ichiro */
686 1.1 ichiro printf("vectors ");
687 1.1 ichiro data_abort_handler_address = (u_int)data_abort_handler;
688 1.1 ichiro prefetch_abort_handler_address = (u_int)prefetch_abort_handler;
689 1.1 ichiro undefined_handler_address = (u_int)undefinedinstruction_bounce;
690 1.1 ichiro printf("\ndata_abort_handler_address = %08x\n", data_abort_handler_address);
691 1.1 ichiro printf("prefetch_abort_handler_address = %08x\n", prefetch_abort_handler_address);
692 1.1 ichiro printf("undefined_handler_address = %08x\n", undefined_handler_address);
693 1.1 ichiro
694 1.1 ichiro /* Initialise the undefined instruction handlers */
695 1.1 ichiro printf("undefined ");
696 1.1 ichiro undefined_init();
697 1.1 ichiro
698 1.4 thorpej /* Load memory into UVM. */
699 1.4 thorpej printf("page ");
700 1.4 thorpej uvm_setpagesize(); /* initialize PAGE_SIZE-dependent variables */
701 1.4 thorpej uvm_page_physload(atop(physical_freestart), atop(physical_freeend),
702 1.4 thorpej atop(physical_freestart), atop(physical_freeend),
703 1.4 thorpej VM_FREELIST_DEFAULT);
704 1.4 thorpej
705 1.1 ichiro /* Boot strap pmap telling it where the kernel page table is */
706 1.1 ichiro printf("pmap ");
707 1.1 ichiro pmap_bootstrap((pd_entry_t *)kernel_l1pt.pv_va, kernel_ptpt);
708 1.1 ichiro
709 1.1 ichiro /* Setup the IRQ system */
710 1.1 ichiro printf("irq ");
711 1.1 ichiro ixp12x0_intr_init();
712 1.1 ichiro printf("done.\n");
713 1.1 ichiro
714 1.1 ichiro #ifdef VERBOSE_INIT_ARM
715 1.1 ichiro printf("freestart = 0x%08lx, free_pages = %d (0x%x)\n",
716 1.1 ichiro physical_freestart, free_pages, free_pages);
717 1.1 ichiro printf("freemempos=%08lx\n", freemempos);
718 1.1 ichiro printf("switching to new L1 page table @%#lx... \n", kernel_l1pt.pv_pa);
719 1.1 ichiro #endif
720 1.1 ichiro
721 1.1 ichiro consinit();
722 1.1 ichiro printf("consinit \n");
723 1.1 ichiro
724 1.1 ichiro ixdp_ixp12x0_cc_setup();
725 1.1 ichiro
726 1.1 ichiro printf("bootstrap done.\n");
727 1.1 ichiro
728 1.1 ichiro #ifdef IPKDB
729 1.1 ichiro /* Initialise ipkdb */
730 1.1 ichiro ipkdb_init();
731 1.1 ichiro if (boothowto & RB_KDB)
732 1.1 ichiro ipkdb_connect(0);
733 1.1 ichiro #endif /* NIPKDB */
734 1.1 ichiro
735 1.1 ichiro #ifdef DDB
736 1.1 ichiro {
737 1.1 ichiro static struct undefined_handler uh;
738 1.1 ichiro
739 1.1 ichiro uh.uh_handler = db_trapper;
740 1.1 ichiro install_coproc_handler_static(0, &uh);
741 1.1 ichiro }
742 1.1 ichiro ddb_init(symbolsize, ((int *)&end), ((char *)&end) + symbolsize);
743 1.1 ichiro
744 1.1 ichiro if (boothowto & RB_KDB)
745 1.1 ichiro Debugger();
746 1.1 ichiro #endif
747 1.1 ichiro
748 1.1 ichiro /* We return the new stack pointer address */
749 1.1 ichiro return(kernelstack.pv_va + USPACE_SVC_STACK_TOP);
750 1.1 ichiro }
751 1.1 ichiro
752 1.1 ichiro void
753 1.1 ichiro consinit(void)
754 1.1 ichiro {
755 1.1 ichiro extern struct bus_space ixpsip_bs_tag;
756 1.1 ichiro static int consinit_called = 0;
757 1.1 ichiro
758 1.1 ichiro if (consinit_called != 0)
759 1.1 ichiro return;
760 1.1 ichiro
761 1.1 ichiro consinit_called = 1;
762 1.1 ichiro
763 1.1 ichiro if (ixpcomcnattach(&ixpsip_bs_tag, IXPCOM_UART_BASE,
764 1.1 ichiro CONSPEED, CONMODE))
765 1.1 ichiro panic("can't init serial console @%lx", IXPCOM_UART_BASE);
766 1.1 ichiro }
767 1.1 ichiro
768 1.1 ichiro #ifdef DEBUG_BEFOREMMU
769 1.1 ichiro cons_decl(ixpcom);
770 1.1 ichiro void
771 1.1 ichiro fakecninit()
772 1.1 ichiro {
773 1.1 ichiro static struct consdev fakecntab = cons_init(ixpcom);
774 1.1 ichiro cn_tab = &fakecntab;
775 1.1 ichiro
776 1.1 ichiro (*cn_tab->cn_init)(0);
777 1.1 ichiro cn_tab->cn_pri = CN_REMOTE;
778 1.1 ichiro }
779 1.1 ichiro #endif
780 1.1 ichiro
781 1.1 ichiro /*
782 1.1 ichiro * For optimal cache cleaning we need two 16K banks of
783 1.1 ichiro * virtual address space that NOTHING else will access
784 1.1 ichiro * and then we alternate the cache cleaning between the
785 1.1 ichiro * two banks.
786 1.1 ichiro * The cache cleaning code requires requires 2 banks aligned
787 1.1 ichiro * on total size boundry so the banks can be alternated by
788 1.1 ichiro * eorring the size bit (assumes the bank size is a power of 2)
789 1.1 ichiro */
790 1.1 ichiro void
791 1.1 ichiro ixdp_ixp12x0_cc_setup(void)
792 1.1 ichiro {
793 1.1 ichiro int loop;
794 1.1 ichiro paddr_t kaddr;
795 1.1 ichiro pt_entry_t *pte;
796 1.1 ichiro
797 1.1 ichiro (void) pmap_extract(pmap_kernel(), KERNEL_TEXT_BASE, &kaddr);
798 1.1 ichiro for (loop = 0; loop < CPU_IXP12X0_CACHE_CLEAN_SIZE; loop += NBPG) {
799 1.1 ichiro pte = vtopte(ixp12x0_cc_base + loop);
800 1.1 ichiro *pte = L2_S_PROTO | kaddr |
801 1.1 ichiro L2_S_PROT(PTE_KERNEL, VM_PROT_READ) | pte_l2_s_cache_mode;
802 1.6 thorpej PTE_SYNC(pte);
803 1.1 ichiro }
804 1.1 ichiro ixp12x0_cache_clean_addr = ixp12x0_cc_base;
805 1.1 ichiro ixp12x0_cache_clean_size = CPU_IXP12X0_CACHE_CLEAN_SIZE / 2;
806 1.1 ichiro }
807