ixm1200_start.S revision 1.2
1 /* $NetBSD: ixm1200_start.S,v 1.2 2002/07/21 14:26:05 ichiro Exp $ */ 2 3 /* 4 * Copyright (c) 2002 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Ichiro FUKUHARA and Naoto Shimazaki. 9 * 10 * This code is derived from software contributed to The NetBSD Foundation 11 * by Jason R. Thorpe. 12 * 13 * Redistribution and use in source and binary forms, with or without 14 * modification, are permitted provided that the following conditions 15 * are met: 16 * 1. Redistributions of source code must retain the above copyright 17 * notice, this list of conditions and the following disclaimer. 18 * 2. Redistributions in binary form must reproduce the above copyright 19 * notice, this list of conditions and the following disclaimer in the 20 * documentation and/or other materials provided with the distribution. 21 * 3. All advertising materials mentioning features or use of this software 22 * must display the following acknowledgement: 23 * This product includes software developed by the NetBSD 24 * Foundation, Inc. and its contributors. 25 * 4. Neither the name of The NetBSD Foundation nor the names of its 26 * contributors may be used to endorse or promote products derived 27 * from this software without specific prior written permission. 28 * 29 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 30 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 31 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 32 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 33 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 34 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 35 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 36 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 37 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 38 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 39 * POSSIBILITY OF SUCH DAMAGE. 40 */ 41 42 #include "assym.h" 43 44 #include <arm/asm.h> 45 #include <arm/armreg.h> 46 #include <arm/arm32/pte.h> 47 48 .section .start,"ax",%progbits 49 50 .global _C_LABEL(ixm1200_start) 51 _C_LABEL(ixm1200_start): 52 /* 53 * Disable IRQ and FIQ 54 */ 55 mrs r3, cpsr_all 56 orr r1, r3, #(I32_bit | F32_bit) 57 msr cpsr_all, r1 58 59 /* 60 * Setup coprocessor 15. 61 * 62 * We assume we've been loaded VA == PA, or that the MMU is 63 * disabled. We will go ahead and disable the MMU here 64 * so that we don't have to worry about flushing caches, etc. 65 */ 66 67 /* CONTROL_CP15 */ 68 mrc p15, 0, r0, c1, c0 ,0 /* read ctrl */ 69 bic r0, r0, #CPU_CONTROL_MMU_ENABLE 70 bic r0, r0, #CPU_CONTROL_AFLT_ENABLE 71 orr r0, r0, #CPU_CONTROL_DC_ENABLE 72 orr r0, r0, #CPU_CONTROL_WBUF_ENABLE 73 bic r0, r0, #CPU_CONTROL_BEND_ENABLE 74 orr r0, r0, #CPU_CONTROL_SYST_ENABLE 75 bic r0, r0, #CPU_CONTROL_ROM_ENABLE 76 orr r0, r0, #CPU_CONTROL_IC_ENABLE 77 bic r0, r0, #CPU_CONTROL_VECRELOC 78 mcr p15, 0, r0, c1, c0 ,0 /* write ctrl */ 79 80 nop 81 nop 82 nop 83 84 /* TRANSLATION_TABLE_BASE */ 85 mov r0, #0 86 mcr p15, 0, r0, c2, c0 ,0 /* write trans table base */ 87 88 /* DOMAIN_ACCESS_CONTROL */ 89 mov r0, #0x00000001 /* use domain 0 as client */ 90 mcr p15, 0, r0, c3, c0 ,0 /* write domain */ 91 92 /* CACHE_CONTROL_OPERATIONS */ 93 mrc p15, 0, r0, c7, c7 ,0 /* flush D and I cache */ 94 mrc p15, 0, r0, c7, c10 ,4 /* drain write buffer */ 95 96 /* TLB_OPERATIONS */ 97 mcr p15, 0, r0, c8, c7 ,0 /* flush D and I TLB */ 98 99 /* READ_BUFFER_OPERATIONS */ 100 mcr p15, 0, r0, c9, c0 ,0 /* flush all entries */ 101 mcr p15, 0, r0, c9, c0 ,4 /* disable user mode MCR access */ 102 103 /* PROCESS_ID_VIRTUAL_ADDR_MAPPING */ 104 mov r0, #0 105 mcr p15, 0, r0, c13, c0 ,0 /* process ID 0 106 107 /* BREAKPOINT_DEBUG_SUPPORT */ 108 mov r0, #0 109 mcr p15, 0, r0, c15, c0 ,0 /* DBAR = 0 */ 110 mcr p15, 0, r0, c15, c1 ,0 /* DBVR = 0 */ 111 mcr p15, 0, r0, c15, c2 ,0 /* DBMR = 0 */ 112 mcr p15, 0, r0, c15, c3 ,0 /* DBCR = 0 (never watch) */ 113 mcr p15, 0, r0, c15, c8 ,0 /* IBCR = 0 (never watch) */ 114 115 /* 116 * We want to construct a memory map that maps us 117 * VA == PA (SDRAM at 0xc0000000). We create these mappings 118 * uncached and unbuffered to be safe. 119 * 120 * We also want to map the various devices we want to 121 * talk to VA == PA during bootstrap. 122 * 123 * We also want to map the v0xf0000000 == p0x90000000 124 * to output eary bootstrup messages to the console. 125 * 126 * We just use section mappings for all of this to make it easy. 127 * 128 * We will put the L1 table to do all this at c01fc000 129 * where is our KERNEL_TEXT_BASE - sizeof(L1 table). 130 */ 131 132 /* 133 * Step 1: Map the entire address space VA == PA. 134 */ 135 ldr r0, Ltable 136 mov r1, #(L1_TABLE_SIZE / 4) /* 4096 entry */ 137 mov r2, #(L1_S_SIZE) /* 1MB / section */ 138 mov r3, #(L1_S_AP(AP_KRW)) /* kernel read/write */ 139 orr r3, r3, #(L1_TYPE_S) /* L1 entry is section */ 140 1: 141 str r3, [r0], #4 142 add r3, r3, r2 143 subs r1, r1, #1 144 bgt 1b 145 146 /* 147 * Step 2: Map VA 0xf0000000->0xf0100000 to PA 0x90000000->0x90100000. 148 */ 149 ldr r0, Ltable 150 add r0, r0, #(0xf00 * 4) /* offset to 0xf0000000 */ 151 mov r3, #0x90000000 152 add r3, r3, #0x00100000 /* set 0x90100000 to r3 */ 153 orr r3, r3, #(L1_S_AP(AP_KRW)) /* kernel read/write */ 154 orr r3, r3, #(L1_TYPE_S) /* L1 entry is section */ 155 str r3, [r0] 156 157 /* OK! Page table is set up. Give it to the CPU. */ 158 ldr r0, Ltable 159 mcr p15, 0, r0, c2, c0 ,0 /* write trans table base */ 160 mcr p15, 0, r0, c8, c7 ,0 /* flush D and I TLB */ 161 162 /* Get ready to jump to the "real" kernel entry point... */ 163 ldr r0, Lstart 164 165 /* OK, let's enable the MMU. */ 166 mrc p15, 0, r1, c1, c0 ,0 /* read ctrl */ 167 orr r1, r1, #CPU_CONTROL_MMU_ENABLE 168 mcr p15, 0, r1, c1, c0 ,0 /* write ctrl */ 169 170 nop 171 nop 172 nop 173 174 /* CPWAIT sequence to make sure the MMU is on... */ 175 mrc p15, 0, r2, c2, c0, 0 /* arbitrary read of CP15 */ 176 mov r2, r2 /* force it to complete */ 177 mov pc, r0 /* leap to kernel entry point! */ 178 179 Lstart: 180 .word start 181 182 Ltable: 183 .word 0xc0200000 - 0x4000 /* our KERNEL_TEXT_BASE - 16KB */ 184 185 /* end of ixm1200_start.S */ 186
Indexes created Thu Oct 23 22:10:10 GMT 2025