lubbock_start.S revision 1.1
1 /* $NetBSD: lubbock_start.S,v 1.1 2003/06/18 10:51:15 bsh Exp $ */ 2 3 /* 4 * Copyright (c) 2002, 2003 Genetec Corporation. All rights reserved. 5 * Written by Hiroyuki Bessho for Genetec Corporation. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. The name of Genetec Corporation may not be used to endorse or 16 * promote products derived from this software without specific prior 17 * written permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY GENETEC CORPORATION ``AS IS'' AND 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL GENETEC CORPORATION 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <machine/asm.h> 33 #include <arm/armreg.h> 34 #include <arm/arm32/pte.h> 35 #include <arm/arm32/pmap.h> /* for PMAP_DOMAIN_KERNEL */ 36 37 #ifndef SDRAM_START 38 #define SDRAM_START 0xa0000000 39 #endif 40 41 /* 42 * CPWAIT -- Canonical method to wait for CP15 update. 43 * NOTE: Clobbers the specified temp reg. 44 * copied from arm/arm/cpufunc_asm_xscale.S 45 * XXX: better be in a common header file. 46 */ 47 #define CPWAIT_BRANCH \ 48 sub pc, pc, #4 49 50 #define CPWAIT(tmp) \ 51 mrc p15, 0, tmp, c2, c0, 0 /* arbitrary read of CP15 */ ;\ 52 mov tmp, tmp /* wait for it to complete */ ;\ 53 CPWAIT_BRANCH /* branch to next insn */ 54 55 /* 56 * Kernel start routine for DBPXA250 (Lubbock) 57 * this code is excuted at the very first after the kernel is loaded 58 * by RedBoot. 59 */ 60 .text 61 62 .global _C_LABEL(lubbock_start) 63 _C_LABEL(lubbock_start): 64 /* Are we running on ROM ? */ 65 cmp pc, #0x06000000 66 bhi lubbock_start_ram 67 68 /* move me to RAM 69 * XXX: we can use memcpy if it is PIC 70 */ 71 ldr r1, Lcopy_size 72 adr r0, _C_LABEL(lubbock_start) 73 add r1, r1, #3 74 mov r1, r1, LSR #2 75 mov r2, #SDRAM_START 76 add r2, r2, #0x00200000 77 mov r4, r2 78 79 5: ldr r3,[r0],#4 80 str r3,[r2],#4 81 subs r1,r1,#1 82 bhi 5b 83 84 /* Jump to RAM */ 85 ldr r0, Lstart_off 86 add pc, r4, r0 87 88 Lcopy_size: .word _edata-_C_LABEL(lubbock_start) 89 Lstart_off: .word lubbock_start_ram-_C_LABEL(lubbock_start) 90 91 lubbock_start_ram: 92 /* 93 * Kernel is loaded in SDRAM (0xa0200000..), and is expected to run 94 * in VA 0xc0200000.. 95 */ 96 97 mrc p15, 0, r0, c2, c0, 0 /* get ttb prepared by redboot */ 98 adr r4, mmu_init_table2 99 100 #ifdef BUILD_STARTUP_PAGETABLE 101 mrc p15, 0, r2, c1, c0, 0 102 tst r2, #CPU_CONTROL_MMU_ENABLE /* we already have a page table? */ 103 bne 3f 104 105 /* build page table from scratch */ 106 ldr r0, Lstartup_pagetable 107 adr r4, mmu_init_table 108 #endif 109 b 3f 110 111 2: 112 str r3, [r0, r2] 113 add r2, r2, #4 114 add r3, r3, #(L1_S_SIZE) 115 adds r1, r1, #-1 116 bhi 2b 117 3: 118 ldmia r4!, {r1,r2,r3} /* # of sections, PA|attr, VA */ 119 cmp r1, #0 120 bne 2b 121 122 mcr p15, 0, r0, c2, c0, 0 /* Set TTB */ 123 mcr p15, 0, r0, c8, c7, 0 /* Flush TLB */ 124 125 /* Set the Domain Access register. Very important! */ 126 mov r0, #((DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL*2)) | DOMAIN_CLIENT) 127 mcr p15, 0, r0, c3, c0, 0 128 129 /* Enable MMU */ 130 mrc p15, 0, r0, c1, c0, 0 131 orr r0, r0, #CPU_CONTROL_MMU_ENABLE 132 mcr p15, 0, r0, c1, c0, 0 133 CPWAIT(r0) 134 135 /* Jump to kernel code in TRUE VA */ 136 adr r0, Lstart 137 ldr pc, [r0] 138 139 Lstart: 140 .word start 141 142 #define MMU_INIT(va,pa,n_sec,attr) \ 143 .word n_sec ; \ 144 .word 4*((va)>>L1_S_SHIFT) ; \ 145 .word (pa)|(attr) ; 146 147 #ifdef BUILD_STARTUP_PAGETABLE 148 #ifndef STARTUP_PAGETABLE_ADDR 149 #define STARTUP_PAGETABLE_ADDR 0xa0004000 150 #endif 151 Lstartup_pagetable .word STARTUP_PAGETABLE_ADDR 152 mmu_init_table: 153 /* fill all table VA==PA */ 154 MMU_INIT(0x00000000, 0x00000000, 1<<(32-L1_S_SHIFT), L1_TYPE_S|L1_S_AP(AP_KRW)) 155 /* map SDRAM VA==PA, WT cacheable */ 156 MMU_INIT(SDRAM_START, SDRAM_START, 64, L1_TYPE_S|L1_S_C|L1_S_AP(AP_KRW)) 157 #endif 158 mmu_init_table2: 159 /* map VA 0xc0000000..0xc3ffffff to PA 0xa0000000..0xa3ffffff */ 160 MMU_INIT(0xc0000000, SDRAM_START, 64, L1_TYPE_S|L1_S_C|L1_S_AP(AP_KRW)) 161 162 .word 0 /* end of table */ 163
Indexes created Thu Oct 02 01:09:59 GMT 2025