obio.c revision 1.1
1 /* $NetBSD: obio.c,v 1.1 2003/06/18 10:51:15 bsh Exp $ */ 2 3 /* 4 * Copyright (c) 2002, 2003 Genetec Corporation. All rights reserved. 5 * Written by Hiroyuki Bessho for Genetec Corporation. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. The name of Genetec Corporation may not be used to endorse or 16 * promote products derived from this software without specific prior 17 * written permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY GENETEC CORPORATION ``AS IS'' AND 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL GENETEC CORPORATION 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * TODO: dispatch interrupt to SOFTSERIAL or SOFTNET according to requested 34 * interrupt level. 35 */ 36 37 #include <sys/param.h> 38 #include <sys/systm.h> 39 #include <sys/device.h> 40 #include <sys/kernel.h> 41 #include <sys/reboot.h> 42 43 #include <machine/cpu.h> 44 #include <machine/bus.h> 45 #include <machine/intr.h> 46 #include <arm/cpufunc.h> 47 48 #include <arm/mainbus/mainbus.h> 49 #include <arm/xscale/pxa2x0reg.h> 50 #include <arm/xscale/pxa2x0var.h> 51 #include <arm/xscale/pxa2x0_gpio.h> 52 #include <arm/sa11x0/sa11x0_var.h> 53 #include <evbarm/lubbock/lubbock_reg.h> 54 #include <evbarm/lubbock/lubbock_var.h> 55 56 #include "locators.h" 57 58 /* prototypes */ 59 static int obio_match(struct device *, struct cfdata *, void *); 60 static void obio_attach(struct device *, struct device *, void *); 61 static int obio_search(struct device *, struct cfdata *, void *); 62 static int obio_print(void *, const char *); 63 64 /* attach structures */ 65 CFATTACH_DECL(obio, sizeof(struct obio_softc), obio_match, obio_attach, 66 NULL, NULL); 67 68 uint32_t obio_intr_mask; 69 70 static int 71 obio_spurious(void *arg) 72 { 73 int irqno = (int)arg; 74 75 printf("Spurious interrupt %d on On-board peripheral", irqno); 76 return 1; 77 } 78 79 80 /* 81 * interrupt handler for GPIO0 (on-board peripherals) 82 * 83 * On Lubbock, 8 interrupts are ORed through on-board logic, 84 * and routed to GPIO0 of PXA250 processor. 85 */ 86 static int 87 obio_intr(void *arg) 88 { 89 int irqno, pending, mask; 90 struct obio_softc *sc = (struct obio_softc *)arg; 91 int psw; 92 93 mask = sc->sc_obio_intr_mask; /* real irq mask for obio */ 94 95 psw = disable_interrupts(I32_bit|F32_bit); 96 pending = bus_space_read_2(sc->sc_iot, sc->sc_obioreg_ioh, 97 LUBBOCK_INTRCTL); 98 /* Here is a chance to lose some interrupts. 99 * You need to modify FPGA program to avoid it 100 */ 101 bus_space_write_2(sc->sc_iot, sc->sc_obioreg_ioh, LUBBOCK_INTRCTL, 0); 102 restore_interrupts(psw); 103 104 105 pending &= mask; 106 while (pending) { 107 irqno = 0; 108 109 for ( ;pending; ++irqno) { 110 if (0 == (pending & (1U<<irqno))) 111 continue; 112 pending &= ~(1U<<irqno); 113 114 #ifdef notyet 115 /* if ipl of this irq is higher than current spl level, 116 call the handler directly instead of dispatching it to 117 software interrupt. */ 118 if (sc->sc_handler[irqno].level > current_spl_level) { 119 (* sc->sc_handler[irqno].func)( 120 sc->sc_handler[irqno].arg ); 121 } 122 else 123 #endif 124 { 125 /* mask this interrupt until software 126 interrupt is handled. */ 127 sc->sc_obio_intr_pending |= (1U<<irqno); 128 mask &= ~(1U<<irqno); 129 bus_space_write_4(sc->sc_iot, sc->sc_obioreg_ioh, 130 LUBBOCK_INTRMASK, mask); 131 132 /* handle it later */ 133 softintr_schedule(sc->sc_si); 134 } 135 } 136 137 psw = disable_interrupts(I32_bit|F32_bit); 138 pending = bus_space_read_2(sc->sc_iot, sc->sc_obioreg_ioh, 139 LUBBOCK_INTRCTL); 140 bus_space_write_2(sc->sc_iot, sc->sc_obioreg_ioh, 141 LUBBOCK_INTRCTL,0); 142 restore_interrupts(psw); 143 pending &= mask; 144 } 145 146 /* GPIO interrupt is edge triggered. make a pulse 147 to let Cotulla notice when other interrupts are 148 still pending */ 149 bus_space_write_2(sc->sc_iot, sc->sc_obioreg_ioh, LUBBOCK_INTRMASK, 0); 150 bus_space_write_2(sc->sc_iot, sc->sc_obioreg_ioh, LUBBOCK_INTRMASK, mask); 151 return 1; 152 } 153 154 static void 155 obio_softintr(void *arg) 156 { 157 struct obio_softc *sc = (struct obio_softc *)arg; 158 int irqno; 159 int psw; 160 int spl_save = current_spl_level; 161 162 psw = disable_interrupts(I32_bit); 163 while ((irqno = find_first_bit(sc->sc_obio_intr_pending)) >= 0) { 164 sc->sc_obio_intr_pending &= ~(1U<<irqno); 165 166 restore_interrupts(psw); 167 168 _splraise(sc->sc_handler[irqno].level); 169 (* sc->sc_handler[irqno].func)( 170 sc->sc_handler[irqno].arg); 171 splx(spl_save); 172 173 psw = disable_interrupts(I32_bit); 174 } 175 176 bus_space_write_4(sc->sc_iot, sc->sc_obioreg_ioh, 177 LUBBOCK_INTRMASK, sc->sc_obio_intr_mask); 178 179 restore_interrupts(psw); 180 } 181 182 /* 183 * int obio_print(void *aux, const char *name) 184 * print configuration info for children 185 */ 186 187 static int 188 obio_print(void *aux, const char *name) 189 { 190 struct obio_attach_args *oba = (struct obio_attach_args*)aux; 191 192 if (oba->oba_addr != OBIOCF_ADDR_DEFAULT) 193 printf(" addr 0x%lx", oba->oba_addr); 194 if (oba->oba_intr > 0) 195 printf(" intr %d", oba->oba_intr); 196 return (UNCONF); 197 } 198 199 int 200 obio_match(struct device *parent, struct cfdata *match, void *aux) 201 { 202 return 1; 203 } 204 205 void 206 obio_attach(struct device *parent, struct device *self, void *aux) 207 { 208 struct obio_softc *sc = (struct obio_softc*)self; 209 int system_id, baseboard_id, expansion_id, processor_card_id; 210 struct pxaip_attach_args *sa = (struct pxaip_attach_args *)aux; 211 char *processor_card_name; 212 int i; 213 214 215 /* Map on-board FPGA registers */ 216 sc->sc_iot = &pxa2x0_bs_tag; 217 if (bus_space_map(sc->sc_iot, LUBBOCK_OBIO_PBASE, LUBBOCK_OBIO_SIZE, 218 0, &(sc->sc_obioreg_ioh))) { 219 printf("%s: can't map FPGA registers\n", self->dv_xname); 220 } 221 222 system_id = bus_space_read_4(sc->sc_iot, sc->sc_obioreg_ioh, 223 LUBBOCK_SYSTEMID); 224 225 baseboard_id = (system_id>>8) & 0x0f; 226 expansion_id = (system_id>>4) & 0x0f; 227 processor_card_id = system_id & 0x0f; 228 229 switch (processor_card_id) { 230 case 0: processor_card_name = "Cotulla"; break; 231 case 1: processor_card_name = "Sabinal"; break; 232 default: processor_card_name = "(unknown)"; 233 } 234 235 printf(" : baseboard=%d (%s), expansion card=%d, processor card=%d (%s)\n", 236 baseboard_id, 237 baseboard_id==8 ? "DBPXA250(lubbock)" : "(unknown)", 238 expansion_id, 239 processor_card_id, processor_card_name ); 240 241 /* 242 * Mask all interrupts. 243 * They are later unmasked at each device's attach routine. 244 */ 245 bus_space_write_4(sc->sc_iot, sc->sc_obioreg_ioh, 246 LUBBOCK_INTRMASK,0); 247 248 sc->sc_intr = sa->pxa_intr; /* irq no. on ICU. */ 249 sc->sc_obio_intr_mask = 0; /* No interrupt used */ 250 sc->sc_obio_intr_pending = 0; 251 sc->sc_ipl = IPL_BIO; 252 253 for (i=0; i < N_OBIO_IRQ; ++i) { 254 sc->sc_handler[i].func = obio_spurious; 255 sc->sc_handler[i].arg = (void *)i; 256 } 257 258 259 /* 260 * establish interrupt handler. 261 */ 262 #if 0 263 /* 264 * level is lowest at first, and changed when 265 * sub-interrupt handlers are established 266 */ 267 sc->sc_ipl = IPL_BIO; 268 #else 269 /* 270 * level is very high to allow high priority sub-interrupts. 271 */ 272 sc->sc_ipl = IPL_AUDIO; 273 #endif 274 sc->sc_ih = pxa2x0_gpio_intr_establish(0, IST_EDGE_FALLING, sc->sc_ipl, 275 obio_intr, sc); 276 sc->sc_si = softintr_establish(IPL_SOFTNET, obio_softintr, sc); 277 278 279 /* 280 * Attach each devices 281 */ 282 config_search(obio_search, self, NULL); 283 } 284 285 int 286 obio_search(parent, cf, aux) 287 struct device *parent; 288 struct cfdata *cf; 289 void *aux; 290 { 291 struct obio_softc *sc = (struct obio_softc *)parent; 292 struct obio_attach_args oba; 293 294 oba.oba_sc = sc; 295 oba.oba_iot = sc->sc_iot; 296 oba.oba_addr = cf->cf_loc[OBIOCF_ADDR]; 297 oba.oba_intr = cf->cf_loc[OBIOCF_INTR]; 298 299 if (config_match(parent, cf, &oba)) 300 config_attach(parent, cf, &oba, obio_print); 301 302 return 0; 303 } 304 305 void * 306 obio_intr_establish(struct obio_softc *sc, 307 int irq, int ipl, int (*func)(void *), void *arg) 308 { 309 int psw; 310 311 if (irq < 0 || N_OBIO_IRQ <= irq) 312 panic("Bad irq no for obio"); 313 314 psw = disable_interrupts(I32_bit); 315 316 sc->sc_handler[irq].func = func; 317 sc->sc_handler[irq].arg = arg; 318 sc->sc_handler[irq].level = ipl; 319 320 #ifdef notyet 321 if (ipl > sc->sc_ipl) { 322 pxa2x0_update_intr_masks(sc->sc_intr, ipl); 323 sc->sc_ipl = ipl; 324 } 325 #endif 326 327 sc->sc_obio_intr_mask |= (1U << irq); 328 bus_space_write_4(sc->sc_iot, sc->sc_obioreg_ioh, 329 LUBBOCK_INTRMASK, sc->sc_obio_intr_mask); 330 331 enable_interrupts(psw); 332 return &sc->sc_handler[irq]; 333 } 334
Indexes created Thu Oct 02 07:10:07 GMT 2025