sacc_obio.c revision 1.1
1/* $NetBSD: sacc_obio.c,v 1.1 2003/08/09 19:38:53 bsh Exp $ */ 2 3/*- 4 * Copyright (c) 2001 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by IWAMOTO Toshihiro. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39/* 40 * for SA-1111 companion chip on Intel DBPXA250 evaluation board. 41 */ 42 43#include <sys/cdefs.h> 44__KERNEL_RCSID(0, "$NetBSD: sacc_obio.c,v 1.1 2003/08/09 19:38:53 bsh Exp $"); 45 46#include <sys/param.h> 47#include <sys/systm.h> 48#include <sys/mbuf.h> 49#include <sys/socket.h> 50#include <sys/ioctl.h> 51#include <sys/errno.h> 52#include <sys/syslog.h> 53#include <sys/select.h> 54#include <sys/device.h> 55 56#include <net/if.h> 57#include <net/if_dl.h> 58#include <net/if_ether.h> 59#include <net/if_media.h> 60 61#include <machine/intr.h> 62#include <machine/bus.h> 63 64#include <arm/sa11x0/sa1111_reg.h> 65#include <arm/sa11x0/sa1111_var.h> 66#include <arm/xscale/pxa2x0reg.h> 67#include <arm/xscale/pxa2x0var.h> 68#include <arm/xscale/pxa2x0_gpio.h> 69 70#include <evbarm/lubbock/lubbock_reg.h> 71#include <evbarm/lubbock/lubbock_var.h> 72 73 74static void sacc_obio_attach(struct device *, struct device *, void *); 75static int sacc_obio_intr(void *arg); 76 77CFATTACH_DECL(sacc_obio, sizeof(struct sacc_softc), sacc_probe, 78 sacc_obio_attach, NULL, NULL); 79 80#if 0 81#define DPRINTF(arg) printf arg 82#else 83#define DPRINTF(arg) 84#endif 85 86uint16_t cs2_memctl_init = 0x7ff0; 87 88static void 89sacc_obio_attach(parent, self, aux) 90 struct device *parent; 91 struct device *self; 92 void *aux; 93{ 94 int i; 95 u_int32_t skid, tmp; 96 struct sacc_softc *sc = (struct sacc_softc *)self; 97 struct obio_softc *psc = (struct obio_softc *)parent; 98 struct obio_attach_args *sa = aux; 99 bus_space_tag_t iot = sa->oba_iot; 100 bus_space_handle_t memctl_ioh; 101 102 printf("\n"); 103 104 /* Set alternative function for GPIO pings 48..57 on PXA2X0 */ 105 for (i=48; i <= 55; ++i) 106 pxa2x0_gpio_set_function(i, GPIO_ALT_FN_2_OUT); 107 pxa2x0_gpio_set_function(56, GPIO_ALT_FN_1_IN); 108 pxa2x0_gpio_set_function(57, GPIO_ALT_FN_1_IN); 109 110 /* XXX */ 111 if (bus_space_map(iot, PXA2X0_MEMCTL_BASE, PXA2X0_MEMCTL_SIZE, 0, 112 &memctl_ioh)) 113 goto fail; 114 115 tmp = bus_space_read_4(iot, memctl_ioh, MEMCTL_MSC2 ); 116 bus_space_write_4(iot, memctl_ioh, MEMCTL_MSC2, 117 (tmp & 0xffff0000) | cs2_memctl_init ); 118 119 bus_space_unmap(iot, memctl_ioh, PXA2X0_MEMCTL_SIZE); 120 121 sc->sc_piot = sc->sc_iot = iot; 122 sc->sc_gpioh = NULL; /* not used */ 123 124 if (bus_space_map(iot, sa->oba_addr, 0x2000/*size*/, 0, &sc->sc_ioh)) 125 goto fail; 126 127 skid = bus_space_read_4(sc->sc_iot, sc->sc_ioh, SACCSBI_SKID); 128 129 printf("%s: SA1111 rev %d.%d\n", sc->sc_dev.dv_xname, 130 (skid & 0xf0) >> 4, skid & 0xf); 131 132 tmp = bus_space_read_4(sc->sc_iot, sc->sc_ioh, SACCSBI_SKCR); 133 tmp = (tmp & ~SKCR_VCOOFF) | SKCR_PLLBYPASS; 134 bus_space_write_4( sc->sc_iot, sc->sc_ioh, SACCSBI_SKCR, tmp ); 135 136 delay(100); /* XXX */ 137 138 tmp |= SKCR_RCLKEN; 139 bus_space_write_4( sc->sc_iot, sc->sc_ioh, SACCSBI_SKCR, tmp ); 140 141#if 1 142 if( tmp != bus_space_read_4( sc->sc_iot, sc->sc_ioh, SACCSBI_SKCR ) ) 143 printf( "!!! FAIL SKCR\n" ); 144#endif 145 146 /* PCMCIA socket0 power control */ 147 bus_space_write_4( sc->sc_iot, sc->sc_ioh, SACCGPIOA_DVR, 0 ); 148 bus_space_write_4( sc->sc_iot, sc->sc_ioh, SACCGPIOA_DDR, 0 ); 149 150 for(i = 0; i < SACCIC_LEN; i++) 151 sc->sc_intrhand[i] = NULL; 152 153 /* initialize SA1111 interrupt controller */ 154 bus_space_write_4(sc->sc_iot, sc->sc_ioh, SACCIC_INTEN0, 0); 155 bus_space_write_4(sc->sc_iot, sc->sc_ioh, SACCIC_INTEN1, 0); 156 bus_space_write_4(sc->sc_iot, sc->sc_ioh, SACCIC_INTTSTSEL, 0); 157 bus_space_write_4(sc->sc_iot, sc->sc_ioh, 158 SACCIC_INTSTATCLR0, 0xffffffff); 159 bus_space_write_4(sc->sc_iot, sc->sc_ioh, 160 SACCIC_INTSTATCLR1, 0xffffffff); 161 162 /* connect to On-board peripheral interrupt */ 163 obio_intr_establish(psc, sa->oba_intr, 164 IPL_HIGH, sacc_obio_intr, sc ); 165 /* 166 * Attach each devices 167 */ 168 config_search(sa1111_search, self, NULL); 169 170 return; 171 172 fail: 173 printf("%s: unable to map registers\n", sc->sc_dev.dv_xname); 174} 175 176static int 177sacc_obio_intr(void *arg) 178{ 179 int i; 180 struct sacc_intrvec intstat; 181 struct sacc_softc *sc = arg; 182 struct sacc_intrhand *ih; 183 184 intstat.lo = 185 bus_space_read_4(sc->sc_iot, sc->sc_ioh, SACCIC_INTSTATCLR0); 186 intstat.hi = 187 bus_space_read_4(sc->sc_iot, sc->sc_ioh, SACCIC_INTSTATCLR1); 188 DPRINTF(("sacc_obio_intr_dispatch: %x %x\n", intstat.lo, intstat.hi)); 189 190 for( i=0; intstat.lo | intstat.hi ; ++i){ 191 if (intstat.lo & (1U<<i)) { 192 /* 193 * Clear intr status before calling intr handlers. 194 * This cause stray interrupts, but clearing 195 * after calling intr handlers cause intr lossage. 196 */ 197 bus_space_write_4(sc->sc_iot, sc->sc_ioh, 198 SACCIC_INTSTATCLR0, (1U<<i) ); 199 200 for(ih = sc->sc_intrhand[i]; ih; ih = ih->ih_next) 201 softintr_schedule(ih->ih_soft); 202 203 intstat.lo &= ~(1U<<i); 204 } 205 if (intstat.hi & (1U<<i)) { 206 bus_space_write_4(sc->sc_iot, sc->sc_ioh, 207 SACCIC_INTSTATCLR1, 1 << i); 208 for(ih = sc->sc_intrhand[i + 32]; ih; ih = ih->ih_next) 209 softintr_schedule(ih->ih_soft); 210 211 intstat.hi &= ~(1U<<i); 212 } 213 } 214 return 1; 215} 216