sacc_obio.c revision 1.13
1/* $NetBSD: sacc_obio.c,v 1.13 2012/11/12 18:00:39 skrll Exp $ */ 2 3/*- 4 * Copyright (c) 2001 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by IWAMOTO Toshihiro. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32/* 33 * for SA-1111 companion chip on Intel DBPXA250 evaluation board. 34 */ 35 36#include <sys/cdefs.h> 37__KERNEL_RCSID(0, "$NetBSD: sacc_obio.c,v 1.13 2012/11/12 18:00:39 skrll Exp $"); 38 39#include <sys/param.h> 40#include <sys/systm.h> 41#include <sys/mbuf.h> 42#include <sys/socket.h> 43#include <sys/ioctl.h> 44#include <sys/errno.h> 45#include <sys/syslog.h> 46#include <sys/select.h> 47#include <sys/device.h> 48 49#include <net/if.h> 50#include <net/if_dl.h> 51#include <net/if_ether.h> 52#include <net/if_media.h> 53 54#include <machine/intr.h> 55#include <sys/bus.h> 56 57#include <arm/sa11x0/sa1111_reg.h> 58#include <arm/sa11x0/sa1111_var.h> 59#include <arm/xscale/pxa2x0cpu.h> 60#include <arm/xscale/pxa2x0reg.h> 61#include <arm/xscale/pxa2x0var.h> 62#include <arm/xscale/pxa2x0_gpio.h> 63 64#include <evbarm/lubbock/lubbock_reg.h> 65#include <evbarm/lubbock/lubbock_var.h> 66 67 68static int sacc_obio_probe(device_t parent, cfdata_t match, void *aux); 69static void sacc_obio_attach(device_t, device_t, void *); 70static int sacc_obio_intr(void *arg); 71 72CFATTACH_DECL_NEW(sacc_obio, sizeof(struct sacc_softc), sacc_obio_probe, 73 sacc_obio_attach, NULL, NULL); 74 75#if 0 76#define DPRINTF(arg) aprint_normal arg 77#else 78#define DPRINTF(arg) 79#endif 80 81uint16_t cs2_memctl_init = 0x7ff0; 82 83static int 84sacc_obio_probe(device_t parent, cfdata_t match, void *aux) 85{ 86 struct obio_attach_args *oa = aux; 87 struct sa11x0_attach_args sa; 88 89 printf("%s: addr=%lx\n", __func__, oa->oba_addr); 90 91 sa.sa_sc = oa->oba_sc; 92 sa.sa_iot = oa->oba_iot; 93 sa.sa_addr = oa->oba_addr; 94 sa.sa_size = 0x2000; 95 96 return sacc_probe(parent, match, &sa); 97} 98 99static void 100sacc_obio_attach(device_t parent, device_t self, void *aux) 101{ 102 int i; 103 uint32_t skid, tmp; 104 struct sacc_softc *sc = device_private(self); 105 struct obio_softc *psc = device_private(parent); 106 struct obio_attach_args *sa = aux; 107 bus_space_tag_t iot = sa->oba_iot; 108 bus_space_handle_t memctl_ioh; 109 110 aprint_normal("\n"); 111 112 /* Set alternative function for GPIO pings 48..57 on PXA2X0 */ 113 for (i=48; i <= 55; ++i) 114 pxa2x0_gpio_set_function(i, GPIO_ALT_FN_2_OUT); 115 pxa2x0_gpio_set_function(56, GPIO_ALT_FN_1_IN); 116 pxa2x0_gpio_set_function(57, GPIO_ALT_FN_1_IN); 117 118 /* XXX */ 119 if (bus_space_map(iot, PXA2X0_MEMCTL_BASE, PXA2X0_MEMCTL_SIZE, 0, 120 &memctl_ioh)) 121 goto fail; 122 123 tmp = bus_space_read_4(iot, memctl_ioh, MEMCTL_MSC2 ); 124 bus_space_write_4(iot, memctl_ioh, MEMCTL_MSC2, 125 (tmp & 0xffff0000) | cs2_memctl_init ); 126 127 bus_space_unmap(iot, memctl_ioh, PXA2X0_MEMCTL_SIZE); 128 129 sc->sc_dev = self; 130 sc->sc_piot = sc->sc_iot = iot; 131 sc->sc_gpioh = 0; /* not used */ 132 133 if (bus_space_map(iot, sa->oba_addr, 0x2000/*size*/, 0, &sc->sc_ioh)) 134 goto fail; 135 136 skid = bus_space_read_4(sc->sc_iot, sc->sc_ioh, SACCSBI_SKID); 137 138 aprint_normal_dev(self, "SA1111 rev %d.%d\n", 139 (skid & 0xf0) >> 4, skid & 0xf); 140 141 tmp = bus_space_read_4(sc->sc_iot, sc->sc_ioh, SACCSBI_SKCR); 142 tmp = (tmp & ~SKCR_VCOOFF) | SKCR_PLLBYPASS; 143 bus_space_write_4( sc->sc_iot, sc->sc_ioh, SACCSBI_SKCR, tmp ); 144 145 delay(100); /* XXX */ 146 147 tmp |= SKCR_RCLKEN; 148 bus_space_write_4( sc->sc_iot, sc->sc_ioh, SACCSBI_SKCR, tmp ); 149 150#if 1 151 if( tmp != bus_space_read_4( sc->sc_iot, sc->sc_ioh, SACCSBI_SKCR ) ) 152 printf( "!!! FAIL SKCR\n" ); 153#endif 154 155 /* PCMCIA socket0 power control */ 156 bus_space_write_4( sc->sc_iot, sc->sc_ioh, SACCGPIOA_DVR, 0 ); 157 bus_space_write_4( sc->sc_iot, sc->sc_ioh, SACCGPIOA_DDR, 0 ); 158 159 for(i = 0; i < SACCIC_LEN; i++) 160 sc->sc_intrhand[i] = NULL; 161 162 /* initialize SA1111 interrupt controller */ 163 bus_space_write_4(sc->sc_iot, sc->sc_ioh, SACCIC_INTEN0, 0); 164 bus_space_write_4(sc->sc_iot, sc->sc_ioh, SACCIC_INTEN1, 0); 165 bus_space_write_4(sc->sc_iot, sc->sc_ioh, SACCIC_INTTSTSEL, 0); 166 bus_space_write_4(sc->sc_iot, sc->sc_ioh, 167 SACCIC_INTSTATCLR0, 0xffffffff); 168 bus_space_write_4(sc->sc_iot, sc->sc_ioh, 169 SACCIC_INTSTATCLR1, 0xffffffff); 170 171 /* connect to On-board peripheral interrupt */ 172 obio_intr_establish(psc, sa->oba_intr, 173 IPL_HIGH, sacc_obio_intr, sc ); 174 /* 175 * Attach each devices 176 */ 177 config_search_ia(sa1111_search, self, "sacc", NULL); 178 179 return; 180 181 fail: 182 aprint_normal_dev(self, "unable to map registers\n"); 183} 184 185static int 186sacc_obio_intr(void *arg) 187{ 188 int i; 189 struct sacc_intrvec intstat; 190 struct sacc_softc *sc = arg; 191 struct sacc_intrhand *ih; 192 193 intstat.lo = 194 bus_space_read_4(sc->sc_iot, sc->sc_ioh, SACCIC_INTSTATCLR0); 195 intstat.hi = 196 bus_space_read_4(sc->sc_iot, sc->sc_ioh, SACCIC_INTSTATCLR1); 197 DPRINTF(("sacc_obio_intr_dispatch: %x %x\n", intstat.lo, intstat.hi)); 198 199 while ((i = find_first_bit(intstat.lo)) >= 0) { 200 201 /* 202 * Clear intr status before calling intr handlers. 203 * This cause stray interrupts, but clearing 204 * after calling intr handlers cause intr lossage. 205 */ 206 bus_space_write_4(sc->sc_iot, sc->sc_ioh, 207 SACCIC_INTSTATCLR0, 1U<<i ); 208 209 for(ih = sc->sc_intrhand[i]; ih; ih = ih->ih_next) 210 softint_schedule(ih->ih_soft); 211 212 intstat.lo &= ~(1U<<i); 213 } 214 215 while ((i = find_first_bit(intstat.hi)) >= 0) { 216 bus_space_write_4(sc->sc_iot, sc->sc_ioh, 217 SACCIC_INTSTATCLR1, 1U<<i); 218 219 for(ih = sc->sc_intrhand[i + 32]; ih; ih = ih->ih_next) 220 softint_schedule(ih->ih_soft); 221 222 intstat.hi &= ~(1U<<i); 223 } 224 225 return 1; 226} 227