marvell_machdep.c revision 1.21
1 /* $NetBSD: marvell_machdep.c,v 1.21 2012/12/12 00:03:11 matt Exp $ */ 2 /* 3 * Copyright (c) 2007, 2008, 2010 KIYOHARA Takashi 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 17 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 18 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 19 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 20 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 21 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 23 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 24 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 */ 27 #include <sys/cdefs.h> 28 __KERNEL_RCSID(0, "$NetBSD: marvell_machdep.c,v 1.21 2012/12/12 00:03:11 matt Exp $"); 29 30 #include "opt_evbarm_boardtype.h" 31 #include "opt_ddb.h" 32 #include "opt_pci.h" 33 #include "opt_mvsoc.h" 34 #include "com.h" 35 #include "gtpci.h" 36 #include "mvpex.h" 37 38 #include <sys/param.h> 39 #include <sys/kernel.h> 40 #include <sys/reboot.h> 41 #include <sys/systm.h> 42 #include <sys/termios.h> 43 44 #include <prop/proplib.h> 45 46 #include <dev/cons.h> 47 #include <dev/md.h> 48 49 #include <dev/marvell/marvellreg.h> 50 #include <dev/marvell/marvellvar.h> 51 #include <dev/pci/pcireg.h> 52 #include <dev/pci/pcivar.h> 53 54 #include <machine/autoconf.h> 55 #include <machine/bootconfig.h> 56 #include <machine/pci_machdep.h> 57 58 #include <uvm/uvm_extern.h> 59 60 #include <arm/db_machdep.h> 61 #include <arm/undefined.h> 62 #include <arm/arm32/machdep.h> 63 64 #include <arm/marvell/mvsocreg.h> 65 #include <arm/marvell/mvsocvar.h> 66 #include <arm/marvell/orionreg.h> 67 #include <arm/marvell/kirkwoodreg.h> 68 #include <arm/marvell/mvsocgppvar.h> 69 70 #include <evbarm/marvell/marvellreg.h> 71 #include <evbarm/marvell/marvellvar.h> 72 73 #include <ddb/db_extern.h> 74 #include <ddb/db_sym.h> 75 76 #include "ksyms.h" 77 78 79 /* Kernel text starts 2MB in from the bottom of the kernel address space. */ 80 #define KERNEL_TEXT_BASE (KERNEL_BASE + 0x00000000) 81 #define KERNEL_VM_BASE (KERNEL_BASE + 0x02000000) 82 83 /* 84 * The range 0xc2000000 - 0xdfffffff is available for kernel VM space 85 * Core-logic registers and I/O mappings occupy 0xfe000000 - 0xffffffff 86 */ 87 #define KERNEL_VM_SIZE 0x1e000000 88 89 BootConfig bootconfig; /* Boot config storage */ 90 static char bootargs[MAX_BOOT_STRING]; 91 char *boot_args = NULL; 92 93 extern int KERNEL_BASE_phys[]; 94 extern char _end[]; 95 96 /* 97 * Macros to translate between physical and virtual for a subset of the 98 * kernel address space. *Not* for general use. 99 */ 100 #define KERNEL_BASE_PHYS physical_start 101 #define KERN_VTOPHYS(va) \ 102 ((paddr_t)((vaddr_t)va - KERNEL_BASE + KERNEL_BASE_PHYS)) 103 #define KERN_PHYSTOV(pa) \ 104 ((vaddr_t)((paddr_t)pa - KERNEL_BASE_PHYS + KERNEL_BASE)) 105 106 107 #include "com.h" 108 #if NCOM > 0 109 #include <dev/ic/comreg.h> 110 #include <dev/ic/comvar.h> 111 #endif 112 113 #ifndef CONSPEED 114 #define CONSPEED B115200 /* It's a setting of the default of u-boot */ 115 #endif 116 #ifndef CONMODE 117 #define CONMODE ((TTYDEF_CFLAG & ~(CSIZE | CSTOPB | PARENB)) | CS8) /* 8N1 */ 118 119 int comcnspeed = CONSPEED; 120 int comcnmode = CONMODE; 121 #endif 122 123 #include "opt_kgdb.h" 124 #ifdef KGDB 125 #include <sys/kgdb.h> 126 #endif 127 128 static void marvell_device_register(device_t, void *); 129 #if NGTPCI > 0 || NMVPEX > 0 130 static void marvell_startend_by_tag(int, uint64_t *, uint64_t *); 131 #endif 132 133 static void 134 marvell_system_reset(void) 135 { 136 /* unmask soft reset */ 137 write_mlmbreg(MVSOC_MLMB_RSTOUTNMASKR, 138 MVSOC_MLMB_RSTOUTNMASKR_SOFTRSTOUTEN); 139 /* assert soft reset */ 140 write_mlmbreg(MVSOC_MLMB_SSRR, MVSOC_MLMB_SSRR_SYSTEMSOFTRST); 141 /* if we're still running, jump to the reset address */ 142 cpu_reset_address = 0; 143 cpu_reset_address_paddr = 0xffff0000; 144 cpu_reset(); 145 /*NOTREACHED*/ 146 } 147 148 static inline 149 pd_entry_t * 150 read_ttb(void) 151 { 152 long ttb; 153 154 __asm volatile("mrc p15, 0, %0, c2, c0, 0" : "=r" (ttb)); 155 156 return (pd_entry_t *)(ttb & ~((1<<14)-1)); 157 } 158 159 /* 160 * Static device mappings. These peripheral registers are mapped at 161 * fixed virtual addresses very early in initarm() so that we can use 162 * them while booting the kernel, and stay at the same address 163 * throughout whole kernel's life time. 164 * 165 * We use this table twice; once with bootstrap page table, and once 166 * with kernel's page table which we build up in initarm(). 167 * 168 * Since we map these registers into the bootstrap page table using 169 * pmap_devmap_bootstrap() which calls pmap_map_chunk(), we map 170 * registers segment-aligned and segment-rounded in order to avoid 171 * using the 2nd page tables. 172 */ 173 #define _A(a) ((a) & ~L1_S_OFFSET) 174 #define _S(s) (((s) + L1_S_SIZE - 1) & ~(L1_S_SIZE-1)) 175 176 static const struct pmap_devmap marvell_devmap[] = { 177 { 178 MARVELL_INTERREGS_VBASE, 179 _A(MARVELL_INTERREGS_PBASE), 180 _S(MARVELL_INTERREGS_SIZE), 181 VM_PROT_READ|VM_PROT_WRITE, 182 PTE_NOCACHE, 183 }, 184 185 { 0, 0, 0, 0, 0 } 186 }; 187 188 #undef _A 189 #undef _S 190 191 extern uint32_t *u_boot_args[]; 192 193 /* 194 * u_int initarm(...) 195 * 196 * Initial entry point on startup. This gets called before main() is 197 * entered. 198 * It should be responsible for setting up everything that must be 199 * in place when main is called. 200 * This includes 201 * Taking a copy of the boot configuration structure. 202 * Initialising the physical console so characters can be printed. 203 * Setting up page tables for the kernel 204 * Relocating the kernel to the bottom of physical memory 205 */ 206 u_int 207 initarm(void *arg) 208 { 209 uint32_t target, attr, base, size; 210 int cs, memtag = 0, iotag = 0, window; 211 212 /* Use the mapped reset routine! */ 213 cpu_reset_address = marvell_system_reset; 214 215 mvsoc_bootstrap(MARVELL_INTERREGS_VBASE); 216 217 /* map some peripheral registers */ 218 pmap_devmap_bootstrap((vaddr_t)read_ttb(), marvell_devmap); 219 220 /* Get ready for splfoo() */ 221 switch (mvsoc_model()) { 222 #ifdef ORION 223 case MARVELL_ORION_1_88F1181: 224 case MARVELL_ORION_1_88F5082: 225 case MARVELL_ORION_1_88F5180N: 226 case MARVELL_ORION_1_88F5181: 227 case MARVELL_ORION_1_88F5182: 228 case MARVELL_ORION_1_88F6082: 229 case MARVELL_ORION_1_88F6183: 230 case MARVELL_ORION_1_88W8660: 231 case MARVELL_ORION_2_88F1281: 232 case MARVELL_ORION_2_88F5281: 233 orion_intr_bootstrap(); 234 235 memtag = ORION_TAG_PEX0_MEM; 236 iotag = ORION_TAG_PEX0_IO; 237 nwindow = ORION_MLMB_NWINDOW; 238 nremap = ORION_MLMB_NREMAP; 239 240 orion_getclks(MARVELL_INTERREGS_VBASE); 241 break; 242 #endif /* ORION */ 243 244 #ifdef KIRKWOOD 245 case MARVELL_KIRKWOOD_88F6180: 246 case MARVELL_KIRKWOOD_88F6192: 247 case MARVELL_KIRKWOOD_88F6281: 248 case MARVELL_KIRKWOOD_88F6282: 249 kirkwood_intr_bootstrap(); 250 251 memtag = KIRKWOOD_TAG_PEX_MEM; 252 iotag = KIRKWOOD_TAG_PEX_IO; 253 nwindow = KIRKWOOD_MLMB_NWINDOW; 254 nremap = KIRKWOOD_MLMB_NREMAP; 255 256 kirkwood_getclks(MARVELL_INTERREGS_VBASE); 257 break; 258 #endif /* KIRKWOOD */ 259 260 #ifdef MV78XX0 261 case MARVELL_MV78XX0_MV78100: 262 case MARVELL_MV78XX0_MV78200: 263 mv78xx0_intr_bootstrap(); 264 265 memtag = MV78XX0_TAG_PEX_MEM; 266 iotag = MV78XX0_TAG_PEX_IO; 267 nwindow = MV78XX0_MLMB_NWINDOW; 268 nremap = MV78XX0_MLMB_NREMAP; 269 270 mv78xx0_getclks(MARVELL_INTERREGS_VBASE); 271 break; 272 #endif /* MV78XX0 */ 273 274 default: 275 /* We can't output console here yet... */ 276 panic("unknown model...\n"); 277 278 /* NOTREACHED */ 279 } 280 281 /* Reset PCI-Express space to window register. */ 282 window = mvsoc_target(memtag, &target, &attr, NULL, NULL); 283 write_mlmbreg(MVSOC_MLMB_WCR(window), 284 MVSOC_MLMB_WCR_WINEN | 285 MVSOC_MLMB_WCR_TARGET(target) | 286 MVSOC_MLMB_WCR_ATTR(attr) | 287 MVSOC_MLMB_WCR_SIZE(MARVELL_PEXMEM_SIZE)); 288 write_mlmbreg(MVSOC_MLMB_WBR(window), 289 MARVELL_PEXMEM_PBASE & MVSOC_MLMB_WBR_BASE_MASK); 290 #ifdef PCI_NETBSD_CONFIGURE 291 if (window < nremap) { 292 write_mlmbreg(MVSOC_MLMB_WRLR(window), 293 MARVELL_PEXMEM_PBASE & MVSOC_MLMB_WRLR_REMAP_MASK); 294 write_mlmbreg(MVSOC_MLMB_WRHR(window), 0); 295 } 296 #endif 297 window = mvsoc_target(iotag, &target, &attr, NULL, NULL); 298 write_mlmbreg(MVSOC_MLMB_WCR(window), 299 MVSOC_MLMB_WCR_WINEN | 300 MVSOC_MLMB_WCR_TARGET(target) | 301 MVSOC_MLMB_WCR_ATTR(attr) | 302 MVSOC_MLMB_WCR_SIZE(MARVELL_PEXIO_SIZE)); 303 write_mlmbreg(MVSOC_MLMB_WBR(window), 304 MARVELL_PEXIO_PBASE & MVSOC_MLMB_WBR_BASE_MASK); 305 #ifdef PCI_NETBSD_CONFIGURE 306 if (window < nremap) { 307 write_mlmbreg(MVSOC_MLMB_WRLR(window), 308 MARVELL_PEXIO_PBASE & MVSOC_MLMB_WRLR_REMAP_MASK); 309 write_mlmbreg(MVSOC_MLMB_WRHR(window), 0); 310 } 311 #endif 312 313 /* 314 * Heads up ... Setup the CPU / MMU / TLB functions 315 */ 316 if (set_cpufuncs()) 317 panic("cpu not recognized!"); 318 319 /* 320 * U-Boot doesn't use the virtual memory. 321 * 322 * Physical Address Range Description 323 * ----------------------- ---------------------------------- 324 * 0x00000000 - 0x0fffffff SDRAM Bank 0 (max 256MB) 325 * 0x10000000 - 0x1fffffff SDRAM Bank 1 (max 256MB) 326 * 0x20000000 - 0x2fffffff SDRAM Bank 2 (max 256MB) 327 * 0x30000000 - 0x3fffffff SDRAM Bank 3 (max 256MB) 328 * 0xf1000000 - 0xf10fffff SoC Internal Registers 329 */ 330 331 cpu_domains((DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL*2)) | DOMAIN_CLIENT); 332 333 consinit(); 334 335 /* Talk to the user */ 336 #ifndef EVBARM_BOARDTYPE 337 #define EVBARM_BOARDTYPE Marvell 338 #endif 339 #define BDSTR(s) _BDSTR(s) 340 #define _BDSTR(s) #s 341 printf("\nNetBSD/evbarm (" BDSTR(EVBARM_BOARDTYPE) ") booting ...\n"); 342 343 /* copy command line U-Boot gave us, if args is valid. */ 344 if (u_boot_args[3] != 0) /* XXXXX: need more check?? */ 345 strncpy(bootargs, (char *)u_boot_args[3], sizeof(bootargs)); 346 347 #ifdef VERBOSE_INIT_ARM 348 printf("initarm: Configuring system ...\n"); 349 #endif 350 351 bootconfig.dramblocks = 0; 352 paddr_t segment_end; 353 segment_end = physmem = 0; 354 for (cs = MARVELL_TAG_SDRAM_CS0; cs <= MARVELL_TAG_SDRAM_CS3; cs++) { 355 mvsoc_target(cs, &target, &attr, &base, &size); 356 if (size == 0) 357 continue; 358 359 bootconfig.dram[bootconfig.dramblocks].address = base; 360 bootconfig.dram[bootconfig.dramblocks].pages = size / PAGE_SIZE; 361 362 if (base != segment_end) 363 panic("memory hole not support"); 364 365 segment_end += size; 366 physmem += size / PAGE_SIZE; 367 368 bootconfig.dramblocks++; 369 } 370 371 arm32_bootmem_init(0, segment_end, (uintptr_t) KERNEL_BASE_phys); 372 arm32_kernel_vm_init(KERNEL_VM_BASE, ARM_VECTORS_HIGH, 0, 373 marvell_devmap, false); 374 375 /* we've a specific device_register routine */ 376 evbarm_device_register = marvell_device_register; 377 378 /* parse bootargs from U-Boot */ 379 boot_args = bootargs; 380 parse_mi_bootargs(boot_args); 381 382 return initarm_common(KERNEL_VM_BASE, KERNEL_VM_SIZE, NULL, 0); 383 } 384 385 void 386 consinit(void) 387 { 388 static int consinit_called = 0; 389 390 if (consinit_called != 0) 391 return; 392 393 consinit_called = 1; 394 395 #if NCOM > 0 396 { 397 extern int mvuart_cnattach(bus_space_tag_t, bus_addr_t, int, 398 uint32_t, int); 399 400 if (mvuart_cnattach(&mvsoc_bs_tag, 401 MARVELL_INTERREGS_VBASE + MVSOC_COM0_BASE, 402 comcnspeed, mvTclk, comcnmode)) 403 panic("can't init serial console"); 404 } 405 #else 406 panic("serial console not configured"); 407 #endif 408 } 409 410 411 static void 412 marvell_device_register(device_t dev, void *aux) 413 { 414 prop_dictionary_t dict = device_properties(dev); 415 416 #if NCOM > 0 417 if (device_is_a(dev, "com") && 418 device_is_a(device_parent(dev), "mvsoc")) 419 prop_dictionary_set_uint32(dict, "frequency", mvTclk); 420 #endif 421 if (device_is_a(dev, "gtidmac")) 422 prop_dictionary_set_uint32(dict, 423 "dmb_speed", mvTclk * sizeof(uint32_t)); /* XXXXXX */ 424 #if NGTPCI > 0 && defined(ORION) 425 if (device_is_a(dev, "gtpci")) { 426 extern struct bus_space 427 orion_pci_io_bs_tag, orion_pci_mem_bs_tag; 428 extern struct arm32_pci_chipset arm32_gtpci_chipset; 429 430 prop_data_t io_bs_tag, mem_bs_tag, pc; 431 prop_array_t int2gpp; 432 prop_number_t gpp; 433 uint64_t start, end; 434 int i, j; 435 static struct { 436 const char *boardtype; 437 int pin[PCI_INTERRUPT_PIN_MAX]; 438 } hints[] = { 439 { "kuronas_x4", 440 { 11, PCI_INTERRUPT_PIN_NONE } }, 441 442 { NULL, 443 { PCI_INTERRUPT_PIN_NONE } }, 444 }; 445 446 arm32_gtpci_chipset.pc_conf_v = device_private(dev); 447 arm32_gtpci_chipset.pc_intr_v = device_private(dev); 448 449 io_bs_tag = prop_data_create_data_nocopy( 450 &orion_pci_io_bs_tag, sizeof(struct bus_space)); 451 KASSERT(io_bs_tag != NULL); 452 prop_dictionary_set(dict, "io-bus-tag", io_bs_tag); 453 prop_object_release(io_bs_tag); 454 mem_bs_tag = prop_data_create_data_nocopy( 455 &orion_pci_mem_bs_tag, sizeof(struct bus_space)); 456 KASSERT(mem_bs_tag != NULL); 457 prop_dictionary_set(dict, "mem-bus-tag", mem_bs_tag); 458 prop_object_release(mem_bs_tag); 459 460 pc = prop_data_create_data_nocopy(&arm32_gtpci_chipset, 461 sizeof(struct arm32_pci_chipset)); 462 KASSERT(pc != NULL); 463 prop_dictionary_set(dict, "pci-chipset", pc); 464 prop_object_release(pc); 465 466 marvell_startend_by_tag(ORION_TAG_PCI_IO, &start, &end); 467 prop_dictionary_set_uint64(dict, "iostart", start); 468 prop_dictionary_set_uint64(dict, "ioend", end); 469 marvell_startend_by_tag(ORION_TAG_PCI_MEM, &start, &end); 470 prop_dictionary_set_uint64(dict, "memstart", start); 471 prop_dictionary_set_uint64(dict, "memend", end); 472 prop_dictionary_set_uint32(dict, 473 "cache-line-size", arm_dcache_align); 474 475 /* Setup the hint for interrupt-pin. */ 476 #define BDSTR(s) _BDSTR(s) 477 #define _BDSTR(s) #s 478 #define THIS_BOARD(str) (strcmp(str, BDSTR(EVBARM_BOARDTYPE)) == 0) 479 for (i = 0; hints[i].boardtype != NULL; i++) 480 if (THIS_BOARD(hints[i].boardtype)) 481 break; 482 if (hints[i].boardtype == NULL) 483 return; 484 485 int2gpp = 486 prop_array_create_with_capacity(PCI_INTERRUPT_PIN_MAX + 1); 487 488 /* first set dummy */ 489 gpp = prop_number_create_integer(0); 490 prop_array_add(int2gpp, gpp); 491 prop_object_release(gpp); 492 493 for (j = 0; hints[i].pin[j] != PCI_INTERRUPT_PIN_NONE; j++) { 494 gpp = prop_number_create_integer(hints[i].pin[j]); 495 prop_array_add(int2gpp, gpp); 496 prop_object_release(gpp); 497 } 498 prop_dictionary_set(dict, "int2gpp", int2gpp); 499 } 500 #endif /* NGTPCI > 0 && defined(ORION) */ 501 #if NMVPEX > 0 502 if (device_is_a(dev, "mvpex")) { 503 #ifdef ORION 504 extern struct bus_space 505 orion_pex0_io_bs_tag, orion_pex0_mem_bs_tag, 506 orion_pex1_io_bs_tag, orion_pex1_mem_bs_tag; 507 #endif 508 #ifdef KIRKWOOD 509 extern struct bus_space 510 kirkwood_pex_io_bs_tag, kirkwood_pex_mem_bs_tag, 511 kirkwood_pex1_io_bs_tag, kirkwood_pex1_mem_bs_tag; 512 #endif 513 extern struct arm32_pci_chipset arm32_mvpex0_chipset; 514 #if defined(ORION) || defined(KIRKWOOD) 515 extern struct arm32_pci_chipset arm32_mvpex1_chipset; 516 517 struct marvell_attach_args *mva = aux; 518 #endif 519 struct bus_space *mvpex_io_bs_tag, *mvpex_mem_bs_tag; 520 struct arm32_pci_chipset *arm32_mvpex_chipset; 521 prop_data_t io_bs_tag, mem_bs_tag, pc; 522 uint64_t start, end; 523 int iotag, memtag; 524 525 switch (mvsoc_model()) { 526 #ifdef ORION 527 case MARVELL_ORION_1_88F5180N: 528 case MARVELL_ORION_1_88F5181: 529 case MARVELL_ORION_1_88F5182: 530 case MARVELL_ORION_1_88W8660: 531 case MARVELL_ORION_2_88F5281: 532 if (mva->mva_offset == MVSOC_PEX_BASE) { 533 mvpex_io_bs_tag = &orion_pex0_io_bs_tag; 534 mvpex_mem_bs_tag = &orion_pex0_mem_bs_tag; 535 arm32_mvpex_chipset = &arm32_mvpex0_chipset; 536 iotag = ORION_TAG_PEX0_IO; 537 memtag = ORION_TAG_PEX0_MEM; 538 } else { 539 mvpex_io_bs_tag = &orion_pex1_io_bs_tag; 540 mvpex_mem_bs_tag = &orion_pex1_mem_bs_tag; 541 arm32_mvpex_chipset = &arm32_mvpex1_chipset; 542 iotag = ORION_TAG_PEX1_IO; 543 memtag = ORION_TAG_PEX1_MEM; 544 } 545 break; 546 #endif 547 548 #ifdef KIRKWOOD 549 case MARVELL_KIRKWOOD_88F6282: 550 if (mva->mva_offset != MVSOC_PEX_BASE) { 551 mvpex_io_bs_tag = &kirkwood_pex1_io_bs_tag; 552 mvpex_mem_bs_tag = &kirkwood_pex1_mem_bs_tag; 553 arm32_mvpex_chipset = &arm32_mvpex1_chipset; 554 iotag = KIRKWOOD_TAG_PEX1_IO; 555 memtag = KIRKWOOD_TAG_PEX1_MEM; 556 break; 557 } 558 559 /* FALLTHROUGH */ 560 561 case MARVELL_KIRKWOOD_88F6180: 562 case MARVELL_KIRKWOOD_88F6192: 563 case MARVELL_KIRKWOOD_88F6281: 564 mvpex_io_bs_tag = &kirkwood_pex_io_bs_tag; 565 mvpex_mem_bs_tag = &kirkwood_pex_mem_bs_tag; 566 arm32_mvpex_chipset = &arm32_mvpex0_chipset; 567 iotag = KIRKWOOD_TAG_PEX_IO; 568 memtag = KIRKWOOD_TAG_PEX_MEM; 569 break; 570 #endif 571 572 default: 573 return; 574 } 575 576 arm32_mvpex_chipset->pc_conf_v = device_private(dev); 577 arm32_mvpex_chipset->pc_intr_v = device_private(dev); 578 579 io_bs_tag = prop_data_create_data_nocopy( 580 mvpex_io_bs_tag, sizeof(struct bus_space)); 581 KASSERT(io_bs_tag != NULL); 582 prop_dictionary_set(dict, "io-bus-tag", io_bs_tag); 583 prop_object_release(io_bs_tag); 584 mem_bs_tag = prop_data_create_data_nocopy( 585 mvpex_mem_bs_tag, sizeof(struct bus_space)); 586 KASSERT(mem_bs_tag != NULL); 587 prop_dictionary_set(dict, "mem-bus-tag", mem_bs_tag); 588 prop_object_release(mem_bs_tag); 589 590 pc = prop_data_create_data_nocopy(arm32_mvpex_chipset, 591 sizeof(struct arm32_pci_chipset)); 592 KASSERT(pc != NULL); 593 prop_dictionary_set(dict, "pci-chipset", pc); 594 prop_object_release(pc); 595 596 marvell_startend_by_tag(iotag, &start, &end); 597 prop_dictionary_set_uint64(dict, "iostart", start); 598 prop_dictionary_set_uint64(dict, "ioend", end); 599 marvell_startend_by_tag(memtag, &start, &end); 600 prop_dictionary_set_uint64(dict, "memstart", start); 601 prop_dictionary_set_uint64(dict, "memend", end); 602 prop_dictionary_set_uint32(dict, 603 "cache-line-size", arm_dcache_align); 604 } 605 #endif 606 } 607 608 #if NGTPCI > 0 || NMVPEX > 0 609 static void 610 marvell_startend_by_tag(int tag, uint64_t *start, uint64_t *end) 611 { 612 uint32_t base, size; 613 int win; 614 615 win = mvsoc_target(tag, NULL, NULL, &base, &size); 616 if (size != 0) { 617 if (win < nremap) 618 *start = read_mlmbreg(MVSOC_MLMB_WRLR(win)) | 619 ((read_mlmbreg(MVSOC_MLMB_WRHR(win)) << 16) << 16); 620 else 621 *start = base; 622 *end = *start + size - 1; 623 } 624 } 625 #endif 626
Indexes created Tue Sep 30 20:09:53 GMT 2025