marvell_machdep.c revision 1.22
1 /* $NetBSD: marvell_machdep.c,v 1.22 2013/09/30 12:57:53 kiyohara Exp $ */ 2 /* 3 * Copyright (c) 2007, 2008, 2010 KIYOHARA Takashi 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 17 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 18 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 19 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 20 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 21 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 23 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 24 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 */ 27 #include <sys/cdefs.h> 28 __KERNEL_RCSID(0, "$NetBSD: marvell_machdep.c,v 1.22 2013/09/30 12:57:53 kiyohara Exp $"); 29 30 #include "opt_evbarm_boardtype.h" 31 #include "opt_ddb.h" 32 #include "opt_pci.h" 33 #include "opt_mvsoc.h" 34 #include "com.h" 35 #include "gtpci.h" 36 #include "mvpex.h" 37 38 #include <sys/param.h> 39 #include <sys/kernel.h> 40 #include <sys/reboot.h> 41 #include <sys/systm.h> 42 #include <sys/termios.h> 43 44 #include <prop/proplib.h> 45 46 #include <dev/cons.h> 47 #include <dev/md.h> 48 49 #include <dev/marvell/marvellreg.h> 50 #include <dev/marvell/marvellvar.h> 51 #include <dev/pci/pcireg.h> 52 #include <dev/pci/pcivar.h> 53 54 #include <machine/autoconf.h> 55 #include <machine/bootconfig.h> 56 #include <machine/pci_machdep.h> 57 58 #include <uvm/uvm_extern.h> 59 60 #include <arm/db_machdep.h> 61 #include <arm/undefined.h> 62 #include <arm/arm32/machdep.h> 63 64 #include <arm/marvell/mvsocreg.h> 65 #include <arm/marvell/mvsocvar.h> 66 #include <arm/marvell/orionreg.h> 67 #include <arm/marvell/kirkwoodreg.h> 68 #include <arm/marvell/mv78xx0reg.h> 69 #include <arm/marvell/armadaxpreg.h> 70 #include <arm/marvell/mvsocgppvar.h> 71 72 #include <evbarm/marvell/marvellreg.h> 73 #include <evbarm/marvell/marvellvar.h> 74 75 #include <ddb/db_extern.h> 76 #include <ddb/db_sym.h> 77 78 #include "ksyms.h" 79 80 81 /* Kernel text starts 2MB in from the bottom of the kernel address space. */ 82 #define KERNEL_TEXT_BASE (KERNEL_BASE + 0x00000000) 83 #define KERNEL_VM_BASE (KERNEL_BASE + 0x02000000) 84 85 /* 86 * The range 0xc2000000 - 0xdfffffff is available for kernel VM space 87 * Core-logic registers and I/O mappings occupy 0xfe000000 - 0xffffffff 88 */ 89 #define KERNEL_VM_SIZE 0x1e000000 90 91 BootConfig bootconfig; /* Boot config storage */ 92 static char bootargs[MAX_BOOT_STRING]; 93 char *boot_args = NULL; 94 95 extern int KERNEL_BASE_phys[]; 96 extern char _end[]; 97 98 /* 99 * Macros to translate between physical and virtual for a subset of the 100 * kernel address space. *Not* for general use. 101 */ 102 #define KERNEL_BASE_PHYS physical_start 103 #define KERN_VTOPHYS(va) \ 104 ((paddr_t)((vaddr_t)va - KERNEL_BASE + KERNEL_BASE_PHYS)) 105 #define KERN_PHYSTOV(pa) \ 106 ((vaddr_t)((paddr_t)pa - KERNEL_BASE_PHYS + KERNEL_BASE)) 107 108 109 #include "com.h" 110 #if NCOM > 0 111 #include <dev/ic/comreg.h> 112 #include <dev/ic/comvar.h> 113 #endif 114 115 #ifndef CONSPEED 116 #define CONSPEED B115200 /* It's a setting of the default of u-boot */ 117 #endif 118 #ifndef CONMODE 119 #define CONMODE ((TTYDEF_CFLAG & ~(CSIZE | CSTOPB | PARENB)) | CS8) /* 8N1 */ 120 121 int comcnspeed = CONSPEED; 122 int comcnmode = CONMODE; 123 #endif 124 125 #include "opt_kgdb.h" 126 #ifdef KGDB 127 #include <sys/kgdb.h> 128 #endif 129 130 static void marvell_device_register(device_t, void *); 131 #if NGTPCI > 0 || NMVPEX > 0 132 static void marvell_startend_by_tag(int, uint64_t *, uint64_t *); 133 #endif 134 135 static void 136 marvell_system_reset(void) 137 { 138 /* unmask soft reset */ 139 write_mlmbreg(MVSOC_MLMB_RSTOUTNMASKR, 140 MVSOC_MLMB_RSTOUTNMASKR_SOFTRSTOUTEN); 141 /* assert soft reset */ 142 write_mlmbreg(MVSOC_MLMB_SSRR, MVSOC_MLMB_SSRR_SYSTEMSOFTRST); 143 /* if we're still running, jump to the reset address */ 144 cpu_reset_address = 0; 145 cpu_reset_address_paddr = 0xffff0000; 146 cpu_reset(); 147 /*NOTREACHED*/ 148 } 149 150 static inline 151 pd_entry_t * 152 read_ttb(void) 153 { 154 long ttb; 155 156 __asm volatile("mrc p15, 0, %0, c2, c0, 0" : "=r" (ttb)); 157 158 return (pd_entry_t *)(ttb & ~((1<<14)-1)); 159 } 160 161 /* 162 * Static device mappings. These peripheral registers are mapped at 163 * fixed virtual addresses very early in initarm() so that we can use 164 * them while booting the kernel, and stay at the same address 165 * throughout whole kernel's life time. 166 * 167 * We use this table twice; once with bootstrap page table, and once 168 * with kernel's page table which we build up in initarm(). 169 * 170 * Since we map these registers into the bootstrap page table using 171 * pmap_devmap_bootstrap() which calls pmap_map_chunk(), we map 172 * registers segment-aligned and segment-rounded in order to avoid 173 * using the 2nd page tables. 174 */ 175 #define _A(a) ((a) & ~L1_S_OFFSET) 176 #define _S(s) (((s) + L1_S_SIZE - 1) & ~(L1_S_SIZE-1)) 177 178 static struct pmap_devmap marvell_devmap[] = { 179 { 180 MARVELL_INTERREGS_VBASE, 181 #if (defined(ORION) || defined(KIRKWOOD) || defined(MV78XX0)) && \ 182 defined(ARMADAXP) 183 _A(0x00000000), 184 #else 185 _A(MARVELL_INTERREGS_PBASE), 186 #endif 187 _S(MARVELL_INTERREGS_SIZE), 188 VM_PROT_READ|VM_PROT_WRITE, 189 PTE_NOCACHE, 190 }, 191 192 { 0, 0, 0, 0, 0 } 193 }; 194 195 extern uint32_t *u_boot_args[]; 196 197 /* 198 * u_int initarm(...) 199 * 200 * Initial entry point on startup. This gets called before main() is 201 * entered. 202 * It should be responsible for setting up everything that must be 203 * in place when main is called. 204 * This includes 205 * Taking a copy of the boot configuration structure. 206 * Initialising the physical console so characters can be printed. 207 * Setting up page tables for the kernel 208 * Relocating the kernel to the bottom of physical memory 209 */ 210 u_int 211 initarm(void *arg) 212 { 213 uint32_t target, attr, base, size; 214 int cs, memtag = 0, iotag = 0, window; 215 216 /* Use the mapped reset routine! */ 217 cpu_reset_address = marvell_system_reset; 218 219 mvsoc_bootstrap(MARVELL_INTERREGS_VBASE); 220 221 #if (defined(ORION) || defined(KIRKWOOD) || defined(MV78XX0)) && \ 222 defined(ARMADAXP) 223 int i; 224 225 for (i = 0; marvell_devmap[i].pd_size != 0; i++) 226 if (marvell_devmap[i].pd_va == MARVELL_INTERREGS_VBASE) { 227 marvell_devmap[i].pd_pa = _A(MARVELL_INTERREGS_PBASE); 228 break; 229 } 230 #endif 231 232 /* map some peripheral registers */ 233 pmap_devmap_bootstrap((vaddr_t)read_ttb(), marvell_devmap); 234 235 /* 236 * Heads up ... Setup the CPU / MMU / TLB functions 237 */ 238 if (set_cpufuncs()) 239 panic("cpu not recognized!"); 240 241 /* 242 * U-Boot doesn't use the virtual memory. 243 * 244 * Physical Address Range Description 245 * ----------------------- ---------------------------------- 246 * 0x00000000 - 0x0fffffff SDRAM Bank 0 (max 256MB) 247 * 0x10000000 - 0x1fffffff SDRAM Bank 1 (max 256MB) 248 * 0x20000000 - 0x2fffffff SDRAM Bank 2 (max 256MB) 249 * 0x30000000 - 0x3fffffff SDRAM Bank 3 (max 256MB) 250 * 0xf1000000 - 0xf10fffff SoC Internal Registers 251 */ 252 253 cpu_domains((DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL*2)) | DOMAIN_CLIENT); 254 255 consinit(); 256 257 /* Talk to the user */ 258 #ifndef EVBARM_BOARDTYPE 259 #define EVBARM_BOARDTYPE Marvell 260 #endif 261 #define BDSTR(s) _BDSTR(s) 262 #define _BDSTR(s) #s 263 printf("\nNetBSD/evbarm (" BDSTR(EVBARM_BOARDTYPE) ") booting ...\n"); 264 265 /* Get ready for splfoo() */ 266 switch (mvsoc_model()) { 267 #ifdef ORION 268 case MARVELL_ORION_1_88F1181: 269 case MARVELL_ORION_1_88F5082: 270 case MARVELL_ORION_1_88F5180N: 271 case MARVELL_ORION_1_88F5181: 272 case MARVELL_ORION_1_88F5182: 273 case MARVELL_ORION_1_88F6082: 274 case MARVELL_ORION_1_88F6183: 275 case MARVELL_ORION_1_88W8660: 276 case MARVELL_ORION_2_88F1281: 277 case MARVELL_ORION_2_88F5281: 278 orion_intr_bootstrap(); 279 280 memtag = ORION_TAG_PEX0_MEM; 281 iotag = ORION_TAG_PEX0_IO; 282 nwindow = ORION_MLMB_NWINDOW; 283 nremap = ORION_MLMB_NREMAP; 284 285 orion_getclks(MARVELL_INTERREGS_VBASE); 286 break; 287 #endif /* ORION */ 288 289 #ifdef KIRKWOOD 290 case MARVELL_KIRKWOOD_88F6180: 291 case MARVELL_KIRKWOOD_88F6192: 292 case MARVELL_KIRKWOOD_88F6281: 293 case MARVELL_KIRKWOOD_88F6282: 294 kirkwood_intr_bootstrap(); 295 296 memtag = KIRKWOOD_TAG_PEX_MEM; 297 iotag = KIRKWOOD_TAG_PEX_IO; 298 nwindow = KIRKWOOD_MLMB_NWINDOW; 299 nremap = KIRKWOOD_MLMB_NREMAP; 300 301 kirkwood_getclks(MARVELL_INTERREGS_VBASE); 302 break; 303 #endif /* KIRKWOOD */ 304 305 #ifdef MV78XX0 306 case MARVELL_MV78XX0_MV78100: 307 case MARVELL_MV78XX0_MV78200: 308 mv78xx0_intr_bootstrap(); 309 310 memtag = MV78XX0_TAG_PEX0_MEM; 311 iotag = MV78XX0_TAG_PEX0_IO; 312 nwindow = MV78XX0_MLMB_NWINDOW; 313 nremap = MV78XX0_MLMB_NREMAP; 314 315 mv78xx0_getclks(MARVELL_INTERREGS_VBASE); 316 break; 317 #endif /* MV78XX0 */ 318 319 #ifdef ARMADAXP 320 case MARVELL_ARMADAXP_MV78130: 321 case MARVELL_ARMADAXP_MV78160: 322 case MARVELL_ARMADAXP_MV78230: 323 case MARVELL_ARMADAXP_MV78260: 324 case MARVELL_ARMADAXP_MV78460: 325 armadaxp_intr_bootstrap(MARVELL_INTERREGS_PBASE); 326 327 memtag = ARMADAXP_TAG_PEX00_MEM; 328 iotag = ARMADAXP_TAG_PEX00_IO; 329 nwindow = ARMADAXP_MLMB_NWINDOW; 330 nremap = ARMADAXP_MLMB_NREMAP; 331 332 armadaxp_getclks(); 333 334 #ifdef L2CACHE_ENABLE 335 /* Initialize L2 Cache */ 336 { 337 extern int armadaxp_l2_init(bus_addr_t); 338 339 (void)armadaxp_l2_init(MARVELL_INTERREGS_PBASE); 340 } 341 #endif 342 343 #ifdef AURORA_IO_CACHE_COHERENCY 344 /* Initialize cache coherency */ 345 armadaxp_io_coherency_init(); 346 #endif 347 break; 348 #endif /* ARMADAXP */ 349 350 default: 351 /* We can't output console here yet... */ 352 panic("unknown model...\n"); 353 354 /* NOTREACHED */ 355 } 356 357 /* Reset PCI-Express space to window register. */ 358 window = mvsoc_target(memtag, &target, &attr, NULL, NULL); 359 write_mlmbreg(MVSOC_MLMB_WCR(window), 360 MVSOC_MLMB_WCR_WINEN | 361 MVSOC_MLMB_WCR_TARGET(target) | 362 MVSOC_MLMB_WCR_ATTR(attr) | 363 MVSOC_MLMB_WCR_SIZE(MARVELL_PEXMEM_SIZE)); 364 write_mlmbreg(MVSOC_MLMB_WBR(window), 365 MARVELL_PEXMEM_PBASE & MVSOC_MLMB_WBR_BASE_MASK); 366 #ifdef PCI_NETBSD_CONFIGURE 367 if (window < nremap) { 368 write_mlmbreg(MVSOC_MLMB_WRLR(window), 369 MARVELL_PEXMEM_PBASE & MVSOC_MLMB_WRLR_REMAP_MASK); 370 write_mlmbreg(MVSOC_MLMB_WRHR(window), 0); 371 } 372 #endif 373 window = mvsoc_target(iotag, &target, &attr, NULL, NULL); 374 write_mlmbreg(MVSOC_MLMB_WCR(window), 375 MVSOC_MLMB_WCR_WINEN | 376 MVSOC_MLMB_WCR_TARGET(target) | 377 MVSOC_MLMB_WCR_ATTR(attr) | 378 MVSOC_MLMB_WCR_SIZE(MARVELL_PEXIO_SIZE)); 379 write_mlmbreg(MVSOC_MLMB_WBR(window), 380 MARVELL_PEXIO_PBASE & MVSOC_MLMB_WBR_BASE_MASK); 381 #ifdef PCI_NETBSD_CONFIGURE 382 if (window < nremap) { 383 write_mlmbreg(MVSOC_MLMB_WRLR(window), 384 MARVELL_PEXIO_PBASE & MVSOC_MLMB_WRLR_REMAP_MASK); 385 write_mlmbreg(MVSOC_MLMB_WRHR(window), 0); 386 } 387 #endif 388 389 /* copy command line U-Boot gave us, if args is valid. */ 390 if (u_boot_args[3] != 0) /* XXXXX: need more check?? */ 391 strncpy(bootargs, (char *)u_boot_args[3], sizeof(bootargs)); 392 393 #ifdef VERBOSE_INIT_ARM 394 printf("initarm: Configuring system ...\n"); 395 #endif 396 397 bootconfig.dramblocks = 0; 398 paddr_t segment_end; 399 segment_end = physmem = 0; 400 for (cs = MARVELL_TAG_SDRAM_CS0; cs <= MARVELL_TAG_SDRAM_CS3; cs++) { 401 mvsoc_target(cs, &target, &attr, &base, &size); 402 if (size == 0) 403 continue; 404 405 bootconfig.dram[bootconfig.dramblocks].address = base; 406 bootconfig.dram[bootconfig.dramblocks].pages = size / PAGE_SIZE; 407 408 if (base != segment_end) 409 panic("memory hole not support"); 410 411 segment_end += size; 412 physmem += size / PAGE_SIZE; 413 414 bootconfig.dramblocks++; 415 } 416 417 arm32_bootmem_init(0, segment_end, (uintptr_t) KERNEL_BASE_phys); 418 arm32_kernel_vm_init(KERNEL_VM_BASE, ARM_VECTORS_HIGH, 0, 419 marvell_devmap, false); 420 421 /* we've a specific device_register routine */ 422 evbarm_device_register = marvell_device_register; 423 424 /* parse bootargs from U-Boot */ 425 boot_args = bootargs; 426 parse_mi_bootargs(boot_args); 427 428 return initarm_common(KERNEL_VM_BASE, KERNEL_VM_SIZE, NULL, 0); 429 } 430 431 void 432 consinit(void) 433 { 434 static int consinit_called = 0; 435 436 if (consinit_called != 0) 437 return; 438 439 consinit_called = 1; 440 441 #if NCOM > 0 442 { 443 extern int mvuart_cnattach(bus_space_tag_t, bus_addr_t, int, 444 uint32_t, int); 445 446 if (mvuart_cnattach(&mvsoc_bs_tag, 447 MARVELL_INTERREGS_PBASE + MVSOC_COM0_BASE, 448 comcnspeed, mvTclk, comcnmode)) 449 panic("can't init serial console"); 450 } 451 #else 452 panic("serial console not configured"); 453 #endif 454 } 455 456 457 static void 458 marvell_device_register(device_t dev, void *aux) 459 { 460 prop_dictionary_t dict = device_properties(dev); 461 462 #if NCOM > 0 463 if (device_is_a(dev, "com") && 464 device_is_a(device_parent(dev), "mvsoc")) 465 prop_dictionary_set_uint32(dict, "frequency", mvTclk); 466 #endif 467 468 if (device_is_a(dev, "gtidmac")) 469 prop_dictionary_set_uint32(dict, 470 "dmb_speed", mvTclk * sizeof(uint32_t)); /* XXXXXX */ 471 472 #if NGTPCI > 0 && defined(ORION) 473 if (device_is_a(dev, "gtpci")) { 474 extern struct bus_space 475 orion_pci_io_bs_tag, orion_pci_mem_bs_tag; 476 extern struct arm32_pci_chipset arm32_gtpci_chipset; 477 478 prop_data_t io_bs_tag, mem_bs_tag, pc; 479 prop_array_t int2gpp; 480 prop_number_t gpp; 481 uint64_t start, end; 482 int i, j; 483 static struct { 484 const char *boardtype; 485 int pin[PCI_INTERRUPT_PIN_MAX]; 486 } hints[] = { 487 { "kuronas_x4", 488 { 11, PCI_INTERRUPT_PIN_NONE } }, 489 490 { NULL, 491 { PCI_INTERRUPT_PIN_NONE } }, 492 }; 493 494 arm32_gtpci_chipset.pc_conf_v = device_private(dev); 495 arm32_gtpci_chipset.pc_intr_v = device_private(dev); 496 497 io_bs_tag = prop_data_create_data_nocopy( 498 &orion_pci_io_bs_tag, sizeof(struct bus_space)); 499 KASSERT(io_bs_tag != NULL); 500 prop_dictionary_set(dict, "io-bus-tag", io_bs_tag); 501 prop_object_release(io_bs_tag); 502 mem_bs_tag = prop_data_create_data_nocopy( 503 &orion_pci_mem_bs_tag, sizeof(struct bus_space)); 504 KASSERT(mem_bs_tag != NULL); 505 prop_dictionary_set(dict, "mem-bus-tag", mem_bs_tag); 506 prop_object_release(mem_bs_tag); 507 508 pc = prop_data_create_data_nocopy(&arm32_gtpci_chipset, 509 sizeof(struct arm32_pci_chipset)); 510 KASSERT(pc != NULL); 511 prop_dictionary_set(dict, "pci-chipset", pc); 512 prop_object_release(pc); 513 514 marvell_startend_by_tag(ORION_TAG_PCI_IO, &start, &end); 515 prop_dictionary_set_uint64(dict, "iostart", start); 516 prop_dictionary_set_uint64(dict, "ioend", end); 517 marvell_startend_by_tag(ORION_TAG_PCI_MEM, &start, &end); 518 prop_dictionary_set_uint64(dict, "memstart", start); 519 prop_dictionary_set_uint64(dict, "memend", end); 520 prop_dictionary_set_uint32(dict, 521 "cache-line-size", arm_dcache_align); 522 523 /* Setup the hint for interrupt-pin. */ 524 #define BDSTR(s) _BDSTR(s) 525 #define _BDSTR(s) #s 526 #define THIS_BOARD(str) (strcmp(str, BDSTR(EVBARM_BOARDTYPE)) == 0) 527 for (i = 0; hints[i].boardtype != NULL; i++) 528 if (THIS_BOARD(hints[i].boardtype)) 529 break; 530 if (hints[i].boardtype == NULL) 531 return; 532 533 int2gpp = 534 prop_array_create_with_capacity(PCI_INTERRUPT_PIN_MAX + 1); 535 536 /* first set dummy */ 537 gpp = prop_number_create_integer(0); 538 prop_array_add(int2gpp, gpp); 539 prop_object_release(gpp); 540 541 for (j = 0; hints[i].pin[j] != PCI_INTERRUPT_PIN_NONE; j++) { 542 gpp = prop_number_create_integer(hints[i].pin[j]); 543 prop_array_add(int2gpp, gpp); 544 prop_object_release(gpp); 545 } 546 prop_dictionary_set(dict, "int2gpp", int2gpp); 547 } 548 #endif /* NGTPCI > 0 && defined(ORION) */ 549 550 #if NMVPEX > 0 551 if (device_is_a(dev, "mvpex")) { 552 #ifdef ORION 553 extern struct bus_space 554 orion_pex0_io_bs_tag, orion_pex0_mem_bs_tag, 555 orion_pex1_io_bs_tag, orion_pex1_mem_bs_tag; 556 #endif 557 #ifdef KIRKWOOD 558 extern struct bus_space 559 kirkwood_pex_io_bs_tag, kirkwood_pex_mem_bs_tag, 560 kirkwood_pex1_io_bs_tag, kirkwood_pex1_mem_bs_tag; 561 #endif 562 #ifdef ARMADAXP 563 extern struct bus_space 564 armadaxp_pex00_io_bs_tag, armadaxp_pex00_mem_bs_tag, 565 armadaxp_pex01_io_bs_tag, armadaxp_pex01_mem_bs_tag, 566 armadaxp_pex02_io_bs_tag, armadaxp_pex02_mem_bs_tag, 567 armadaxp_pex03_io_bs_tag, armadaxp_pex03_mem_bs_tag, 568 armadaxp_pex2_io_bs_tag, armadaxp_pex2_mem_bs_tag, 569 armadaxp_pex3_io_bs_tag, armadaxp_pex3_mem_bs_tag; 570 int i; 571 #endif 572 extern struct arm32_pci_chipset 573 arm32_mvpex0_chipset, arm32_mvpex1_chipset; 574 575 struct marvell_attach_args *mva = aux; 576 struct bus_space *mvpex_io_bs_tag, *mvpex_mem_bs_tag; 577 struct arm32_pci_chipset *arm32_mvpex_chipset; 578 prop_data_t io_bs_tag, mem_bs_tag, pc; 579 uint64_t start, end; 580 int iotag, memtag; 581 582 switch (mvsoc_model()) { 583 #ifdef ORION 584 case MARVELL_ORION_1_88F5180N: 585 case MARVELL_ORION_1_88F5181: 586 case MARVELL_ORION_1_88F5182: 587 case MARVELL_ORION_1_88W8660: 588 case MARVELL_ORION_2_88F5281: 589 if (mva->mva_offset == MVSOC_PEX_BASE) { 590 mvpex_io_bs_tag = &orion_pex0_io_bs_tag; 591 mvpex_mem_bs_tag = &orion_pex0_mem_bs_tag; 592 arm32_mvpex_chipset = &arm32_mvpex0_chipset; 593 iotag = ORION_TAG_PEX0_IO; 594 memtag = ORION_TAG_PEX0_MEM; 595 } else { 596 mvpex_io_bs_tag = &orion_pex1_io_bs_tag; 597 mvpex_mem_bs_tag = &orion_pex1_mem_bs_tag; 598 arm32_mvpex_chipset = &arm32_mvpex1_chipset; 599 iotag = ORION_TAG_PEX1_IO; 600 memtag = ORION_TAG_PEX1_MEM; 601 } 602 break; 603 #endif 604 605 #ifdef KIRKWOOD 606 case MARVELL_KIRKWOOD_88F6282: 607 if (mva->mva_offset != MVSOC_PEX_BASE) { 608 mvpex_io_bs_tag = &kirkwood_pex1_io_bs_tag; 609 mvpex_mem_bs_tag = &kirkwood_pex1_mem_bs_tag; 610 arm32_mvpex_chipset = &arm32_mvpex1_chipset; 611 iotag = KIRKWOOD_TAG_PEX1_IO; 612 memtag = KIRKWOOD_TAG_PEX1_MEM; 613 break; 614 } 615 616 /* FALLTHROUGH */ 617 618 case MARVELL_KIRKWOOD_88F6180: 619 case MARVELL_KIRKWOOD_88F6192: 620 case MARVELL_KIRKWOOD_88F6281: 621 mvpex_io_bs_tag = &kirkwood_pex_io_bs_tag; 622 mvpex_mem_bs_tag = &kirkwood_pex_mem_bs_tag; 623 arm32_mvpex_chipset = &arm32_mvpex0_chipset; 624 iotag = KIRKWOOD_TAG_PEX_IO; 625 memtag = KIRKWOOD_TAG_PEX_MEM; 626 break; 627 #endif 628 629 #ifdef ARMADAXP 630 case MARVELL_ARMADAXP_MV78130: 631 case MARVELL_ARMADAXP_MV78160: 632 case MARVELL_ARMADAXP_MV78230: 633 case MARVELL_ARMADAXP_MV78260: 634 case MARVELL_ARMADAXP_MV78460: 635 { 636 extern struct arm32_pci_chipset 637 arm32_mvpex2_chipset, arm32_mvpex3_chipset, 638 arm32_mvpex4_chipset, arm32_mvpex5_chipset; 639 const struct { 640 bus_size_t offset; 641 struct bus_space *io_bs_tag; 642 struct bus_space *mem_bs_tag; 643 struct arm32_pci_chipset *chipset; 644 int iotag; 645 int memtag; 646 } mvpex_tags[] = { 647 { MVSOC_PEX_BASE, 648 &armadaxp_pex00_io_bs_tag, 649 &armadaxp_pex00_mem_bs_tag, 650 &arm32_mvpex0_chipset, 651 ARMADAXP_TAG_PEX00_IO, 652 ARMADAXP_TAG_PEX00_MEM }, 653 654 { ARMADAXP_PEX01_BASE, 655 &armadaxp_pex01_io_bs_tag, 656 &armadaxp_pex01_mem_bs_tag, 657 &arm32_mvpex1_chipset, 658 ARMADAXP_TAG_PEX01_IO, 659 ARMADAXP_TAG_PEX01_MEM }, 660 661 { ARMADAXP_PEX02_BASE, 662 &armadaxp_pex02_io_bs_tag, 663 &armadaxp_pex02_mem_bs_tag, 664 &arm32_mvpex2_chipset, 665 ARMADAXP_TAG_PEX02_IO, 666 ARMADAXP_TAG_PEX02_MEM }, 667 668 { ARMADAXP_PEX03_BASE, 669 &armadaxp_pex03_io_bs_tag, 670 &armadaxp_pex03_mem_bs_tag, 671 &arm32_mvpex3_chipset, 672 ARMADAXP_TAG_PEX03_IO, 673 ARMADAXP_TAG_PEX03_MEM }, 674 675 { ARMADAXP_PEX2_BASE, 676 &armadaxp_pex2_io_bs_tag, 677 &armadaxp_pex2_mem_bs_tag, 678 &arm32_mvpex4_chipset, 679 ARMADAXP_TAG_PEX2_IO, 680 ARMADAXP_TAG_PEX2_MEM }, 681 682 { ARMADAXP_PEX3_BASE, 683 &armadaxp_pex3_io_bs_tag, 684 &armadaxp_pex3_mem_bs_tag, 685 &arm32_mvpex5_chipset, 686 ARMADAXP_TAG_PEX3_IO, 687 ARMADAXP_TAG_PEX3_MEM }, 688 689 { 0, 0, 0, 0, 0 }, 690 }; 691 692 for (i = 0; mvpex_tags[i].offset != 0; i++) { 693 if (mva->mva_offset != mvpex_tags[i].offset) 694 continue; 695 break; 696 } 697 if (mvpex_tags[i].offset == 0) 698 return; 699 mvpex_io_bs_tag = mvpex_tags[i].io_bs_tag; 700 mvpex_mem_bs_tag = mvpex_tags[i].mem_bs_tag; 701 arm32_mvpex_chipset = mvpex_tags[i].chipset; 702 iotag = mvpex_tags[i].iotag; 703 memtag = mvpex_tags[i].memtag; 704 break; 705 } 706 #endif 707 708 default: 709 return; 710 } 711 712 arm32_mvpex_chipset->pc_conf_v = device_private(dev); 713 arm32_mvpex_chipset->pc_intr_v = device_private(dev); 714 715 io_bs_tag = prop_data_create_data_nocopy( 716 mvpex_io_bs_tag, sizeof(struct bus_space)); 717 KASSERT(io_bs_tag != NULL); 718 prop_dictionary_set(dict, "io-bus-tag", io_bs_tag); 719 prop_object_release(io_bs_tag); 720 mem_bs_tag = prop_data_create_data_nocopy( 721 mvpex_mem_bs_tag, sizeof(struct bus_space)); 722 KASSERT(mem_bs_tag != NULL); 723 prop_dictionary_set(dict, "mem-bus-tag", mem_bs_tag); 724 prop_object_release(mem_bs_tag); 725 726 pc = prop_data_create_data_nocopy(arm32_mvpex_chipset, 727 sizeof(struct arm32_pci_chipset)); 728 KASSERT(pc != NULL); 729 prop_dictionary_set(dict, "pci-chipset", pc); 730 prop_object_release(pc); 731 732 marvell_startend_by_tag(iotag, &start, &end); 733 prop_dictionary_set_uint64(dict, "iostart", start); 734 prop_dictionary_set_uint64(dict, "ioend", end); 735 marvell_startend_by_tag(memtag, &start, &end); 736 prop_dictionary_set_uint64(dict, "memstart", start); 737 prop_dictionary_set_uint64(dict, "memend", end); 738 prop_dictionary_set_uint32(dict, 739 "cache-line-size", arm_dcache_align); 740 } 741 #endif 742 } 743 744 #if NGTPCI > 0 || NMVPEX > 0 745 static void 746 marvell_startend_by_tag(int tag, uint64_t *start, uint64_t *end) 747 { 748 uint32_t base, size; 749 int win; 750 751 win = mvsoc_target(tag, NULL, NULL, &base, &size); 752 if (size != 0) { 753 if (win < nremap) 754 *start = read_mlmbreg(MVSOC_MLMB_WRLR(win)) | 755 ((read_mlmbreg(MVSOC_MLMB_WRHR(win)) << 16) << 16); 756 else 757 *start = base; 758 *end = *start + size - 1; 759 } 760 } 761 #endif 762
Indexes created Wed Oct 01 07:09:59 GMT 2025