marvell_machdep.c revision 1.24
1 /* $NetBSD: marvell_machdep.c,v 1.24 2013/11/20 12:59:21 kiyohara Exp $ */ 2 /* 3 * Copyright (c) 2007, 2008, 2010 KIYOHARA Takashi 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 17 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 18 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 19 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 20 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 21 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 23 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 24 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 */ 27 #include <sys/cdefs.h> 28 __KERNEL_RCSID(0, "$NetBSD: marvell_machdep.c,v 1.24 2013/11/20 12:59:21 kiyohara Exp $"); 29 30 #include "opt_evbarm_boardtype.h" 31 #include "opt_ddb.h" 32 #include "opt_pci.h" 33 #include "opt_mvsoc.h" 34 #include "com.h" 35 #include "gtpci.h" 36 #include "mvpex.h" 37 38 #include <sys/param.h> 39 #include <sys/kernel.h> 40 #include <sys/reboot.h> 41 #include <sys/systm.h> 42 #include <sys/termios.h> 43 44 #include <prop/proplib.h> 45 46 #include <dev/cons.h> 47 #include <dev/md.h> 48 49 #include <dev/marvell/marvellreg.h> 50 #include <dev/marvell/marvellvar.h> 51 #include <dev/pci/pcireg.h> 52 #include <dev/pci/pcivar.h> 53 54 #include <machine/autoconf.h> 55 #include <machine/bootconfig.h> 56 #include <machine/pci_machdep.h> 57 58 #include <uvm/uvm_extern.h> 59 60 #include <arm/db_machdep.h> 61 #include <arm/undefined.h> 62 #include <arm/arm32/machdep.h> 63 64 #include <arm/marvell/mvsocreg.h> 65 #include <arm/marvell/mvsocvar.h> 66 #include <arm/marvell/orionreg.h> 67 #include <arm/marvell/kirkwoodreg.h> 68 #include <arm/marvell/mv78xx0reg.h> 69 #include <arm/marvell/armadaxpreg.h> 70 #include <arm/marvell/mvsocgppvar.h> 71 72 #include <evbarm/marvell/marvellreg.h> 73 #include <evbarm/marvell/marvellvar.h> 74 75 #include <ddb/db_extern.h> 76 #include <ddb/db_sym.h> 77 78 #include "ksyms.h" 79 80 81 /* Kernel text starts 2MB in from the bottom of the kernel address space. */ 82 #define KERNEL_TEXT_BASE (KERNEL_BASE + 0x00000000) 83 #define KERNEL_VM_BASE (KERNEL_BASE + 0x02000000) 84 85 /* 86 * The range 0xc2000000 - 0xdfffffff is available for kernel VM space 87 * Core-logic registers and I/O mappings occupy 0xfe000000 - 0xffffffff 88 */ 89 #define KERNEL_VM_SIZE 0x1e000000 90 91 BootConfig bootconfig; /* Boot config storage */ 92 static char bootargs[MAX_BOOT_STRING]; 93 char *boot_args = NULL; 94 95 extern int KERNEL_BASE_phys[]; 96 extern char _end[]; 97 98 /* 99 * Macros to translate between physical and virtual for a subset of the 100 * kernel address space. *Not* for general use. 101 */ 102 #define KERNEL_BASE_PHYS physical_start 103 #define KERN_VTOPHYS(va) \ 104 ((paddr_t)((vaddr_t)va - KERNEL_BASE + KERNEL_BASE_PHYS)) 105 #define KERN_PHYSTOV(pa) \ 106 ((vaddr_t)((paddr_t)pa - KERNEL_BASE_PHYS + KERNEL_BASE)) 107 108 109 #include "com.h" 110 #if NCOM > 0 111 #include <dev/ic/comreg.h> 112 #include <dev/ic/comvar.h> 113 #endif 114 115 #ifndef CONSPEED 116 #define CONSPEED B115200 /* It's a setting of the default of u-boot */ 117 #endif 118 #ifndef CONMODE 119 #define CONMODE ((TTYDEF_CFLAG & ~(CSIZE | CSTOPB | PARENB)) | CS8) /* 8N1 */ 120 121 int comcnspeed = CONSPEED; 122 int comcnmode = CONMODE; 123 #endif 124 125 #include "opt_kgdb.h" 126 #ifdef KGDB 127 #include <sys/kgdb.h> 128 #endif 129 130 static void marvell_device_register(device_t, void *); 131 #if NGTPCI > 0 || NMVPEX > 0 132 static void marvell_startend_by_tag(int, uint64_t *, uint64_t *); 133 #endif 134 135 #if defined(ORION) || defined(KIRKWOOD) || defined(MV78XX0) 136 static void 137 marvell_system_reset_old(void) 138 { 139 /* unmask soft reset */ 140 write_mlmbreg(MVSOC_MLMB_RSTOUTNMASKR, 141 MVSOC_MLMB_RSTOUTNMASKR_SOFTRSTOUTEN); 142 /* assert soft reset */ 143 write_mlmbreg(MVSOC_MLMB_SSRR, MVSOC_MLMB_SSRR_SYSTEMSOFTRST); 144 145 /* if we're still running, jump to the reset address */ 146 cpu_reset_address = 0; 147 cpu_reset_address_paddr = 0xffff0000; 148 cpu_reset(); 149 /*NOTREACHED*/ 150 } 151 #endif 152 153 #if defined(ARMADAXP) 154 static void 155 marvell_system_reset(void) 156 { 157 158 /* Unmask soft reset */ 159 write_miscreg(MVSOC_MISC_RSTOUTNMASKR, 160 MVSOC_MISC_RSTOUTNMASKR_GLOBALSOFTRSTOUTEN); 161 /* Assert soft reset */ 162 write_miscreg(MVSOC_MISC_SSRR, MVSOC_MISC_SSRR_GLOBALSOFTRST); 163 164 while (1); 165 166 /*NOTREACHED*/ 167 } 168 #endif 169 170 171 static inline 172 pd_entry_t * 173 read_ttb(void) 174 { 175 long ttb; 176 177 __asm volatile("mrc p15, 0, %0, c2, c0, 0" : "=r" (ttb)); 178 179 return (pd_entry_t *)(ttb & ~((1<<14)-1)); 180 } 181 182 /* 183 * Static device mappings. These peripheral registers are mapped at 184 * fixed virtual addresses very early in initarm() so that we can use 185 * them while booting the kernel, and stay at the same address 186 * throughout whole kernel's life time. 187 * 188 * We use this table twice; once with bootstrap page table, and once 189 * with kernel's page table which we build up in initarm(). 190 * 191 * Since we map these registers into the bootstrap page table using 192 * pmap_devmap_bootstrap() which calls pmap_map_chunk(), we map 193 * registers segment-aligned and segment-rounded in order to avoid 194 * using the 2nd page tables. 195 */ 196 #define _A(a) ((a) & ~L1_S_OFFSET) 197 #define _S(s) (((s) + L1_S_SIZE - 1) & ~(L1_S_SIZE-1)) 198 199 static struct pmap_devmap marvell_devmap[] = { 200 { 201 MARVELL_INTERREGS_VBASE, 202 #if (defined(ORION) || defined(KIRKWOOD) || defined(MV78XX0)) && \ 203 defined(ARMADAXP) 204 _A(0x00000000), 205 #else 206 _A(MARVELL_INTERREGS_PBASE), 207 #endif 208 _S(MARVELL_INTERREGS_SIZE), 209 VM_PROT_READ|VM_PROT_WRITE, 210 PTE_NOCACHE, 211 }, 212 213 { 0, 0, 0, 0, 0 } 214 }; 215 216 extern uint32_t *u_boot_args[]; 217 218 /* 219 * u_int initarm(...) 220 * 221 * Initial entry point on startup. This gets called before main() is 222 * entered. 223 * It should be responsible for setting up everything that must be 224 * in place when main is called. 225 * This includes 226 * Taking a copy of the boot configuration structure. 227 * Initialising the physical console so characters can be printed. 228 * Setting up page tables for the kernel 229 * Relocating the kernel to the bottom of physical memory 230 */ 231 u_int 232 initarm(void *arg) 233 { 234 uint32_t target, attr, base, size; 235 int cs, memtag = 0, iotag = 0, window; 236 237 mvsoc_bootstrap(MARVELL_INTERREGS_VBASE); 238 239 /* 240 * Heads up ... Setup the CPU / MMU / TLB functions 241 */ 242 if (set_cpufuncs()) 243 panic("cpu not recognized!"); 244 245 #if (defined(ORION) || defined(KIRKWOOD) || defined(MV78XX0)) && \ 246 defined(ARMADAXP) 247 int i; 248 249 for (i = 0; marvell_devmap[i].pd_size != 0; i++) 250 if (marvell_devmap[i].pd_va == MARVELL_INTERREGS_VBASE) { 251 marvell_devmap[i].pd_pa = _A(MARVELL_INTERREGS_PBASE); 252 break; 253 } 254 #endif 255 256 /* map some peripheral registers */ 257 pmap_devmap_bootstrap((vaddr_t)read_ttb(), marvell_devmap); 258 259 /* 260 * U-Boot doesn't use the virtual memory. 261 * 262 * Physical Address Range Description 263 * ----------------------- ---------------------------------- 264 * 0x00000000 - 0x0fffffff SDRAM Bank 0 (max 256MB) 265 * 0x10000000 - 0x1fffffff SDRAM Bank 1 (max 256MB) 266 * 0x20000000 - 0x2fffffff SDRAM Bank 2 (max 256MB) 267 * 0x30000000 - 0x3fffffff SDRAM Bank 3 (max 256MB) 268 * 0xf1000000 - 0xf10fffff SoC Internal Registers 269 */ 270 271 cpu_domains((DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL*2)) | DOMAIN_CLIENT); 272 273 /* Get ready for splfoo() */ 274 switch (mvsoc_model()) { 275 #ifdef ORION 276 case MARVELL_ORION_1_88F1181: 277 case MARVELL_ORION_1_88F5082: 278 case MARVELL_ORION_1_88F5180N: 279 case MARVELL_ORION_1_88F5181: 280 case MARVELL_ORION_1_88F5182: 281 case MARVELL_ORION_1_88F6082: 282 case MARVELL_ORION_1_88F6183: 283 case MARVELL_ORION_1_88W8660: 284 case MARVELL_ORION_2_88F1281: 285 case MARVELL_ORION_2_88F5281: 286 cpu_reset_address = marvell_system_reset_old; 287 288 orion_intr_bootstrap(); 289 290 memtag = ORION_TAG_PEX0_MEM; 291 iotag = ORION_TAG_PEX0_IO; 292 nwindow = ORION_MLMB_NWINDOW; 293 nremap = ORION_MLMB_NREMAP; 294 295 orion_getclks(MARVELL_INTERREGS_VBASE); 296 break; 297 #endif /* ORION */ 298 299 #ifdef KIRKWOOD 300 case MARVELL_KIRKWOOD_88F6180: 301 case MARVELL_KIRKWOOD_88F6192: 302 case MARVELL_KIRKWOOD_88F6281: 303 case MARVELL_KIRKWOOD_88F6282: 304 cpu_reset_address = marvell_system_reset_old; 305 306 kirkwood_intr_bootstrap(); 307 308 memtag = KIRKWOOD_TAG_PEX_MEM; 309 iotag = KIRKWOOD_TAG_PEX_IO; 310 nwindow = KIRKWOOD_MLMB_NWINDOW; 311 nremap = KIRKWOOD_MLMB_NREMAP; 312 313 kirkwood_getclks(MARVELL_INTERREGS_VBASE); 314 break; 315 #endif /* KIRKWOOD */ 316 317 #ifdef MV78XX0 318 case MARVELL_MV78XX0_MV78100: 319 case MARVELL_MV78XX0_MV78200: 320 cpu_reset_address = marvell_system_reset_old; 321 322 mv78xx0_intr_bootstrap(); 323 324 memtag = MV78XX0_TAG_PEX0_MEM; 325 iotag = MV78XX0_TAG_PEX0_IO; 326 nwindow = MV78XX0_MLMB_NWINDOW; 327 nremap = MV78XX0_MLMB_NREMAP; 328 329 mv78xx0_getclks(MARVELL_INTERREGS_VBASE); 330 break; 331 #endif /* MV78XX0 */ 332 333 #ifdef ARMADAXP 334 case MARVELL_ARMADAXP_MV78130: 335 case MARVELL_ARMADAXP_MV78160: 336 case MARVELL_ARMADAXP_MV78230: 337 case MARVELL_ARMADAXP_MV78260: 338 case MARVELL_ARMADAXP_MV78460: 339 cpu_reset_address = marvell_system_reset; 340 341 armadaxp_intr_bootstrap(MARVELL_INTERREGS_PBASE); 342 343 memtag = ARMADAXP_TAG_PEX00_MEM; 344 iotag = ARMADAXP_TAG_PEX00_IO; 345 nwindow = ARMADAXP_MLMB_NWINDOW; 346 nremap = ARMADAXP_MLMB_NREMAP; 347 348 armadaxp_getclks(); 349 350 #ifdef L2CACHE_ENABLE 351 /* Initialize L2 Cache */ 352 { 353 extern int armadaxp_l2_init(bus_addr_t); 354 355 (void)armadaxp_l2_init(MARVELL_INTERREGS_PBASE); 356 } 357 #endif 358 359 #ifdef AURORA_IO_CACHE_COHERENCY 360 /* Initialize cache coherency */ 361 armadaxp_io_coherency_init(); 362 #endif 363 break; 364 #endif /* ARMADAXP */ 365 366 default: 367 /* We can't output console here yet... */ 368 panic("unknown model...\n"); 369 370 /* NOTREACHED */ 371 } 372 373 consinit(); 374 375 /* Talk to the user */ 376 #ifndef EVBARM_BOARDTYPE 377 #define EVBARM_BOARDTYPE Marvell 378 #endif 379 #define BDSTR(s) _BDSTR(s) 380 #define _BDSTR(s) #s 381 printf("\nNetBSD/evbarm (" BDSTR(EVBARM_BOARDTYPE) ") booting ...\n"); 382 383 /* Reset PCI-Express space to window register. */ 384 window = mvsoc_target(memtag, &target, &attr, NULL, NULL); 385 write_mlmbreg(MVSOC_MLMB_WCR(window), 386 MVSOC_MLMB_WCR_WINEN | 387 MVSOC_MLMB_WCR_TARGET(target) | 388 MVSOC_MLMB_WCR_ATTR(attr) | 389 MVSOC_MLMB_WCR_SIZE(MARVELL_PEXMEM_SIZE)); 390 write_mlmbreg(MVSOC_MLMB_WBR(window), 391 MARVELL_PEXMEM_PBASE & MVSOC_MLMB_WBR_BASE_MASK); 392 #ifdef PCI_NETBSD_CONFIGURE 393 if (window < nremap) { 394 write_mlmbreg(MVSOC_MLMB_WRLR(window), 395 MARVELL_PEXMEM_PBASE & MVSOC_MLMB_WRLR_REMAP_MASK); 396 write_mlmbreg(MVSOC_MLMB_WRHR(window), 0); 397 } 398 #endif 399 window = mvsoc_target(iotag, &target, &attr, NULL, NULL); 400 write_mlmbreg(MVSOC_MLMB_WCR(window), 401 MVSOC_MLMB_WCR_WINEN | 402 MVSOC_MLMB_WCR_TARGET(target) | 403 MVSOC_MLMB_WCR_ATTR(attr) | 404 MVSOC_MLMB_WCR_SIZE(MARVELL_PEXIO_SIZE)); 405 write_mlmbreg(MVSOC_MLMB_WBR(window), 406 MARVELL_PEXIO_PBASE & MVSOC_MLMB_WBR_BASE_MASK); 407 #ifdef PCI_NETBSD_CONFIGURE 408 if (window < nremap) { 409 write_mlmbreg(MVSOC_MLMB_WRLR(window), 410 MARVELL_PEXIO_PBASE & MVSOC_MLMB_WRLR_REMAP_MASK); 411 write_mlmbreg(MVSOC_MLMB_WRHR(window), 0); 412 } 413 #endif 414 415 /* copy command line U-Boot gave us, if args is valid. */ 416 if (u_boot_args[3] != 0) /* XXXXX: need more check?? */ 417 strncpy(bootargs, (char *)u_boot_args[3], sizeof(bootargs)); 418 419 #ifdef VERBOSE_INIT_ARM 420 printf("initarm: Configuring system ...\n"); 421 #endif 422 423 bootconfig.dramblocks = 0; 424 paddr_t segment_end; 425 segment_end = physmem = 0; 426 for (cs = MARVELL_TAG_SDRAM_CS0; cs <= MARVELL_TAG_SDRAM_CS3; cs++) { 427 mvsoc_target(cs, &target, &attr, &base, &size); 428 if (size == 0) 429 continue; 430 431 bootconfig.dram[bootconfig.dramblocks].address = base; 432 bootconfig.dram[bootconfig.dramblocks].pages = size / PAGE_SIZE; 433 434 if (base != segment_end) 435 panic("memory hole not support"); 436 437 segment_end += size; 438 physmem += size / PAGE_SIZE; 439 440 bootconfig.dramblocks++; 441 } 442 443 arm32_bootmem_init(0, segment_end, (uintptr_t) KERNEL_BASE_phys); 444 arm32_kernel_vm_init(KERNEL_VM_BASE, ARM_VECTORS_HIGH, 0, 445 marvell_devmap, false); 446 447 /* we've a specific device_register routine */ 448 evbarm_device_register = marvell_device_register; 449 450 /* parse bootargs from U-Boot */ 451 boot_args = bootargs; 452 parse_mi_bootargs(boot_args); 453 454 return initarm_common(KERNEL_VM_BASE, KERNEL_VM_SIZE, NULL, 0); 455 } 456 457 void 458 consinit(void) 459 { 460 static int consinit_called = 0; 461 462 if (consinit_called != 0) 463 return; 464 465 consinit_called = 1; 466 467 #if NCOM > 0 468 { 469 extern int mvuart_cnattach(bus_space_tag_t, bus_addr_t, int, 470 uint32_t, int); 471 472 if (mvuart_cnattach(&mvsoc_bs_tag, 473 MARVELL_INTERREGS_PBASE + MVSOC_COM0_BASE, 474 comcnspeed, mvTclk, comcnmode)) 475 panic("can't init serial console"); 476 } 477 #else 478 panic("serial console not configured"); 479 #endif 480 } 481 482 483 static void 484 marvell_device_register(device_t dev, void *aux) 485 { 486 prop_dictionary_t dict = device_properties(dev); 487 488 #if NCOM > 0 489 if (device_is_a(dev, "com") && 490 device_is_a(device_parent(dev), "mvsoc")) 491 prop_dictionary_set_uint32(dict, "frequency", mvTclk); 492 #endif 493 494 if (device_is_a(dev, "gtidmac")) 495 prop_dictionary_set_uint32(dict, 496 "dmb_speed", mvTclk * sizeof(uint32_t)); /* XXXXXX */ 497 498 #if NGTPCI > 0 && defined(ORION) 499 if (device_is_a(dev, "gtpci")) { 500 extern struct bus_space 501 orion_pci_io_bs_tag, orion_pci_mem_bs_tag; 502 extern struct arm32_pci_chipset arm32_gtpci_chipset; 503 504 prop_data_t io_bs_tag, mem_bs_tag, pc; 505 prop_array_t int2gpp; 506 prop_number_t gpp; 507 uint64_t start, end; 508 int i, j; 509 static struct { 510 const char *boardtype; 511 int pin[PCI_INTERRUPT_PIN_MAX]; 512 } hints[] = { 513 { "kuronas_x4", 514 { 11, PCI_INTERRUPT_PIN_NONE } }, 515 516 { NULL, 517 { PCI_INTERRUPT_PIN_NONE } }, 518 }; 519 520 arm32_gtpci_chipset.pc_conf_v = device_private(dev); 521 arm32_gtpci_chipset.pc_intr_v = device_private(dev); 522 523 io_bs_tag = prop_data_create_data_nocopy( 524 &orion_pci_io_bs_tag, sizeof(struct bus_space)); 525 KASSERT(io_bs_tag != NULL); 526 prop_dictionary_set(dict, "io-bus-tag", io_bs_tag); 527 prop_object_release(io_bs_tag); 528 mem_bs_tag = prop_data_create_data_nocopy( 529 &orion_pci_mem_bs_tag, sizeof(struct bus_space)); 530 KASSERT(mem_bs_tag != NULL); 531 prop_dictionary_set(dict, "mem-bus-tag", mem_bs_tag); 532 prop_object_release(mem_bs_tag); 533 534 pc = prop_data_create_data_nocopy(&arm32_gtpci_chipset, 535 sizeof(struct arm32_pci_chipset)); 536 KASSERT(pc != NULL); 537 prop_dictionary_set(dict, "pci-chipset", pc); 538 prop_object_release(pc); 539 540 marvell_startend_by_tag(ORION_TAG_PCI_IO, &start, &end); 541 prop_dictionary_set_uint64(dict, "iostart", start); 542 prop_dictionary_set_uint64(dict, "ioend", end); 543 marvell_startend_by_tag(ORION_TAG_PCI_MEM, &start, &end); 544 prop_dictionary_set_uint64(dict, "memstart", start); 545 prop_dictionary_set_uint64(dict, "memend", end); 546 prop_dictionary_set_uint32(dict, 547 "cache-line-size", arm_dcache_align); 548 549 /* Setup the hint for interrupt-pin. */ 550 #define BDSTR(s) _BDSTR(s) 551 #define _BDSTR(s) #s 552 #define THIS_BOARD(str) (strcmp(str, BDSTR(EVBARM_BOARDTYPE)) == 0) 553 for (i = 0; hints[i].boardtype != NULL; i++) 554 if (THIS_BOARD(hints[i].boardtype)) 555 break; 556 if (hints[i].boardtype == NULL) 557 return; 558 559 int2gpp = 560 prop_array_create_with_capacity(PCI_INTERRUPT_PIN_MAX + 1); 561 562 /* first set dummy */ 563 gpp = prop_number_create_integer(0); 564 prop_array_add(int2gpp, gpp); 565 prop_object_release(gpp); 566 567 for (j = 0; hints[i].pin[j] != PCI_INTERRUPT_PIN_NONE; j++) { 568 gpp = prop_number_create_integer(hints[i].pin[j]); 569 prop_array_add(int2gpp, gpp); 570 prop_object_release(gpp); 571 } 572 prop_dictionary_set(dict, "int2gpp", int2gpp); 573 } 574 #endif /* NGTPCI > 0 && defined(ORION) */ 575 576 #if NMVPEX > 0 577 if (device_is_a(dev, "mvpex")) { 578 #ifdef ORION 579 extern struct bus_space 580 orion_pex0_io_bs_tag, orion_pex0_mem_bs_tag, 581 orion_pex1_io_bs_tag, orion_pex1_mem_bs_tag; 582 #endif 583 #ifdef KIRKWOOD 584 extern struct bus_space 585 kirkwood_pex_io_bs_tag, kirkwood_pex_mem_bs_tag, 586 kirkwood_pex1_io_bs_tag, kirkwood_pex1_mem_bs_tag; 587 #endif 588 #ifdef ARMADAXP 589 extern struct bus_space 590 armadaxp_pex00_io_bs_tag, armadaxp_pex00_mem_bs_tag, 591 armadaxp_pex01_io_bs_tag, armadaxp_pex01_mem_bs_tag, 592 armadaxp_pex02_io_bs_tag, armadaxp_pex02_mem_bs_tag, 593 armadaxp_pex03_io_bs_tag, armadaxp_pex03_mem_bs_tag, 594 armadaxp_pex2_io_bs_tag, armadaxp_pex2_mem_bs_tag, 595 armadaxp_pex3_io_bs_tag, armadaxp_pex3_mem_bs_tag; 596 int i; 597 #endif 598 extern struct arm32_pci_chipset 599 arm32_mvpex0_chipset, arm32_mvpex1_chipset; 600 601 struct marvell_attach_args *mva = aux; 602 struct bus_space *mvpex_io_bs_tag, *mvpex_mem_bs_tag; 603 struct arm32_pci_chipset *arm32_mvpex_chipset; 604 prop_data_t io_bs_tag, mem_bs_tag, pc; 605 uint64_t start, end; 606 int iotag, memtag; 607 608 switch (mvsoc_model()) { 609 #ifdef ORION 610 case MARVELL_ORION_1_88F5180N: 611 case MARVELL_ORION_1_88F5181: 612 case MARVELL_ORION_1_88F5182: 613 case MARVELL_ORION_1_88W8660: 614 case MARVELL_ORION_2_88F5281: 615 if (mva->mva_offset == MVSOC_PEX_BASE) { 616 mvpex_io_bs_tag = &orion_pex0_io_bs_tag; 617 mvpex_mem_bs_tag = &orion_pex0_mem_bs_tag; 618 arm32_mvpex_chipset = &arm32_mvpex0_chipset; 619 iotag = ORION_TAG_PEX0_IO; 620 memtag = ORION_TAG_PEX0_MEM; 621 } else { 622 mvpex_io_bs_tag = &orion_pex1_io_bs_tag; 623 mvpex_mem_bs_tag = &orion_pex1_mem_bs_tag; 624 arm32_mvpex_chipset = &arm32_mvpex1_chipset; 625 iotag = ORION_TAG_PEX1_IO; 626 memtag = ORION_TAG_PEX1_MEM; 627 } 628 break; 629 #endif 630 631 #ifdef KIRKWOOD 632 case MARVELL_KIRKWOOD_88F6282: 633 if (mva->mva_offset != MVSOC_PEX_BASE) { 634 mvpex_io_bs_tag = &kirkwood_pex1_io_bs_tag; 635 mvpex_mem_bs_tag = &kirkwood_pex1_mem_bs_tag; 636 arm32_mvpex_chipset = &arm32_mvpex1_chipset; 637 iotag = KIRKWOOD_TAG_PEX1_IO; 638 memtag = KIRKWOOD_TAG_PEX1_MEM; 639 break; 640 } 641 642 /* FALLTHROUGH */ 643 644 case MARVELL_KIRKWOOD_88F6180: 645 case MARVELL_KIRKWOOD_88F6192: 646 case MARVELL_KIRKWOOD_88F6281: 647 mvpex_io_bs_tag = &kirkwood_pex_io_bs_tag; 648 mvpex_mem_bs_tag = &kirkwood_pex_mem_bs_tag; 649 arm32_mvpex_chipset = &arm32_mvpex0_chipset; 650 iotag = KIRKWOOD_TAG_PEX_IO; 651 memtag = KIRKWOOD_TAG_PEX_MEM; 652 break; 653 #endif 654 655 #ifdef ARMADAXP 656 case MARVELL_ARMADAXP_MV78130: 657 case MARVELL_ARMADAXP_MV78160: 658 case MARVELL_ARMADAXP_MV78230: 659 case MARVELL_ARMADAXP_MV78260: 660 case MARVELL_ARMADAXP_MV78460: 661 { 662 extern struct arm32_pci_chipset 663 arm32_mvpex2_chipset, arm32_mvpex3_chipset, 664 arm32_mvpex4_chipset, arm32_mvpex5_chipset; 665 const struct { 666 bus_size_t offset; 667 struct bus_space *io_bs_tag; 668 struct bus_space *mem_bs_tag; 669 struct arm32_pci_chipset *chipset; 670 int iotag; 671 int memtag; 672 } mvpex_tags[] = { 673 { MVSOC_PEX_BASE, 674 &armadaxp_pex00_io_bs_tag, 675 &armadaxp_pex00_mem_bs_tag, 676 &arm32_mvpex0_chipset, 677 ARMADAXP_TAG_PEX00_IO, 678 ARMADAXP_TAG_PEX00_MEM }, 679 680 { ARMADAXP_PEX01_BASE, 681 &armadaxp_pex01_io_bs_tag, 682 &armadaxp_pex01_mem_bs_tag, 683 &arm32_mvpex1_chipset, 684 ARMADAXP_TAG_PEX01_IO, 685 ARMADAXP_TAG_PEX01_MEM }, 686 687 { ARMADAXP_PEX02_BASE, 688 &armadaxp_pex02_io_bs_tag, 689 &armadaxp_pex02_mem_bs_tag, 690 &arm32_mvpex2_chipset, 691 ARMADAXP_TAG_PEX02_IO, 692 ARMADAXP_TAG_PEX02_MEM }, 693 694 { ARMADAXP_PEX03_BASE, 695 &armadaxp_pex03_io_bs_tag, 696 &armadaxp_pex03_mem_bs_tag, 697 &arm32_mvpex3_chipset, 698 ARMADAXP_TAG_PEX03_IO, 699 ARMADAXP_TAG_PEX03_MEM }, 700 701 { ARMADAXP_PEX2_BASE, 702 &armadaxp_pex2_io_bs_tag, 703 &armadaxp_pex2_mem_bs_tag, 704 &arm32_mvpex4_chipset, 705 ARMADAXP_TAG_PEX2_IO, 706 ARMADAXP_TAG_PEX2_MEM }, 707 708 { ARMADAXP_PEX3_BASE, 709 &armadaxp_pex3_io_bs_tag, 710 &armadaxp_pex3_mem_bs_tag, 711 &arm32_mvpex5_chipset, 712 ARMADAXP_TAG_PEX3_IO, 713 ARMADAXP_TAG_PEX3_MEM }, 714 715 { 0, 0, 0, 0, 0 }, 716 }; 717 718 for (i = 0; mvpex_tags[i].offset != 0; i++) { 719 if (mva->mva_offset != mvpex_tags[i].offset) 720 continue; 721 break; 722 } 723 if (mvpex_tags[i].offset == 0) 724 return; 725 mvpex_io_bs_tag = mvpex_tags[i].io_bs_tag; 726 mvpex_mem_bs_tag = mvpex_tags[i].mem_bs_tag; 727 arm32_mvpex_chipset = mvpex_tags[i].chipset; 728 iotag = mvpex_tags[i].iotag; 729 memtag = mvpex_tags[i].memtag; 730 break; 731 } 732 #endif 733 734 default: 735 return; 736 } 737 738 arm32_mvpex_chipset->pc_conf_v = device_private(dev); 739 arm32_mvpex_chipset->pc_intr_v = device_private(dev); 740 741 io_bs_tag = prop_data_create_data_nocopy( 742 mvpex_io_bs_tag, sizeof(struct bus_space)); 743 KASSERT(io_bs_tag != NULL); 744 prop_dictionary_set(dict, "io-bus-tag", io_bs_tag); 745 prop_object_release(io_bs_tag); 746 mem_bs_tag = prop_data_create_data_nocopy( 747 mvpex_mem_bs_tag, sizeof(struct bus_space)); 748 KASSERT(mem_bs_tag != NULL); 749 prop_dictionary_set(dict, "mem-bus-tag", mem_bs_tag); 750 prop_object_release(mem_bs_tag); 751 752 pc = prop_data_create_data_nocopy(arm32_mvpex_chipset, 753 sizeof(struct arm32_pci_chipset)); 754 KASSERT(pc != NULL); 755 prop_dictionary_set(dict, "pci-chipset", pc); 756 prop_object_release(pc); 757 758 marvell_startend_by_tag(iotag, &start, &end); 759 prop_dictionary_set_uint64(dict, "iostart", start); 760 prop_dictionary_set_uint64(dict, "ioend", end); 761 marvell_startend_by_tag(memtag, &start, &end); 762 prop_dictionary_set_uint64(dict, "memstart", start); 763 prop_dictionary_set_uint64(dict, "memend", end); 764 prop_dictionary_set_uint32(dict, 765 "cache-line-size", arm_dcache_align); 766 } 767 #endif 768 } 769 770 #if NGTPCI > 0 || NMVPEX > 0 771 static void 772 marvell_startend_by_tag(int tag, uint64_t *start, uint64_t *end) 773 { 774 uint32_t base, size; 775 int win; 776 777 win = mvsoc_target(tag, NULL, NULL, &base, &size); 778 if (size != 0) { 779 if (win < nremap) 780 *start = read_mlmbreg(MVSOC_MLMB_WRLR(win)) | 781 ((read_mlmbreg(MVSOC_MLMB_WRHR(win)) << 16) << 16); 782 else 783 *start = base; 784 *end = *start + size - 1; 785 } 786 } 787 #endif 788
Indexes created Tue Sep 30 20:09:53 GMT 2025