marvell_machdep.c revision 1.25
1 /* $NetBSD: marvell_machdep.c,v 1.25 2013/12/23 03:19:43 kiyohara Exp $ */ 2 /* 3 * Copyright (c) 2007, 2008, 2010 KIYOHARA Takashi 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 17 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 18 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 19 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 20 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 21 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 23 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 24 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 */ 27 #include <sys/cdefs.h> 28 __KERNEL_RCSID(0, "$NetBSD: marvell_machdep.c,v 1.25 2013/12/23 03:19:43 kiyohara Exp $"); 29 30 #include "opt_evbarm_boardtype.h" 31 #include "opt_ddb.h" 32 #include "opt_pci.h" 33 #include "opt_mvsoc.h" 34 #include "com.h" 35 #include "gtpci.h" 36 #include "mvpex.h" 37 38 #include <sys/param.h> 39 #include <sys/kernel.h> 40 #include <sys/reboot.h> 41 #include <sys/systm.h> 42 #include <sys/termios.h> 43 44 #include <prop/proplib.h> 45 46 #include <dev/cons.h> 47 #include <dev/md.h> 48 49 #include <dev/marvell/marvellreg.h> 50 #include <dev/marvell/marvellvar.h> 51 #include <dev/pci/pcireg.h> 52 #include <dev/pci/pcivar.h> 53 54 #include <machine/autoconf.h> 55 #include <machine/bootconfig.h> 56 #include <machine/pci_machdep.h> 57 58 #include <uvm/uvm_extern.h> 59 60 #include <arm/db_machdep.h> 61 #include <arm/undefined.h> 62 #include <arm/arm32/machdep.h> 63 64 #include <arm/marvell/mvsocreg.h> 65 #include <arm/marvell/mvsocvar.h> 66 #include <arm/marvell/orionreg.h> 67 #include <arm/marvell/kirkwoodreg.h> 68 #include <arm/marvell/mv78xx0reg.h> 69 #include <arm/marvell/armadaxpreg.h> 70 #include <arm/marvell/mvsocgppvar.h> 71 72 #include <evbarm/marvell/marvellreg.h> 73 #include <evbarm/marvell/marvellvar.h> 74 75 #include <ddb/db_extern.h> 76 #include <ddb/db_sym.h> 77 78 #include "ksyms.h" 79 80 81 /* Kernel text starts 2MB in from the bottom of the kernel address space. */ 82 #define KERNEL_TEXT_BASE (KERNEL_BASE + 0x00000000) 83 #define KERNEL_VM_BASE (KERNEL_BASE + 0x02000000) 84 85 /* 86 * The range 0xc2000000 - 0xdfffffff is available for kernel VM space 87 * Core-logic registers and I/O mappings occupy 0xfe000000 - 0xffffffff 88 */ 89 #define KERNEL_VM_SIZE 0x1e000000 90 91 BootConfig bootconfig; /* Boot config storage */ 92 static char bootargs[MAX_BOOT_STRING]; 93 char *boot_args = NULL; 94 95 extern int KERNEL_BASE_phys[]; 96 extern char _end[]; 97 98 /* 99 * Macros to translate between physical and virtual for a subset of the 100 * kernel address space. *Not* for general use. 101 */ 102 #define KERNEL_BASE_PHYS physical_start 103 #define KERN_VTOPHYS(va) \ 104 ((paddr_t)((vaddr_t)va - KERNEL_BASE + KERNEL_BASE_PHYS)) 105 #define KERN_PHYSTOV(pa) \ 106 ((vaddr_t)((paddr_t)pa - KERNEL_BASE_PHYS + KERNEL_BASE)) 107 108 109 #include "com.h" 110 #if NCOM > 0 111 #include <dev/ic/comreg.h> 112 #include <dev/ic/comvar.h> 113 #endif 114 115 #ifndef CONSPEED 116 #define CONSPEED B115200 /* It's a setting of the default of u-boot */ 117 #endif 118 #ifndef CONMODE 119 #define CONMODE ((TTYDEF_CFLAG & ~(CSIZE | CSTOPB | PARENB)) | CS8) /* 8N1 */ 120 121 int comcnspeed = CONSPEED; 122 int comcnmode = CONMODE; 123 #endif 124 125 #include "opt_kgdb.h" 126 #ifdef KGDB 127 #include <sys/kgdb.h> 128 #endif 129 130 static void marvell_device_register(device_t, void *); 131 #if NGTPCI > 0 || NMVPEX > 0 132 static void marvell_startend_by_tag(int, uint64_t *, uint64_t *); 133 #endif 134 135 #if defined(ORION) || defined(KIRKWOOD) || defined(MV78XX0) 136 static void 137 marvell_system_reset(void) 138 { 139 /* unmask soft reset */ 140 write_mlmbreg(MVSOC_MLMB_RSTOUTNMASKR, 141 MVSOC_MLMB_RSTOUTNMASKR_SOFTRSTOUTEN); 142 /* assert soft reset */ 143 write_mlmbreg(MVSOC_MLMB_SSRR, MVSOC_MLMB_SSRR_SYSTEMSOFTRST); 144 145 /* if we're still running, jump to the reset address */ 146 cpu_reset_address = 0; 147 cpu_reset_address_paddr = 0xffff0000; 148 cpu_reset(); 149 /*NOTREACHED*/ 150 } 151 #endif 152 153 #if defined(ARMADAXP) 154 static void 155 armadaxp_system_reset(void) 156 { 157 extern vaddr_t misc_base; 158 159 #define write_miscreg(r, v) (*(volatile uint32_t *)(misc_base + (r)) = (v)) 160 161 /* Unmask soft reset */ 162 write_miscreg(ARMADAXP_MISC_RSTOUTNMASKR, 163 ARMADAXP_MISC_RSTOUTNMASKR_GLOBALSOFTRSTOUTEN); 164 /* Assert soft reset */ 165 write_miscreg(ARMADAXP_MISC_SSRR, ARMADAXP_MISC_SSRR_GLOBALSOFTRST); 166 167 while (1); 168 169 /*NOTREACHED*/ 170 } 171 #endif 172 173 174 static inline 175 pd_entry_t * 176 read_ttb(void) 177 { 178 long ttb; 179 180 __asm volatile("mrc p15, 0, %0, c2, c0, 0" : "=r" (ttb)); 181 182 return (pd_entry_t *)(ttb & ~((1<<14)-1)); 183 } 184 185 /* 186 * Static device mappings. These peripheral registers are mapped at 187 * fixed virtual addresses very early in initarm() so that we can use 188 * them while booting the kernel, and stay at the same address 189 * throughout whole kernel's life time. 190 * 191 * We use this table twice; once with bootstrap page table, and once 192 * with kernel's page table which we build up in initarm(). 193 * 194 * Since we map these registers into the bootstrap page table using 195 * pmap_devmap_bootstrap() which calls pmap_map_chunk(), we map 196 * registers segment-aligned and segment-rounded in order to avoid 197 * using the 2nd page tables. 198 */ 199 #define _A(a) ((a) & ~L1_S_OFFSET) 200 #define _S(s) (((s) + L1_S_SIZE - 1) & ~(L1_S_SIZE-1)) 201 202 static struct pmap_devmap marvell_devmap[] = { 203 { 204 MARVELL_INTERREGS_VBASE, 205 #if (defined(ORION) || defined(KIRKWOOD) || defined(MV78XX0)) && \ 206 defined(ARMADAXP) 207 _A(0x00000000), 208 #else 209 _A(MARVELL_INTERREGS_PBASE), 210 #endif 211 _S(MARVELL_INTERREGS_SIZE), 212 VM_PROT_READ|VM_PROT_WRITE, 213 PTE_NOCACHE, 214 }, 215 216 { 0, 0, 0, 0, 0 } 217 }; 218 219 extern uint32_t *u_boot_args[]; 220 221 /* 222 * u_int initarm(...) 223 * 224 * Initial entry point on startup. This gets called before main() is 225 * entered. 226 * It should be responsible for setting up everything that must be 227 * in place when main is called. 228 * This includes 229 * Taking a copy of the boot configuration structure. 230 * Initialising the physical console so characters can be printed. 231 * Setting up page tables for the kernel 232 * Relocating the kernel to the bottom of physical memory 233 */ 234 u_int 235 initarm(void *arg) 236 { 237 uint32_t target, attr, base, size; 238 int cs, memtag = 0, iotag = 0, window; 239 240 mvsoc_bootstrap(MARVELL_INTERREGS_VBASE); 241 242 /* 243 * Heads up ... Setup the CPU / MMU / TLB functions 244 */ 245 if (set_cpufuncs()) 246 panic("cpu not recognized!"); 247 248 #if (defined(ORION) || defined(KIRKWOOD) || defined(MV78XX0)) && \ 249 defined(ARMADAXP) 250 int i; 251 252 for (i = 0; marvell_devmap[i].pd_size != 0; i++) 253 if (marvell_devmap[i].pd_va == MARVELL_INTERREGS_VBASE) { 254 marvell_devmap[i].pd_pa = _A(MARVELL_INTERREGS_PBASE); 255 break; 256 } 257 #endif 258 259 /* map some peripheral registers */ 260 pmap_devmap_bootstrap((vaddr_t)read_ttb(), marvell_devmap); 261 262 /* 263 * U-Boot doesn't use the virtual memory. 264 * 265 * Physical Address Range Description 266 * ----------------------- ---------------------------------- 267 * 0x00000000 - 0x0fffffff SDRAM Bank 0 (max 256MB) 268 * 0x10000000 - 0x1fffffff SDRAM Bank 1 (max 256MB) 269 * 0x20000000 - 0x2fffffff SDRAM Bank 2 (max 256MB) 270 * 0x30000000 - 0x3fffffff SDRAM Bank 3 (max 256MB) 271 * 0xf1000000 - 0xf10fffff SoC Internal Registers 272 */ 273 274 cpu_domains((DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL*2)) | DOMAIN_CLIENT); 275 276 /* Get ready for splfoo() */ 277 switch (mvsoc_model()) { 278 #ifdef ORION 279 case MARVELL_ORION_1_88F1181: 280 case MARVELL_ORION_1_88F5082: 281 case MARVELL_ORION_1_88F5180N: 282 case MARVELL_ORION_1_88F5181: 283 case MARVELL_ORION_1_88F5182: 284 case MARVELL_ORION_1_88F6082: 285 case MARVELL_ORION_1_88F6183: 286 case MARVELL_ORION_1_88W8660: 287 case MARVELL_ORION_2_88F1281: 288 case MARVELL_ORION_2_88F5281: 289 cpu_reset_address = marvell_system_reset; 290 291 orion_intr_bootstrap(); 292 293 memtag = ORION_TAG_PEX0_MEM; 294 iotag = ORION_TAG_PEX0_IO; 295 nwindow = ORION_MLMB_NWINDOW; 296 nremap = ORION_MLMB_NREMAP; 297 298 orion_getclks(MARVELL_INTERREGS_VBASE); 299 break; 300 #endif /* ORION */ 301 302 #ifdef KIRKWOOD 303 case MARVELL_KIRKWOOD_88F6180: 304 case MARVELL_KIRKWOOD_88F6192: 305 case MARVELL_KIRKWOOD_88F6281: 306 case MARVELL_KIRKWOOD_88F6282: 307 cpu_reset_address = marvell_system_reset; 308 309 kirkwood_intr_bootstrap(); 310 311 memtag = KIRKWOOD_TAG_PEX_MEM; 312 iotag = KIRKWOOD_TAG_PEX_IO; 313 nwindow = KIRKWOOD_MLMB_NWINDOW; 314 nremap = KIRKWOOD_MLMB_NREMAP; 315 316 kirkwood_getclks(MARVELL_INTERREGS_VBASE); 317 break; 318 #endif /* KIRKWOOD */ 319 320 #ifdef MV78XX0 321 case MARVELL_MV78XX0_MV78100: 322 case MARVELL_MV78XX0_MV78200: 323 cpu_reset_address = marvell_system_reset; 324 325 mv78xx0_intr_bootstrap(); 326 327 memtag = MV78XX0_TAG_PEX0_MEM; 328 iotag = MV78XX0_TAG_PEX0_IO; 329 nwindow = MV78XX0_MLMB_NWINDOW; 330 nremap = MV78XX0_MLMB_NREMAP; 331 332 mv78xx0_getclks(MARVELL_INTERREGS_VBASE); 333 break; 334 #endif /* MV78XX0 */ 335 336 #ifdef ARMADAXP 337 case MARVELL_ARMADAXP_MV78130: 338 case MARVELL_ARMADAXP_MV78160: 339 case MARVELL_ARMADAXP_MV78230: 340 case MARVELL_ARMADAXP_MV78260: 341 case MARVELL_ARMADAXP_MV78460: 342 cpu_reset_address = armadaxp_system_reset; 343 344 armadaxp_intr_bootstrap(MARVELL_INTERREGS_PBASE); 345 346 memtag = ARMADAXP_TAG_PEX00_MEM; 347 iotag = ARMADAXP_TAG_PEX00_IO; 348 nwindow = ARMADAXP_MLMB_NWINDOW; 349 nremap = ARMADAXP_MLMB_NREMAP; 350 351 extern vaddr_t misc_base; 352 misc_base = MARVELL_INTERREGS_VBASE + ARMADAXP_MISC_BASE; 353 armadaxp_getclks(); 354 355 #ifdef L2CACHE_ENABLE 356 /* Initialize L2 Cache */ 357 { 358 extern int armadaxp_l2_init(bus_addr_t); 359 360 (void)armadaxp_l2_init(MARVELL_INTERREGS_PBASE); 361 } 362 #endif 363 364 #ifdef AURORA_IO_CACHE_COHERENCY 365 /* Initialize cache coherency */ 366 armadaxp_io_coherency_init(); 367 #endif 368 break; 369 #endif /* ARMADAXP */ 370 371 default: 372 /* We can't output console here yet... */ 373 panic("unknown model...\n"); 374 375 /* NOTREACHED */ 376 } 377 378 consinit(); 379 380 /* Talk to the user */ 381 #ifndef EVBARM_BOARDTYPE 382 #define EVBARM_BOARDTYPE Marvell 383 #endif 384 #define BDSTR(s) _BDSTR(s) 385 #define _BDSTR(s) #s 386 printf("\nNetBSD/evbarm (" BDSTR(EVBARM_BOARDTYPE) ") booting ...\n"); 387 388 /* Reset PCI-Express space to window register. */ 389 window = mvsoc_target(memtag, &target, &attr, NULL, NULL); 390 write_mlmbreg(MVSOC_MLMB_WCR(window), 391 MVSOC_MLMB_WCR_WINEN | 392 MVSOC_MLMB_WCR_TARGET(target) | 393 MVSOC_MLMB_WCR_ATTR(attr) | 394 MVSOC_MLMB_WCR_SIZE(MARVELL_PEXMEM_SIZE)); 395 write_mlmbreg(MVSOC_MLMB_WBR(window), 396 MARVELL_PEXMEM_PBASE & MVSOC_MLMB_WBR_BASE_MASK); 397 #ifdef PCI_NETBSD_CONFIGURE 398 if (window < nremap) { 399 write_mlmbreg(MVSOC_MLMB_WRLR(window), 400 MARVELL_PEXMEM_PBASE & MVSOC_MLMB_WRLR_REMAP_MASK); 401 write_mlmbreg(MVSOC_MLMB_WRHR(window), 0); 402 } 403 #endif 404 window = mvsoc_target(iotag, &target, &attr, NULL, NULL); 405 write_mlmbreg(MVSOC_MLMB_WCR(window), 406 MVSOC_MLMB_WCR_WINEN | 407 MVSOC_MLMB_WCR_TARGET(target) | 408 MVSOC_MLMB_WCR_ATTR(attr) | 409 MVSOC_MLMB_WCR_SIZE(MARVELL_PEXIO_SIZE)); 410 write_mlmbreg(MVSOC_MLMB_WBR(window), 411 MARVELL_PEXIO_PBASE & MVSOC_MLMB_WBR_BASE_MASK); 412 #ifdef PCI_NETBSD_CONFIGURE 413 if (window < nremap) { 414 write_mlmbreg(MVSOC_MLMB_WRLR(window), 415 MARVELL_PEXIO_PBASE & MVSOC_MLMB_WRLR_REMAP_MASK); 416 write_mlmbreg(MVSOC_MLMB_WRHR(window), 0); 417 } 418 #endif 419 420 /* copy command line U-Boot gave us, if args is valid. */ 421 if (u_boot_args[3] != 0) /* XXXXX: need more check?? */ 422 strncpy(bootargs, (char *)u_boot_args[3], sizeof(bootargs)); 423 424 #ifdef VERBOSE_INIT_ARM 425 printf("initarm: Configuring system ...\n"); 426 #endif 427 428 bootconfig.dramblocks = 0; 429 paddr_t segment_end; 430 segment_end = physmem = 0; 431 for (cs = MARVELL_TAG_SDRAM_CS0; cs <= MARVELL_TAG_SDRAM_CS3; cs++) { 432 mvsoc_target(cs, &target, &attr, &base, &size); 433 if (size == 0) 434 continue; 435 436 bootconfig.dram[bootconfig.dramblocks].address = base; 437 bootconfig.dram[bootconfig.dramblocks].pages = size / PAGE_SIZE; 438 439 if (base != segment_end) 440 panic("memory hole not support"); 441 442 segment_end += size; 443 physmem += size / PAGE_SIZE; 444 445 bootconfig.dramblocks++; 446 } 447 448 arm32_bootmem_init(0, segment_end, (uintptr_t) KERNEL_BASE_phys); 449 arm32_kernel_vm_init(KERNEL_VM_BASE, ARM_VECTORS_HIGH, 0, 450 marvell_devmap, false); 451 452 /* we've a specific device_register routine */ 453 evbarm_device_register = marvell_device_register; 454 455 /* parse bootargs from U-Boot */ 456 boot_args = bootargs; 457 parse_mi_bootargs(boot_args); 458 459 return initarm_common(KERNEL_VM_BASE, KERNEL_VM_SIZE, NULL, 0); 460 } 461 462 void 463 consinit(void) 464 { 465 static int consinit_called = 0; 466 467 if (consinit_called != 0) 468 return; 469 470 consinit_called = 1; 471 472 #if NCOM > 0 473 { 474 extern int mvuart_cnattach(bus_space_tag_t, bus_addr_t, int, 475 uint32_t, int); 476 477 if (mvuart_cnattach(&mvsoc_bs_tag, 478 MARVELL_INTERREGS_PBASE + MVSOC_COM0_BASE, 479 comcnspeed, mvTclk, comcnmode)) 480 panic("can't init serial console"); 481 } 482 #else 483 panic("serial console not configured"); 484 #endif 485 } 486 487 488 static void 489 marvell_device_register(device_t dev, void *aux) 490 { 491 prop_dictionary_t dict = device_properties(dev); 492 493 #if NCOM > 0 494 if (device_is_a(dev, "com") && 495 device_is_a(device_parent(dev), "mvsoc")) 496 prop_dictionary_set_uint32(dict, "frequency", mvTclk); 497 #endif 498 499 if (device_is_a(dev, "gtidmac")) 500 prop_dictionary_set_uint32(dict, 501 "dmb_speed", mvTclk * sizeof(uint32_t)); /* XXXXXX */ 502 503 #if NGTPCI > 0 && defined(ORION) 504 if (device_is_a(dev, "gtpci")) { 505 extern struct bus_space 506 orion_pci_io_bs_tag, orion_pci_mem_bs_tag; 507 extern struct arm32_pci_chipset arm32_gtpci_chipset; 508 509 prop_data_t io_bs_tag, mem_bs_tag, pc; 510 prop_array_t int2gpp; 511 prop_number_t gpp; 512 uint64_t start, end; 513 int i, j; 514 static struct { 515 const char *boardtype; 516 int pin[PCI_INTERRUPT_PIN_MAX]; 517 } hints[] = { 518 { "kuronas_x4", 519 { 11, PCI_INTERRUPT_PIN_NONE } }, 520 521 { NULL, 522 { PCI_INTERRUPT_PIN_NONE } }, 523 }; 524 525 arm32_gtpci_chipset.pc_conf_v = device_private(dev); 526 arm32_gtpci_chipset.pc_intr_v = device_private(dev); 527 528 io_bs_tag = prop_data_create_data_nocopy( 529 &orion_pci_io_bs_tag, sizeof(struct bus_space)); 530 KASSERT(io_bs_tag != NULL); 531 prop_dictionary_set(dict, "io-bus-tag", io_bs_tag); 532 prop_object_release(io_bs_tag); 533 mem_bs_tag = prop_data_create_data_nocopy( 534 &orion_pci_mem_bs_tag, sizeof(struct bus_space)); 535 KASSERT(mem_bs_tag != NULL); 536 prop_dictionary_set(dict, "mem-bus-tag", mem_bs_tag); 537 prop_object_release(mem_bs_tag); 538 539 pc = prop_data_create_data_nocopy(&arm32_gtpci_chipset, 540 sizeof(struct arm32_pci_chipset)); 541 KASSERT(pc != NULL); 542 prop_dictionary_set(dict, "pci-chipset", pc); 543 prop_object_release(pc); 544 545 marvell_startend_by_tag(ORION_TAG_PCI_IO, &start, &end); 546 prop_dictionary_set_uint64(dict, "iostart", start); 547 prop_dictionary_set_uint64(dict, "ioend", end); 548 marvell_startend_by_tag(ORION_TAG_PCI_MEM, &start, &end); 549 prop_dictionary_set_uint64(dict, "memstart", start); 550 prop_dictionary_set_uint64(dict, "memend", end); 551 prop_dictionary_set_uint32(dict, 552 "cache-line-size", arm_dcache_align); 553 554 /* Setup the hint for interrupt-pin. */ 555 #define BDSTR(s) _BDSTR(s) 556 #define _BDSTR(s) #s 557 #define THIS_BOARD(str) (strcmp(str, BDSTR(EVBARM_BOARDTYPE)) == 0) 558 for (i = 0; hints[i].boardtype != NULL; i++) 559 if (THIS_BOARD(hints[i].boardtype)) 560 break; 561 if (hints[i].boardtype == NULL) 562 return; 563 564 int2gpp = 565 prop_array_create_with_capacity(PCI_INTERRUPT_PIN_MAX + 1); 566 567 /* first set dummy */ 568 gpp = prop_number_create_integer(0); 569 prop_array_add(int2gpp, gpp); 570 prop_object_release(gpp); 571 572 for (j = 0; hints[i].pin[j] != PCI_INTERRUPT_PIN_NONE; j++) { 573 gpp = prop_number_create_integer(hints[i].pin[j]); 574 prop_array_add(int2gpp, gpp); 575 prop_object_release(gpp); 576 } 577 prop_dictionary_set(dict, "int2gpp", int2gpp); 578 } 579 #endif /* NGTPCI > 0 && defined(ORION) */ 580 581 #if NMVPEX > 0 582 if (device_is_a(dev, "mvpex")) { 583 #ifdef ORION 584 extern struct bus_space 585 orion_pex0_io_bs_tag, orion_pex0_mem_bs_tag, 586 orion_pex1_io_bs_tag, orion_pex1_mem_bs_tag; 587 #endif 588 #ifdef KIRKWOOD 589 extern struct bus_space 590 kirkwood_pex_io_bs_tag, kirkwood_pex_mem_bs_tag, 591 kirkwood_pex1_io_bs_tag, kirkwood_pex1_mem_bs_tag; 592 #endif 593 #ifdef ARMADAXP 594 extern struct bus_space 595 armadaxp_pex00_io_bs_tag, armadaxp_pex00_mem_bs_tag, 596 armadaxp_pex01_io_bs_tag, armadaxp_pex01_mem_bs_tag, 597 armadaxp_pex02_io_bs_tag, armadaxp_pex02_mem_bs_tag, 598 armadaxp_pex03_io_bs_tag, armadaxp_pex03_mem_bs_tag, 599 armadaxp_pex2_io_bs_tag, armadaxp_pex2_mem_bs_tag, 600 armadaxp_pex3_io_bs_tag, armadaxp_pex3_mem_bs_tag; 601 int i; 602 #endif 603 extern struct arm32_pci_chipset 604 arm32_mvpex0_chipset, arm32_mvpex1_chipset; 605 606 struct marvell_attach_args *mva = aux; 607 struct bus_space *mvpex_io_bs_tag, *mvpex_mem_bs_tag; 608 struct arm32_pci_chipset *arm32_mvpex_chipset; 609 prop_data_t io_bs_tag, mem_bs_tag, pc; 610 uint64_t start, end; 611 int iotag, memtag; 612 613 switch (mvsoc_model()) { 614 #ifdef ORION 615 case MARVELL_ORION_1_88F5180N: 616 case MARVELL_ORION_1_88F5181: 617 case MARVELL_ORION_1_88F5182: 618 case MARVELL_ORION_1_88W8660: 619 case MARVELL_ORION_2_88F5281: 620 if (mva->mva_offset == MVSOC_PEX_BASE) { 621 mvpex_io_bs_tag = &orion_pex0_io_bs_tag; 622 mvpex_mem_bs_tag = &orion_pex0_mem_bs_tag; 623 arm32_mvpex_chipset = &arm32_mvpex0_chipset; 624 iotag = ORION_TAG_PEX0_IO; 625 memtag = ORION_TAG_PEX0_MEM; 626 } else { 627 mvpex_io_bs_tag = &orion_pex1_io_bs_tag; 628 mvpex_mem_bs_tag = &orion_pex1_mem_bs_tag; 629 arm32_mvpex_chipset = &arm32_mvpex1_chipset; 630 iotag = ORION_TAG_PEX1_IO; 631 memtag = ORION_TAG_PEX1_MEM; 632 } 633 break; 634 #endif 635 636 #ifdef KIRKWOOD 637 case MARVELL_KIRKWOOD_88F6282: 638 if (mva->mva_offset != MVSOC_PEX_BASE) { 639 mvpex_io_bs_tag = &kirkwood_pex1_io_bs_tag; 640 mvpex_mem_bs_tag = &kirkwood_pex1_mem_bs_tag; 641 arm32_mvpex_chipset = &arm32_mvpex1_chipset; 642 iotag = KIRKWOOD_TAG_PEX1_IO; 643 memtag = KIRKWOOD_TAG_PEX1_MEM; 644 break; 645 } 646 647 /* FALLTHROUGH */ 648 649 case MARVELL_KIRKWOOD_88F6180: 650 case MARVELL_KIRKWOOD_88F6192: 651 case MARVELL_KIRKWOOD_88F6281: 652 mvpex_io_bs_tag = &kirkwood_pex_io_bs_tag; 653 mvpex_mem_bs_tag = &kirkwood_pex_mem_bs_tag; 654 arm32_mvpex_chipset = &arm32_mvpex0_chipset; 655 iotag = KIRKWOOD_TAG_PEX_IO; 656 memtag = KIRKWOOD_TAG_PEX_MEM; 657 break; 658 #endif 659 660 #ifdef ARMADAXP 661 case MARVELL_ARMADAXP_MV78130: 662 case MARVELL_ARMADAXP_MV78160: 663 case MARVELL_ARMADAXP_MV78230: 664 case MARVELL_ARMADAXP_MV78260: 665 case MARVELL_ARMADAXP_MV78460: 666 { 667 extern struct arm32_pci_chipset 668 arm32_mvpex2_chipset, arm32_mvpex3_chipset, 669 arm32_mvpex4_chipset, arm32_mvpex5_chipset; 670 const struct { 671 bus_size_t offset; 672 struct bus_space *io_bs_tag; 673 struct bus_space *mem_bs_tag; 674 struct arm32_pci_chipset *chipset; 675 int iotag; 676 int memtag; 677 } mvpex_tags[] = { 678 { MVSOC_PEX_BASE, 679 &armadaxp_pex00_io_bs_tag, 680 &armadaxp_pex00_mem_bs_tag, 681 &arm32_mvpex0_chipset, 682 ARMADAXP_TAG_PEX00_IO, 683 ARMADAXP_TAG_PEX00_MEM }, 684 685 { ARMADAXP_PEX01_BASE, 686 &armadaxp_pex01_io_bs_tag, 687 &armadaxp_pex01_mem_bs_tag, 688 &arm32_mvpex1_chipset, 689 ARMADAXP_TAG_PEX01_IO, 690 ARMADAXP_TAG_PEX01_MEM }, 691 692 { ARMADAXP_PEX02_BASE, 693 &armadaxp_pex02_io_bs_tag, 694 &armadaxp_pex02_mem_bs_tag, 695 &arm32_mvpex2_chipset, 696 ARMADAXP_TAG_PEX02_IO, 697 ARMADAXP_TAG_PEX02_MEM }, 698 699 { ARMADAXP_PEX03_BASE, 700 &armadaxp_pex03_io_bs_tag, 701 &armadaxp_pex03_mem_bs_tag, 702 &arm32_mvpex3_chipset, 703 ARMADAXP_TAG_PEX03_IO, 704 ARMADAXP_TAG_PEX03_MEM }, 705 706 { ARMADAXP_PEX2_BASE, 707 &armadaxp_pex2_io_bs_tag, 708 &armadaxp_pex2_mem_bs_tag, 709 &arm32_mvpex4_chipset, 710 ARMADAXP_TAG_PEX2_IO, 711 ARMADAXP_TAG_PEX2_MEM }, 712 713 { ARMADAXP_PEX3_BASE, 714 &armadaxp_pex3_io_bs_tag, 715 &armadaxp_pex3_mem_bs_tag, 716 &arm32_mvpex5_chipset, 717 ARMADAXP_TAG_PEX3_IO, 718 ARMADAXP_TAG_PEX3_MEM }, 719 720 { 0, 0, 0, 0, 0 }, 721 }; 722 723 for (i = 0; mvpex_tags[i].offset != 0; i++) { 724 if (mva->mva_offset != mvpex_tags[i].offset) 725 continue; 726 break; 727 } 728 if (mvpex_tags[i].offset == 0) 729 return; 730 mvpex_io_bs_tag = mvpex_tags[i].io_bs_tag; 731 mvpex_mem_bs_tag = mvpex_tags[i].mem_bs_tag; 732 arm32_mvpex_chipset = mvpex_tags[i].chipset; 733 iotag = mvpex_tags[i].iotag; 734 memtag = mvpex_tags[i].memtag; 735 break; 736 } 737 #endif 738 739 default: 740 return; 741 } 742 743 arm32_mvpex_chipset->pc_conf_v = device_private(dev); 744 arm32_mvpex_chipset->pc_intr_v = device_private(dev); 745 746 io_bs_tag = prop_data_create_data_nocopy( 747 mvpex_io_bs_tag, sizeof(struct bus_space)); 748 KASSERT(io_bs_tag != NULL); 749 prop_dictionary_set(dict, "io-bus-tag", io_bs_tag); 750 prop_object_release(io_bs_tag); 751 mem_bs_tag = prop_data_create_data_nocopy( 752 mvpex_mem_bs_tag, sizeof(struct bus_space)); 753 KASSERT(mem_bs_tag != NULL); 754 prop_dictionary_set(dict, "mem-bus-tag", mem_bs_tag); 755 prop_object_release(mem_bs_tag); 756 757 pc = prop_data_create_data_nocopy(arm32_mvpex_chipset, 758 sizeof(struct arm32_pci_chipset)); 759 KASSERT(pc != NULL); 760 prop_dictionary_set(dict, "pci-chipset", pc); 761 prop_object_release(pc); 762 763 marvell_startend_by_tag(iotag, &start, &end); 764 prop_dictionary_set_uint64(dict, "iostart", start); 765 prop_dictionary_set_uint64(dict, "ioend", end); 766 marvell_startend_by_tag(memtag, &start, &end); 767 prop_dictionary_set_uint64(dict, "memstart", start); 768 prop_dictionary_set_uint64(dict, "memend", end); 769 prop_dictionary_set_uint32(dict, 770 "cache-line-size", arm_dcache_align); 771 } 772 #endif 773 } 774 775 #if NGTPCI > 0 || NMVPEX > 0 776 static void 777 marvell_startend_by_tag(int tag, uint64_t *start, uint64_t *end) 778 { 779 uint32_t base, size; 780 int win; 781 782 win = mvsoc_target(tag, NULL, NULL, &base, &size); 783 if (size != 0) { 784 if (win < nremap) 785 *start = read_mlmbreg(MVSOC_MLMB_WRLR(win)) | 786 ((read_mlmbreg(MVSOC_MLMB_WRHR(win)) << 16) << 16); 787 else 788 *start = base; 789 *end = *start + size - 1; 790 } 791 } 792 #endif 793
Indexes created Thu Oct 02 07:10:07 GMT 2025