marvell_machdep.c revision 1.28
1 /* $NetBSD: marvell_machdep.c,v 1.28 2014/03/15 13:48:44 kiyohara Exp $ */ 2 /* 3 * Copyright (c) 2007, 2008, 2010 KIYOHARA Takashi 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 17 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 18 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 19 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 20 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 21 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 23 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 24 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 */ 27 #include <sys/cdefs.h> 28 __KERNEL_RCSID(0, "$NetBSD: marvell_machdep.c,v 1.28 2014/03/15 13:48:44 kiyohara Exp $"); 29 30 #include "opt_evbarm_boardtype.h" 31 #include "opt_ddb.h" 32 #include "opt_pci.h" 33 #include "opt_mvsoc.h" 34 #include "com.h" 35 #include "gtpci.h" 36 #include "mvpex.h" 37 38 #include <sys/param.h> 39 #include <sys/kernel.h> 40 #include <sys/reboot.h> 41 #include <sys/systm.h> 42 #include <sys/termios.h> 43 44 #include <prop/proplib.h> 45 46 #include <dev/cons.h> 47 #include <dev/md.h> 48 49 #include <dev/marvell/marvellreg.h> 50 #include <dev/marvell/marvellvar.h> 51 #include <dev/pci/pcireg.h> 52 #include <dev/pci/pcivar.h> 53 54 #include <machine/autoconf.h> 55 #include <machine/bootconfig.h> 56 #include <machine/pci_machdep.h> 57 58 #include <uvm/uvm_extern.h> 59 60 #include <arm/db_machdep.h> 61 #include <arm/undefined.h> 62 #include <arm/arm32/machdep.h> 63 64 #include <arm/marvell/mvsocreg.h> 65 #include <arm/marvell/mvsocvar.h> 66 #include <arm/marvell/orionreg.h> 67 #include <arm/marvell/kirkwoodreg.h> 68 #include <arm/marvell/mv78xx0reg.h> 69 #include <arm/marvell/armadaxpreg.h> 70 #include <arm/marvell/mvsocgppvar.h> 71 72 #include <evbarm/marvell/marvellreg.h> 73 #include <evbarm/marvell/marvellvar.h> 74 75 #include <ddb/db_extern.h> 76 #include <ddb/db_sym.h> 77 78 #include "ksyms.h" 79 80 81 /* Kernel text starts 2MB in from the bottom of the kernel address space. */ 82 #define KERNEL_TEXT_BASE (KERNEL_BASE + 0x00000000) 83 #define KERNEL_VM_BASE (KERNEL_BASE + 0x02000000) 84 85 /* 86 * The range 0xc2000000 - 0xdfffffff is available for kernel VM space 87 * Core-logic registers and I/O mappings occupy 0xfe000000 - 0xffffffff 88 */ 89 #define KERNEL_VM_SIZE 0x1e000000 90 91 BootConfig bootconfig; /* Boot config storage */ 92 static char bootargs[MAX_BOOT_STRING]; 93 char *boot_args = NULL; 94 95 extern int KERNEL_BASE_phys[]; 96 extern char _end[]; 97 98 /* 99 * Macros to translate between physical and virtual for a subset of the 100 * kernel address space. *Not* for general use. 101 */ 102 #define KERNEL_BASE_PHYS physical_start 103 #define KERN_VTOPHYS(va) \ 104 ((paddr_t)((vaddr_t)va - KERNEL_BASE + KERNEL_BASE_PHYS)) 105 #define KERN_PHYSTOV(pa) \ 106 ((vaddr_t)((paddr_t)pa - KERNEL_BASE_PHYS + KERNEL_BASE)) 107 108 109 #include "com.h" 110 #if NCOM > 0 111 #include <dev/ic/comreg.h> 112 #include <dev/ic/comvar.h> 113 #endif 114 115 #ifndef CONSPEED 116 #define CONSPEED B115200 /* It's a setting of the default of u-boot */ 117 #endif 118 #ifndef CONMODE 119 #define CONMODE ((TTYDEF_CFLAG & ~(CSIZE | CSTOPB | PARENB)) | CS8) /* 8N1 */ 120 121 int comcnspeed = CONSPEED; 122 int comcnmode = CONMODE; 123 #endif 124 125 #include "opt_kgdb.h" 126 #ifdef KGDB 127 #include <sys/kgdb.h> 128 #endif 129 130 static void marvell_device_register(device_t, void *); 131 #if NGTPCI > 0 || NMVPEX > 0 132 static void marvell_startend_by_tag(int, uint64_t *, uint64_t *); 133 #endif 134 135 #if defined(ORION) || defined(KIRKWOOD) || defined(MV78XX0) 136 static void 137 marvell_system_reset(void) 138 { 139 /* unmask soft reset */ 140 write_mlmbreg(MVSOC_MLMB_RSTOUTNMASKR, 141 MVSOC_MLMB_RSTOUTNMASKR_SOFTRSTOUTEN); 142 /* assert soft reset */ 143 write_mlmbreg(MVSOC_MLMB_SSRR, MVSOC_MLMB_SSRR_SYSTEMSOFTRST); 144 145 /* if we're still running, jump to the reset address */ 146 cpu_reset_address = 0; 147 cpu_reset_address_paddr = 0xffff0000; 148 cpu_reset(); 149 /*NOTREACHED*/ 150 } 151 #endif 152 153 #if defined(ARMADAXP) 154 static void 155 armadaxp_system_reset(void) 156 { 157 extern vaddr_t misc_base; 158 159 #define write_miscreg(r, v) (*(volatile uint32_t *)(misc_base + (r)) = (v)) 160 161 /* Unmask soft reset */ 162 write_miscreg(ARMADAXP_MISC_RSTOUTNMASKR, 163 ARMADAXP_MISC_RSTOUTNMASKR_GLOBALSOFTRSTOUTEN); 164 /* Assert soft reset */ 165 write_miscreg(ARMADAXP_MISC_SSRR, ARMADAXP_MISC_SSRR_GLOBALSOFTRST); 166 167 while (1); 168 169 /*NOTREACHED*/ 170 } 171 #endif 172 173 174 static inline 175 pd_entry_t * 176 read_ttb(void) 177 { 178 long ttb; 179 180 __asm volatile("mrc p15, 0, %0, c2, c0, 0" : "=r" (ttb)); 181 182 return (pd_entry_t *)(ttb & ~((1<<14)-1)); 183 } 184 185 /* 186 * Static device mappings. These peripheral registers are mapped at 187 * fixed virtual addresses very early in initarm() so that we can use 188 * them while booting the kernel, and stay at the same address 189 * throughout whole kernel's life time. 190 * 191 * We use this table twice; once with bootstrap page table, and once 192 * with kernel's page table which we build up in initarm(). 193 * 194 * Since we map these registers into the bootstrap page table using 195 * pmap_devmap_bootstrap() which calls pmap_map_chunk(), we map 196 * registers segment-aligned and segment-rounded in order to avoid 197 * using the 2nd page tables. 198 */ 199 #define _A(a) ((a) & ~L1_S_OFFSET) 200 #define _S(s) (((s) + L1_S_SIZE - 1) & ~(L1_S_SIZE-1)) 201 202 static struct pmap_devmap marvell_devmap[] = { 203 { 204 MARVELL_INTERREGS_VBASE, 205 _A(MARVELL_INTERREGS_PBASE), 206 _S(MARVELL_INTERREGS_SIZE), 207 VM_PROT_READ|VM_PROT_WRITE, 208 PTE_NOCACHE, 209 }, 210 211 { 0, 0, 0, 0, 0 } 212 }; 213 214 extern uint32_t *u_boot_args[]; 215 216 /* 217 * u_int initarm(...) 218 * 219 * Initial entry point on startup. This gets called before main() is 220 * entered. 221 * It should be responsible for setting up everything that must be 222 * in place when main is called. 223 * This includes 224 * Taking a copy of the boot configuration structure. 225 * Initialising the physical console so characters can be printed. 226 * Setting up page tables for the kernel 227 * Relocating the kernel to the bottom of physical memory 228 */ 229 u_int 230 initarm(void *arg) 231 { 232 uint32_t target, attr, base, size; 233 int cs, cs_end, memtag = 0, iotag = 0, window; 234 235 mvsoc_bootstrap(MARVELL_INTERREGS_VBASE); 236 237 /* 238 * Heads up ... Setup the CPU / MMU / TLB functions 239 */ 240 if (set_cpufuncs()) 241 panic("cpu not recognized!"); 242 243 /* map some peripheral registers */ 244 pmap_devmap_bootstrap((vaddr_t)read_ttb(), marvell_devmap); 245 246 /* 247 * U-Boot doesn't use the virtual memory. 248 * 249 * Physical Address Range Description 250 * ----------------------- ---------------------------------- 251 * 0x00000000 - 0x0fffffff SDRAM Bank 0 (max 256MB) 252 * 0x10000000 - 0x1fffffff SDRAM Bank 1 (max 256MB) 253 * 0x20000000 - 0x2fffffff SDRAM Bank 2 (max 256MB) 254 * 0x30000000 - 0x3fffffff SDRAM Bank 3 (max 256MB) 255 * 0xf1000000 - 0xf10fffff SoC Internal Registers 256 */ 257 258 cpu_domains((DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL*2)) | DOMAIN_CLIENT); 259 260 /* Get ready for splfoo() */ 261 switch (mvsoc_model()) { 262 #ifdef ORION 263 case MARVELL_ORION_1_88F1181: 264 case MARVELL_ORION_1_88F5082: 265 case MARVELL_ORION_1_88F5180N: 266 case MARVELL_ORION_1_88F5181: 267 case MARVELL_ORION_1_88F5182: 268 case MARVELL_ORION_1_88F6082: 269 case MARVELL_ORION_1_88F6183: 270 case MARVELL_ORION_1_88W8660: 271 case MARVELL_ORION_2_88F1281: 272 case MARVELL_ORION_2_88F5281: 273 cpu_reset_address = marvell_system_reset; 274 275 orion_intr_bootstrap(); 276 277 memtag = ORION_TAG_PEX0_MEM; 278 iotag = ORION_TAG_PEX0_IO; 279 nwindow = ORION_MLMB_NWINDOW; 280 nremap = ORION_MLMB_NREMAP; 281 282 cs = MARVELL_TAG_SDRAM_CS0; 283 cs_end = MARVELL_TAG_SDRAM_CS3; 284 285 orion_getclks(MARVELL_INTERREGS_VBASE); 286 break; 287 #endif /* ORION */ 288 289 #ifdef KIRKWOOD 290 case MARVELL_KIRKWOOD_88F6180: 291 case MARVELL_KIRKWOOD_88F6192: 292 case MARVELL_KIRKWOOD_88F6281: 293 case MARVELL_KIRKWOOD_88F6282: 294 cpu_reset_address = marvell_system_reset; 295 296 kirkwood_intr_bootstrap(); 297 298 memtag = KIRKWOOD_TAG_PEX_MEM; 299 iotag = KIRKWOOD_TAG_PEX_IO; 300 nwindow = KIRKWOOD_MLMB_NWINDOW; 301 nremap = KIRKWOOD_MLMB_NREMAP; 302 303 cs = MARVELL_TAG_SDRAM_CS0; 304 cs_end = MARVELL_TAG_SDRAM_CS3; 305 306 kirkwood_getclks(MARVELL_INTERREGS_VBASE); 307 mvsoc_clkgating = kirkwood_clkgating; 308 break; 309 #endif /* KIRKWOOD */ 310 311 #ifdef MV78XX0 312 case MARVELL_MV78XX0_MV78100: 313 case MARVELL_MV78XX0_MV78200: 314 cpu_reset_address = marvell_system_reset; 315 316 mv78xx0_intr_bootstrap(); 317 318 memtag = MV78XX0_TAG_PEX0_MEM; 319 iotag = MV78XX0_TAG_PEX0_IO; 320 nwindow = MV78XX0_MLMB_NWINDOW; 321 nremap = MV78XX0_MLMB_NREMAP; 322 323 cs = MARVELL_TAG_SDRAM_CS0; 324 cs_end = MARVELL_TAG_SDRAM_CS3; 325 326 mv78xx0_getclks(MARVELL_INTERREGS_VBASE); 327 break; 328 #endif /* MV78XX0 */ 329 330 #ifdef ARMADAXP 331 case MARVELL_ARMADAXP_MV78130: 332 case MARVELL_ARMADAXP_MV78160: 333 case MARVELL_ARMADAXP_MV78230: 334 case MARVELL_ARMADAXP_MV78260: 335 case MARVELL_ARMADAXP_MV78460: 336 cpu_reset_address = armadaxp_system_reset; 337 338 armadaxp_intr_bootstrap(MARVELL_INTERREGS_PBASE); 339 340 memtag = ARMADAXP_TAG_PEX00_MEM; 341 iotag = ARMADAXP_TAG_PEX00_IO; 342 nwindow = ARMADAXP_MLMB_NWINDOW; 343 nremap = ARMADAXP_MLMB_NREMAP; 344 345 cs = MARVELL_TAG_DDR3_CS0; 346 cs_end = MARVELL_TAG_DDR3_CS3; 347 348 extern vaddr_t misc_base; 349 misc_base = MARVELL_INTERREGS_VBASE + ARMADAXP_MISC_BASE; 350 armadaxp_getclks(); 351 mvsoc_clkgating = armadaxp_clkgating; 352 353 #ifdef L2CACHE_ENABLE 354 /* Initialize L2 Cache */ 355 { 356 extern int armadaxp_l2_init(bus_addr_t); 357 358 (void)armadaxp_l2_init(MARVELL_INTERREGS_PBASE); 359 } 360 #endif 361 362 #ifdef AURORA_IO_CACHE_COHERENCY 363 /* Initialize cache coherency */ 364 armadaxp_io_coherency_init(); 365 #endif 366 break; 367 368 case MARVELL_ARMADA370_MV6707: 369 case MARVELL_ARMADA370_MV6710: 370 case MARVELL_ARMADA370_MV6W11: 371 cpu_reset_address = armadaxp_system_reset; 372 373 armadaxp_intr_bootstrap(MARVELL_INTERREGS_PBASE); 374 375 memtag = ARMADAXP_TAG_PEX00_MEM; 376 iotag = ARMADAXP_TAG_PEX00_IO; 377 nwindow = ARMADAXP_MLMB_NWINDOW; 378 nremap = ARMADAXP_MLMB_NREMAP; 379 380 cs = MARVELL_TAG_DDR3_CS0; 381 cs_end = MARVELL_TAG_DDR3_CS3; 382 383 extern vaddr_t misc_base; 384 misc_base = MARVELL_INTERREGS_VBASE + ARMADAXP_MISC_BASE; 385 armada370_getclks(); 386 mvsoc_clkgating = armadaxp_clkgating; 387 388 #ifdef L2CACHE_ENABLE 389 /* Initialize L2 Cache */ 390 { 391 extern int armadaxp_l2_init(bus_addr_t); 392 393 (void)armadaxp_l2_init(MARVELL_INTERREGS_PBASE); 394 } 395 #endif 396 397 #ifdef AURORA_IO_CACHE_COHERENCY 398 /* Initialize cache coherency */ 399 armadaxp_io_coherency_init(); 400 #endif 401 break; 402 #endif /* ARMADAXP */ 403 404 default: 405 /* We can't output console here yet... */ 406 panic("unknown model...\n"); 407 408 /* NOTREACHED */ 409 } 410 411 consinit(); 412 413 /* Talk to the user */ 414 #ifndef EVBARM_BOARDTYPE 415 #define EVBARM_BOARDTYPE Marvell 416 #endif 417 #define BDSTR(s) _BDSTR(s) 418 #define _BDSTR(s) #s 419 printf("\nNetBSD/evbarm (" BDSTR(EVBARM_BOARDTYPE) ") booting ...\n"); 420 421 /* Reset PCI-Express space to window register. */ 422 window = mvsoc_target(memtag, &target, &attr, NULL, NULL); 423 write_mlmbreg(MVSOC_MLMB_WCR(window), 424 MVSOC_MLMB_WCR_WINEN | 425 MVSOC_MLMB_WCR_TARGET(target) | 426 MVSOC_MLMB_WCR_ATTR(attr) | 427 MVSOC_MLMB_WCR_SIZE(MARVELL_PEXMEM_SIZE)); 428 write_mlmbreg(MVSOC_MLMB_WBR(window), 429 MARVELL_PEXMEM_PBASE & MVSOC_MLMB_WBR_BASE_MASK); 430 #ifdef PCI_NETBSD_CONFIGURE 431 if (window < nremap) { 432 write_mlmbreg(MVSOC_MLMB_WRLR(window), 433 MARVELL_PEXMEM_PBASE & MVSOC_MLMB_WRLR_REMAP_MASK); 434 write_mlmbreg(MVSOC_MLMB_WRHR(window), 0); 435 } 436 #endif 437 window = mvsoc_target(iotag, &target, &attr, NULL, NULL); 438 write_mlmbreg(MVSOC_MLMB_WCR(window), 439 MVSOC_MLMB_WCR_WINEN | 440 MVSOC_MLMB_WCR_TARGET(target) | 441 MVSOC_MLMB_WCR_ATTR(attr) | 442 MVSOC_MLMB_WCR_SIZE(MARVELL_PEXIO_SIZE)); 443 write_mlmbreg(MVSOC_MLMB_WBR(window), 444 MARVELL_PEXIO_PBASE & MVSOC_MLMB_WBR_BASE_MASK); 445 #ifdef PCI_NETBSD_CONFIGURE 446 if (window < nremap) { 447 write_mlmbreg(MVSOC_MLMB_WRLR(window), 448 MARVELL_PEXIO_PBASE & MVSOC_MLMB_WRLR_REMAP_MASK); 449 write_mlmbreg(MVSOC_MLMB_WRHR(window), 0); 450 } 451 #endif 452 453 /* copy command line U-Boot gave us, if args is valid. */ 454 if (u_boot_args[3] != 0) /* XXXXX: need more check?? */ 455 strncpy(bootargs, (char *)u_boot_args[3], sizeof(bootargs)); 456 457 #ifdef VERBOSE_INIT_ARM 458 printf("initarm: Configuring system ...\n"); 459 #endif 460 461 bootconfig.dramblocks = 0; 462 paddr_t segment_end; 463 segment_end = physmem = 0; 464 for ( ; cs <= cs_end; cs++) { 465 mvsoc_target(cs, &target, &attr, &base, &size); 466 if (size == 0) 467 continue; 468 469 bootconfig.dram[bootconfig.dramblocks].address = base; 470 bootconfig.dram[bootconfig.dramblocks].pages = size / PAGE_SIZE; 471 472 if (base != segment_end) 473 panic("memory hole not support"); 474 475 segment_end += size; 476 physmem += size / PAGE_SIZE; 477 478 bootconfig.dramblocks++; 479 } 480 481 arm32_bootmem_init(0, segment_end, (uintptr_t) KERNEL_BASE_phys); 482 arm32_kernel_vm_init(KERNEL_VM_BASE, ARM_VECTORS_HIGH, 0, 483 marvell_devmap, false); 484 485 /* we've a specific device_register routine */ 486 evbarm_device_register = marvell_device_register; 487 488 /* parse bootargs from U-Boot */ 489 boot_args = bootargs; 490 parse_mi_bootargs(boot_args); 491 492 return initarm_common(KERNEL_VM_BASE, KERNEL_VM_SIZE, NULL, 0); 493 } 494 495 void 496 consinit(void) 497 { 498 static int consinit_called = 0; 499 500 if (consinit_called != 0) 501 return; 502 503 consinit_called = 1; 504 505 #if NCOM > 0 506 { 507 extern int mvuart_cnattach(bus_space_tag_t, bus_addr_t, int, 508 uint32_t, int); 509 510 if (mvuart_cnattach(&mvsoc_bs_tag, 511 MARVELL_INTERREGS_PBASE + MVSOC_COM0_BASE, 512 comcnspeed, mvTclk, comcnmode)) 513 panic("can't init serial console"); 514 } 515 #else 516 panic("serial console not configured"); 517 #endif 518 } 519 520 521 static void 522 marvell_device_register(device_t dev, void *aux) 523 { 524 prop_dictionary_t dict = device_properties(dev); 525 526 #if NCOM > 0 527 if (device_is_a(dev, "com") && 528 device_is_a(device_parent(dev), "mvsoc")) 529 prop_dictionary_set_uint32(dict, "frequency", mvTclk); 530 #endif 531 532 if (device_is_a(dev, "gtidmac")) 533 prop_dictionary_set_uint32(dict, 534 "dmb_speed", mvTclk * sizeof(uint32_t)); /* XXXXXX */ 535 536 #if NGTPCI > 0 && defined(ORION) 537 if (device_is_a(dev, "gtpci")) { 538 extern struct bus_space 539 orion_pci_io_bs_tag, orion_pci_mem_bs_tag; 540 extern struct arm32_pci_chipset arm32_gtpci_chipset; 541 542 prop_data_t io_bs_tag, mem_bs_tag, pc; 543 prop_array_t int2gpp; 544 prop_number_t gpp; 545 uint64_t start, end; 546 int i, j; 547 static struct { 548 const char *boardtype; 549 int pin[PCI_INTERRUPT_PIN_MAX]; 550 } hints[] = { 551 { "kuronas_x4", 552 { 11, PCI_INTERRUPT_PIN_NONE } }, 553 554 { NULL, 555 { PCI_INTERRUPT_PIN_NONE } }, 556 }; 557 558 arm32_gtpci_chipset.pc_conf_v = device_private(dev); 559 arm32_gtpci_chipset.pc_intr_v = device_private(dev); 560 561 io_bs_tag = prop_data_create_data_nocopy( 562 &orion_pci_io_bs_tag, sizeof(struct bus_space)); 563 KASSERT(io_bs_tag != NULL); 564 prop_dictionary_set(dict, "io-bus-tag", io_bs_tag); 565 prop_object_release(io_bs_tag); 566 mem_bs_tag = prop_data_create_data_nocopy( 567 &orion_pci_mem_bs_tag, sizeof(struct bus_space)); 568 KASSERT(mem_bs_tag != NULL); 569 prop_dictionary_set(dict, "mem-bus-tag", mem_bs_tag); 570 prop_object_release(mem_bs_tag); 571 572 pc = prop_data_create_data_nocopy(&arm32_gtpci_chipset, 573 sizeof(struct arm32_pci_chipset)); 574 KASSERT(pc != NULL); 575 prop_dictionary_set(dict, "pci-chipset", pc); 576 prop_object_release(pc); 577 578 marvell_startend_by_tag(ORION_TAG_PCI_IO, &start, &end); 579 prop_dictionary_set_uint64(dict, "iostart", start); 580 prop_dictionary_set_uint64(dict, "ioend", end); 581 marvell_startend_by_tag(ORION_TAG_PCI_MEM, &start, &end); 582 prop_dictionary_set_uint64(dict, "memstart", start); 583 prop_dictionary_set_uint64(dict, "memend", end); 584 prop_dictionary_set_uint32(dict, 585 "cache-line-size", arm_dcache_align); 586 587 /* Setup the hint for interrupt-pin. */ 588 #define BDSTR(s) _BDSTR(s) 589 #define _BDSTR(s) #s 590 #define THIS_BOARD(str) (strcmp(str, BDSTR(EVBARM_BOARDTYPE)) == 0) 591 for (i = 0; hints[i].boardtype != NULL; i++) 592 if (THIS_BOARD(hints[i].boardtype)) 593 break; 594 if (hints[i].boardtype == NULL) 595 return; 596 597 int2gpp = 598 prop_array_create_with_capacity(PCI_INTERRUPT_PIN_MAX + 1); 599 600 /* first set dummy */ 601 gpp = prop_number_create_integer(0); 602 prop_array_add(int2gpp, gpp); 603 prop_object_release(gpp); 604 605 for (j = 0; hints[i].pin[j] != PCI_INTERRUPT_PIN_NONE; j++) { 606 gpp = prop_number_create_integer(hints[i].pin[j]); 607 prop_array_add(int2gpp, gpp); 608 prop_object_release(gpp); 609 } 610 prop_dictionary_set(dict, "int2gpp", int2gpp); 611 } 612 #endif /* NGTPCI > 0 && defined(ORION) */ 613 614 #if NMVPEX > 0 615 if (device_is_a(dev, "mvpex")) { 616 #ifdef ORION 617 extern struct bus_space 618 orion_pex0_io_bs_tag, orion_pex0_mem_bs_tag, 619 orion_pex1_io_bs_tag, orion_pex1_mem_bs_tag; 620 #endif 621 #ifdef KIRKWOOD 622 extern struct bus_space 623 kirkwood_pex_io_bs_tag, kirkwood_pex_mem_bs_tag, 624 kirkwood_pex1_io_bs_tag, kirkwood_pex1_mem_bs_tag; 625 #endif 626 #ifdef ARMADAXP 627 extern struct bus_space 628 armadaxp_pex00_io_bs_tag, armadaxp_pex00_mem_bs_tag, 629 armadaxp_pex01_io_bs_tag, armadaxp_pex01_mem_bs_tag, 630 armadaxp_pex02_io_bs_tag, armadaxp_pex02_mem_bs_tag, 631 armadaxp_pex03_io_bs_tag, armadaxp_pex03_mem_bs_tag, 632 armadaxp_pex2_io_bs_tag, armadaxp_pex2_mem_bs_tag, 633 armadaxp_pex3_io_bs_tag, armadaxp_pex3_mem_bs_tag; 634 int i; 635 #endif 636 extern struct arm32_pci_chipset 637 arm32_mvpex0_chipset, arm32_mvpex1_chipset; 638 639 struct marvell_attach_args *mva = aux; 640 struct bus_space *mvpex_io_bs_tag, *mvpex_mem_bs_tag; 641 struct arm32_pci_chipset *arm32_mvpex_chipset; 642 prop_data_t io_bs_tag, mem_bs_tag, pc; 643 uint64_t start, end; 644 int iotag, memtag; 645 646 switch (mvsoc_model()) { 647 #ifdef ORION 648 case MARVELL_ORION_1_88F5180N: 649 case MARVELL_ORION_1_88F5181: 650 case MARVELL_ORION_1_88F5182: 651 case MARVELL_ORION_1_88W8660: 652 case MARVELL_ORION_2_88F5281: 653 if (mva->mva_offset == MVSOC_PEX_BASE) { 654 mvpex_io_bs_tag = &orion_pex0_io_bs_tag; 655 mvpex_mem_bs_tag = &orion_pex0_mem_bs_tag; 656 arm32_mvpex_chipset = &arm32_mvpex0_chipset; 657 iotag = ORION_TAG_PEX0_IO; 658 memtag = ORION_TAG_PEX0_MEM; 659 } else { 660 mvpex_io_bs_tag = &orion_pex1_io_bs_tag; 661 mvpex_mem_bs_tag = &orion_pex1_mem_bs_tag; 662 arm32_mvpex_chipset = &arm32_mvpex1_chipset; 663 iotag = ORION_TAG_PEX1_IO; 664 memtag = ORION_TAG_PEX1_MEM; 665 } 666 break; 667 #endif 668 669 #ifdef KIRKWOOD 670 case MARVELL_KIRKWOOD_88F6282: 671 if (mva->mva_offset != MVSOC_PEX_BASE) { 672 mvpex_io_bs_tag = &kirkwood_pex1_io_bs_tag; 673 mvpex_mem_bs_tag = &kirkwood_pex1_mem_bs_tag; 674 arm32_mvpex_chipset = &arm32_mvpex1_chipset; 675 iotag = KIRKWOOD_TAG_PEX1_IO; 676 memtag = KIRKWOOD_TAG_PEX1_MEM; 677 break; 678 } 679 680 /* FALLTHROUGH */ 681 682 case MARVELL_KIRKWOOD_88F6180: 683 case MARVELL_KIRKWOOD_88F6192: 684 case MARVELL_KIRKWOOD_88F6281: 685 mvpex_io_bs_tag = &kirkwood_pex_io_bs_tag; 686 mvpex_mem_bs_tag = &kirkwood_pex_mem_bs_tag; 687 arm32_mvpex_chipset = &arm32_mvpex0_chipset; 688 iotag = KIRKWOOD_TAG_PEX_IO; 689 memtag = KIRKWOOD_TAG_PEX_MEM; 690 break; 691 #endif 692 693 #ifdef ARMADAXP 694 case MARVELL_ARMADAXP_MV78130: 695 case MARVELL_ARMADAXP_MV78160: 696 case MARVELL_ARMADAXP_MV78230: 697 case MARVELL_ARMADAXP_MV78260: 698 case MARVELL_ARMADAXP_MV78460: 699 700 case MARVELL_ARMADA370_MV6707: 701 case MARVELL_ARMADA370_MV6710: 702 case MARVELL_ARMADA370_MV6W11: 703 { 704 extern struct arm32_pci_chipset 705 arm32_mvpex2_chipset, arm32_mvpex3_chipset, 706 arm32_mvpex4_chipset, arm32_mvpex5_chipset; 707 const struct { 708 bus_size_t offset; 709 struct bus_space *io_bs_tag; 710 struct bus_space *mem_bs_tag; 711 struct arm32_pci_chipset *chipset; 712 int iotag; 713 int memtag; 714 } mvpex_tags[] = { 715 { MVSOC_PEX_BASE, 716 &armadaxp_pex00_io_bs_tag, 717 &armadaxp_pex00_mem_bs_tag, 718 &arm32_mvpex0_chipset, 719 ARMADAXP_TAG_PEX00_IO, 720 ARMADAXP_TAG_PEX00_MEM }, 721 722 { ARMADAXP_PEX01_BASE, 723 &armadaxp_pex01_io_bs_tag, 724 &armadaxp_pex01_mem_bs_tag, 725 &arm32_mvpex1_chipset, 726 ARMADAXP_TAG_PEX01_IO, 727 ARMADAXP_TAG_PEX01_MEM }, 728 729 { ARMADAXP_PEX02_BASE, 730 &armadaxp_pex02_io_bs_tag, 731 &armadaxp_pex02_mem_bs_tag, 732 &arm32_mvpex2_chipset, 733 ARMADAXP_TAG_PEX02_IO, 734 ARMADAXP_TAG_PEX02_MEM }, 735 736 { ARMADAXP_PEX03_BASE, 737 &armadaxp_pex03_io_bs_tag, 738 &armadaxp_pex03_mem_bs_tag, 739 &arm32_mvpex3_chipset, 740 ARMADAXP_TAG_PEX03_IO, 741 ARMADAXP_TAG_PEX03_MEM }, 742 743 { ARMADAXP_PEX2_BASE, 744 &armadaxp_pex2_io_bs_tag, 745 &armadaxp_pex2_mem_bs_tag, 746 &arm32_mvpex4_chipset, 747 ARMADAXP_TAG_PEX2_IO, 748 ARMADAXP_TAG_PEX2_MEM }, 749 750 { ARMADAXP_PEX3_BASE, 751 &armadaxp_pex3_io_bs_tag, 752 &armadaxp_pex3_mem_bs_tag, 753 &arm32_mvpex5_chipset, 754 ARMADAXP_TAG_PEX3_IO, 755 ARMADAXP_TAG_PEX3_MEM }, 756 757 { 0, 0, 0, 0, 0 }, 758 }; 759 760 for (i = 0; mvpex_tags[i].offset != 0; i++) { 761 if (mva->mva_offset != mvpex_tags[i].offset) 762 continue; 763 break; 764 } 765 if (mvpex_tags[i].offset == 0) 766 return; 767 mvpex_io_bs_tag = mvpex_tags[i].io_bs_tag; 768 mvpex_mem_bs_tag = mvpex_tags[i].mem_bs_tag; 769 arm32_mvpex_chipset = mvpex_tags[i].chipset; 770 iotag = mvpex_tags[i].iotag; 771 memtag = mvpex_tags[i].memtag; 772 break; 773 } 774 #endif 775 776 default: 777 return; 778 } 779 780 arm32_mvpex_chipset->pc_conf_v = device_private(dev); 781 arm32_mvpex_chipset->pc_intr_v = device_private(dev); 782 783 io_bs_tag = prop_data_create_data_nocopy( 784 mvpex_io_bs_tag, sizeof(struct bus_space)); 785 KASSERT(io_bs_tag != NULL); 786 prop_dictionary_set(dict, "io-bus-tag", io_bs_tag); 787 prop_object_release(io_bs_tag); 788 mem_bs_tag = prop_data_create_data_nocopy( 789 mvpex_mem_bs_tag, sizeof(struct bus_space)); 790 KASSERT(mem_bs_tag != NULL); 791 prop_dictionary_set(dict, "mem-bus-tag", mem_bs_tag); 792 prop_object_release(mem_bs_tag); 793 794 pc = prop_data_create_data_nocopy(arm32_mvpex_chipset, 795 sizeof(struct arm32_pci_chipset)); 796 KASSERT(pc != NULL); 797 prop_dictionary_set(dict, "pci-chipset", pc); 798 prop_object_release(pc); 799 800 marvell_startend_by_tag(iotag, &start, &end); 801 prop_dictionary_set_uint64(dict, "iostart", start); 802 prop_dictionary_set_uint64(dict, "ioend", end); 803 marvell_startend_by_tag(memtag, &start, &end); 804 prop_dictionary_set_uint64(dict, "memstart", start); 805 prop_dictionary_set_uint64(dict, "memend", end); 806 prop_dictionary_set_uint32(dict, 807 "cache-line-size", arm_dcache_align); 808 } 809 #endif 810 } 811 812 #if NGTPCI > 0 || NMVPEX > 0 813 static void 814 marvell_startend_by_tag(int tag, uint64_t *start, uint64_t *end) 815 { 816 uint32_t base, size; 817 int win; 818 819 win = mvsoc_target(tag, NULL, NULL, &base, &size); 820 if (size != 0) { 821 if (win < nremap) 822 *start = read_mlmbreg(MVSOC_MLMB_WRLR(win)) | 823 ((read_mlmbreg(MVSOC_MLMB_WRHR(win)) << 16) << 16); 824 else 825 *start = base; 826 *end = *start + size - 1; 827 } 828 } 829 #endif 830
Indexes created Thu Oct 02 01:09:59 GMT 2025