marvell_machdep.c revision 1.30
1 /* $NetBSD: marvell_machdep.c,v 1.30 2014/08/30 13:19:52 kiyohara Exp $ */ 2 /* 3 * Copyright (c) 2007, 2008, 2010 KIYOHARA Takashi 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 17 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 18 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 19 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 20 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 21 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 23 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 24 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 */ 27 #include <sys/cdefs.h> 28 __KERNEL_RCSID(0, "$NetBSD: marvell_machdep.c,v 1.30 2014/08/30 13:19:52 kiyohara Exp $"); 29 30 #include "opt_evbarm_boardtype.h" 31 #include "opt_ddb.h" 32 #include "opt_pci.h" 33 #include "opt_mvsoc.h" 34 #include "com.h" 35 #include "gtpci.h" 36 #include "mvpex.h" 37 38 #include <sys/param.h> 39 #include <sys/kernel.h> 40 #include <sys/reboot.h> 41 #include <sys/systm.h> 42 #include <sys/termios.h> 43 44 #include <prop/proplib.h> 45 46 #include <dev/cons.h> 47 #include <dev/md.h> 48 49 #include <dev/marvell/marvellreg.h> 50 #include <dev/marvell/marvellvar.h> 51 #include <dev/pci/pcireg.h> 52 #include <dev/pci/pcivar.h> 53 54 #include <machine/autoconf.h> 55 #include <machine/bootconfig.h> 56 #include <machine/pci_machdep.h> 57 58 #include <uvm/uvm_extern.h> 59 60 #include <arm/db_machdep.h> 61 #include <arm/undefined.h> 62 #include <arm/arm32/machdep.h> 63 64 #include <arm/marvell/mvsocreg.h> 65 #include <arm/marvell/mvsocvar.h> 66 #include <arm/marvell/orionreg.h> 67 #include <arm/marvell/kirkwoodreg.h> 68 #include <arm/marvell/mv78xx0reg.h> 69 #include <arm/marvell/armadaxpreg.h> 70 #include <arm/marvell/mvsocgppvar.h> 71 72 #include <evbarm/marvell/marvellreg.h> 73 #include <evbarm/marvell/marvellvar.h> 74 75 #include <ddb/db_extern.h> 76 #include <ddb/db_sym.h> 77 78 #include "ksyms.h" 79 80 81 /* 82 * The range 0xc2000000 - 0xdfffffff is available for kernel VM space 83 * Core-logic registers and I/O mappings occupy 0xfe000000 - 0xffffffff 84 */ 85 #if (KERNEL_BASE & 0xf0000000) == 0x80000000 86 #define KERNEL_VM_BASE (KERNEL_BASE + 0x42000000) 87 #else 88 #define KERNEL_VM_BASE (KERNEL_BASE + 0x02000000) 89 #endif 90 #define KERNEL_VM_SIZE 0x1e000000 91 92 BootConfig bootconfig; /* Boot config storage */ 93 static char bootargs[MAX_BOOT_STRING]; 94 char *boot_args = NULL; 95 96 extern int KERNEL_BASE_phys[]; 97 extern char _end[]; 98 99 /* 100 * Macros to translate between physical and virtual for a subset of the 101 * kernel address space. *Not* for general use. 102 */ 103 #define KERNEL_BASE_PHYS physical_start 104 105 106 #include "com.h" 107 #if NCOM > 0 108 #include <dev/ic/comreg.h> 109 #include <dev/ic/comvar.h> 110 #endif 111 112 #ifndef CONSPEED 113 #define CONSPEED B115200 /* It's a setting of the default of u-boot */ 114 #endif 115 #ifndef CONMODE 116 #define CONMODE ((TTYDEF_CFLAG & ~(CSIZE | CSTOPB | PARENB)) | CS8) /* 8N1 */ 117 118 int comcnspeed = CONSPEED; 119 int comcnmode = CONMODE; 120 #endif 121 122 #include "opt_kgdb.h" 123 #ifdef KGDB 124 #include <sys/kgdb.h> 125 #endif 126 127 static void marvell_device_register(device_t, void *); 128 #if NGTPCI > 0 || NMVPEX > 0 129 static void marvell_startend_by_tag(int, uint64_t *, uint64_t *); 130 #endif 131 132 #if defined(ORION) || defined(KIRKWOOD) || defined(MV78XX0) 133 static void 134 marvell_system_reset(void) 135 { 136 /* unmask soft reset */ 137 write_mlmbreg(MVSOC_MLMB_RSTOUTNMASKR, 138 MVSOC_MLMB_RSTOUTNMASKR_SOFTRSTOUTEN); 139 /* assert soft reset */ 140 write_mlmbreg(MVSOC_MLMB_SSRR, MVSOC_MLMB_SSRR_SYSTEMSOFTRST); 141 142 /* if we're still running, jump to the reset address */ 143 cpu_reset_address = 0; 144 cpu_reset_address_paddr = 0xffff0000; 145 cpu_reset(); 146 /*NOTREACHED*/ 147 } 148 #endif 149 150 #if defined(ARMADAXP) 151 static void 152 armadaxp_system_reset(void) 153 { 154 extern vaddr_t misc_base; 155 156 #define write_miscreg(r, v) (*(volatile uint32_t *)(misc_base + (r)) = (v)) 157 158 /* Unmask soft reset */ 159 write_miscreg(ARMADAXP_MISC_RSTOUTNMASKR, 160 ARMADAXP_MISC_RSTOUTNMASKR_GLOBALSOFTRSTOUTEN); 161 /* Assert soft reset */ 162 write_miscreg(ARMADAXP_MISC_SSRR, ARMADAXP_MISC_SSRR_GLOBALSOFTRST); 163 164 while (1); 165 166 /*NOTREACHED*/ 167 } 168 #endif 169 170 171 static inline pd_entry_t * 172 read_ttb(void) 173 { 174 175 return (pd_entry_t *)(armreg_ttbr_read() & ~((1<<14)-1)); 176 } 177 178 /* 179 * Static device mappings. These peripheral registers are mapped at 180 * fixed virtual addresses very early in initarm() so that we can use 181 * them while booting the kernel, and stay at the same address 182 * throughout whole kernel's life time. 183 * 184 * We use this table twice; once with bootstrap page table, and once 185 * with kernel's page table which we build up in initarm(). 186 * 187 * Since we map these registers into the bootstrap page table using 188 * pmap_devmap_bootstrap() which calls pmap_map_chunk(), we map 189 * registers segment-aligned and segment-rounded in order to avoid 190 * using the 2nd page tables. 191 */ 192 #define _A(a) ((a) & ~L1_S_OFFSET) 193 #define _S(s) (((s) + L1_S_SIZE - 1) & ~(L1_S_SIZE-1)) 194 195 static struct pmap_devmap marvell_devmap[] = { 196 { 197 MARVELL_INTERREGS_VBASE, 198 _A(MARVELL_INTERREGS_PBASE), 199 _S(MARVELL_INTERREGS_SIZE), 200 VM_PROT_READ|VM_PROT_WRITE, 201 PTE_NOCACHE, 202 }, 203 204 { 0, 0, 0, 0, 0 } 205 }; 206 207 extern uint32_t *u_boot_args[]; 208 209 /* 210 * u_int initarm(...) 211 * 212 * Initial entry point on startup. This gets called before main() is 213 * entered. 214 * It should be responsible for setting up everything that must be 215 * in place when main is called. 216 * This includes 217 * Taking a copy of the boot configuration structure. 218 * Initialising the physical console so characters can be printed. 219 * Setting up page tables for the kernel 220 * Relocating the kernel to the bottom of physical memory 221 */ 222 u_int 223 initarm(void *arg) 224 { 225 uint32_t target, attr, base, size; 226 int cs, cs_end, memtag = 0, iotag = 0, window; 227 228 mvsoc_bootstrap(MARVELL_INTERREGS_VBASE); 229 230 /* 231 * Heads up ... Setup the CPU / MMU / TLB functions 232 */ 233 if (set_cpufuncs()) 234 panic("cpu not recognized!"); 235 236 /* map some peripheral registers */ 237 pmap_devmap_bootstrap((vaddr_t)read_ttb(), marvell_devmap); 238 239 /* 240 * U-Boot doesn't use the virtual memory. 241 * 242 * Physical Address Range Description 243 * ----------------------- ---------------------------------- 244 * 0x00000000 - 0x0fffffff SDRAM Bank 0 (max 256MB) 245 * 0x10000000 - 0x1fffffff SDRAM Bank 1 (max 256MB) 246 * 0x20000000 - 0x2fffffff SDRAM Bank 2 (max 256MB) 247 * 0x30000000 - 0x3fffffff SDRAM Bank 3 (max 256MB) 248 * 0xf1000000 - 0xf10fffff SoC Internal Registers 249 */ 250 251 cpu_domains((DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL*2)) | DOMAIN_CLIENT); 252 253 /* Get ready for splfoo() */ 254 switch (mvsoc_model()) { 255 #ifdef ORION 256 case MARVELL_ORION_1_88F1181: 257 case MARVELL_ORION_1_88F5082: 258 case MARVELL_ORION_1_88F5180N: 259 case MARVELL_ORION_1_88F5181: 260 case MARVELL_ORION_1_88F5182: 261 case MARVELL_ORION_1_88F6082: 262 case MARVELL_ORION_1_88F6183: 263 case MARVELL_ORION_1_88W8660: 264 case MARVELL_ORION_2_88F1281: 265 case MARVELL_ORION_2_88F5281: 266 cpu_reset_address = marvell_system_reset; 267 268 orion_intr_bootstrap(); 269 270 memtag = ORION_TAG_PEX0_MEM; 271 iotag = ORION_TAG_PEX0_IO; 272 nwindow = ORION_MLMB_NWINDOW; 273 nremap = ORION_MLMB_NREMAP; 274 275 cs = MARVELL_TAG_SDRAM_CS0; 276 cs_end = MARVELL_TAG_SDRAM_CS3; 277 278 orion_getclks(MARVELL_INTERREGS_VBASE); 279 break; 280 #endif /* ORION */ 281 282 #ifdef KIRKWOOD 283 case MARVELL_KIRKWOOD_88F6180: 284 case MARVELL_KIRKWOOD_88F6192: 285 case MARVELL_KIRKWOOD_88F6281: 286 case MARVELL_KIRKWOOD_88F6282: 287 cpu_reset_address = marvell_system_reset; 288 289 kirkwood_intr_bootstrap(); 290 291 memtag = KIRKWOOD_TAG_PEX_MEM; 292 iotag = KIRKWOOD_TAG_PEX_IO; 293 nwindow = KIRKWOOD_MLMB_NWINDOW; 294 nremap = KIRKWOOD_MLMB_NREMAP; 295 296 cs = MARVELL_TAG_SDRAM_CS0; 297 cs_end = MARVELL_TAG_SDRAM_CS3; 298 299 kirkwood_getclks(MARVELL_INTERREGS_VBASE); 300 mvsoc_clkgating = kirkwood_clkgating; 301 break; 302 #endif /* KIRKWOOD */ 303 304 #ifdef MV78XX0 305 case MARVELL_MV78XX0_MV78100: 306 case MARVELL_MV78XX0_MV78200: 307 cpu_reset_address = marvell_system_reset; 308 309 mv78xx0_intr_bootstrap(); 310 311 memtag = MV78XX0_TAG_PEX0_MEM; 312 iotag = MV78XX0_TAG_PEX0_IO; 313 nwindow = MV78XX0_MLMB_NWINDOW; 314 nremap = MV78XX0_MLMB_NREMAP; 315 316 cs = MARVELL_TAG_SDRAM_CS0; 317 cs_end = MARVELL_TAG_SDRAM_CS3; 318 319 mv78xx0_getclks(MARVELL_INTERREGS_VBASE); 320 break; 321 #endif /* MV78XX0 */ 322 323 #ifdef ARMADAXP 324 case MARVELL_ARMADAXP_MV78130: 325 case MARVELL_ARMADAXP_MV78160: 326 case MARVELL_ARMADAXP_MV78230: 327 case MARVELL_ARMADAXP_MV78260: 328 case MARVELL_ARMADAXP_MV78460: 329 cpu_reset_address = armadaxp_system_reset; 330 331 armadaxp_intr_bootstrap(MARVELL_INTERREGS_PBASE); 332 333 memtag = ARMADAXP_TAG_PEX00_MEM; 334 iotag = ARMADAXP_TAG_PEX00_IO; 335 nwindow = ARMADAXP_MLMB_NWINDOW; 336 nremap = ARMADAXP_MLMB_NREMAP; 337 338 cs = MARVELL_TAG_DDR3_CS0; 339 cs_end = MARVELL_TAG_DDR3_CS3; 340 341 extern vaddr_t misc_base; 342 misc_base = MARVELL_INTERREGS_VBASE + ARMADAXP_MISC_BASE; 343 armadaxp_getclks(); 344 mvsoc_clkgating = armadaxp_clkgating; 345 346 #ifdef L2CACHE_ENABLE 347 /* Initialize L2 Cache */ 348 { 349 extern int armadaxp_l2_init(bus_addr_t); 350 351 (void)armadaxp_l2_init(MARVELL_INTERREGS_PBASE); 352 } 353 #endif 354 355 #ifdef AURORA_IO_CACHE_COHERENCY 356 /* Initialize cache coherency */ 357 armadaxp_io_coherency_init(); 358 #endif 359 break; 360 361 case MARVELL_ARMADA370_MV6707: 362 case MARVELL_ARMADA370_MV6710: 363 case MARVELL_ARMADA370_MV6W11: 364 cpu_reset_address = armadaxp_system_reset; 365 366 armadaxp_intr_bootstrap(MARVELL_INTERREGS_PBASE); 367 368 memtag = ARMADAXP_TAG_PEX00_MEM; 369 iotag = ARMADAXP_TAG_PEX00_IO; 370 nwindow = ARMADAXP_MLMB_NWINDOW; 371 nremap = ARMADAXP_MLMB_NREMAP; 372 373 cs = MARVELL_TAG_DDR3_CS0; 374 cs_end = MARVELL_TAG_DDR3_CS3; 375 376 extern vaddr_t misc_base; 377 misc_base = MARVELL_INTERREGS_VBASE + ARMADAXP_MISC_BASE; 378 armada370_getclks(); 379 mvsoc_clkgating = armadaxp_clkgating; 380 381 #ifdef L2CACHE_ENABLE 382 /* Initialize L2 Cache */ 383 { 384 extern int armadaxp_l2_init(bus_addr_t); 385 386 (void)armadaxp_l2_init(MARVELL_INTERREGS_PBASE); 387 } 388 #endif 389 390 #ifdef AURORA_IO_CACHE_COHERENCY 391 /* Initialize cache coherency */ 392 armadaxp_io_coherency_init(); 393 #endif 394 break; 395 #endif /* ARMADAXP */ 396 397 default: 398 /* We can't output console here yet... */ 399 panic("unknown model...\n"); 400 401 /* NOTREACHED */ 402 } 403 404 consinit(); 405 406 /* Talk to the user */ 407 #ifndef EVBARM_BOARDTYPE 408 #define EVBARM_BOARDTYPE Marvell 409 #endif 410 #define BDSTR(s) _BDSTR(s) 411 #define _BDSTR(s) #s 412 printf("\nNetBSD/evbarm (" BDSTR(EVBARM_BOARDTYPE) ") booting ...\n"); 413 414 /* Reset PCI-Express space to window register. */ 415 window = mvsoc_target(memtag, &target, &attr, NULL, NULL); 416 write_mlmbreg(MVSOC_MLMB_WCR(window), 417 MVSOC_MLMB_WCR_WINEN | 418 MVSOC_MLMB_WCR_TARGET(target) | 419 MVSOC_MLMB_WCR_ATTR(attr) | 420 MVSOC_MLMB_WCR_SIZE(MARVELL_PEXMEM_SIZE)); 421 write_mlmbreg(MVSOC_MLMB_WBR(window), 422 MARVELL_PEXMEM_PBASE & MVSOC_MLMB_WBR_BASE_MASK); 423 #ifdef PCI_NETBSD_CONFIGURE 424 if (window < nremap) { 425 write_mlmbreg(MVSOC_MLMB_WRLR(window), 426 MARVELL_PEXMEM_PBASE & MVSOC_MLMB_WRLR_REMAP_MASK); 427 write_mlmbreg(MVSOC_MLMB_WRHR(window), 0); 428 } 429 #endif 430 window = mvsoc_target(iotag, &target, &attr, NULL, NULL); 431 write_mlmbreg(MVSOC_MLMB_WCR(window), 432 MVSOC_MLMB_WCR_WINEN | 433 MVSOC_MLMB_WCR_TARGET(target) | 434 MVSOC_MLMB_WCR_ATTR(attr) | 435 MVSOC_MLMB_WCR_SIZE(MARVELL_PEXIO_SIZE)); 436 write_mlmbreg(MVSOC_MLMB_WBR(window), 437 MARVELL_PEXIO_PBASE & MVSOC_MLMB_WBR_BASE_MASK); 438 #ifdef PCI_NETBSD_CONFIGURE 439 if (window < nremap) { 440 write_mlmbreg(MVSOC_MLMB_WRLR(window), 441 MARVELL_PEXIO_PBASE & MVSOC_MLMB_WRLR_REMAP_MASK); 442 write_mlmbreg(MVSOC_MLMB_WRHR(window), 0); 443 } 444 #endif 445 446 /* copy command line U-Boot gave us, if args is valid. */ 447 if (u_boot_args[3] != 0) /* XXXXX: need more check?? */ 448 strncpy(bootargs, (char *)u_boot_args[3], sizeof(bootargs)); 449 450 #ifdef VERBOSE_INIT_ARM 451 printf("initarm: Configuring system ...\n"); 452 #endif 453 454 bootconfig.dramblocks = 0; 455 paddr_t segment_end; 456 segment_end = physmem = 0; 457 for ( ; cs <= cs_end; cs++) { 458 mvsoc_target(cs, &target, &attr, &base, &size); 459 if (size == 0) 460 continue; 461 462 bootconfig.dram[bootconfig.dramblocks].address = base; 463 bootconfig.dram[bootconfig.dramblocks].pages = size / PAGE_SIZE; 464 465 if (base != segment_end) 466 panic("memory hole not support"); 467 468 segment_end += size; 469 physmem += size / PAGE_SIZE; 470 471 bootconfig.dramblocks++; 472 } 473 474 #ifdef __HAVE_MM_MD_DIRECT_MAPPED_PHYS 475 const bool mapallmem_p = true; 476 #else 477 const bool mapallmem_p = false; 478 #endif 479 480 arm32_bootmem_init(0, segment_end, (uintptr_t) KERNEL_BASE_phys); 481 arm32_kernel_vm_init(KERNEL_VM_BASE, ARM_VECTORS_HIGH, 0, 482 marvell_devmap, mapallmem_p); 483 484 /* we've a specific device_register routine */ 485 evbarm_device_register = marvell_device_register; 486 487 /* parse bootargs from U-Boot */ 488 boot_args = bootargs; 489 parse_mi_bootargs(boot_args); 490 491 return initarm_common(KERNEL_VM_BASE, KERNEL_VM_SIZE, NULL, 0); 492 } 493 494 void 495 consinit(void) 496 { 497 static int consinit_called = 0; 498 499 if (consinit_called != 0) 500 return; 501 502 consinit_called = 1; 503 504 #if NCOM > 0 505 { 506 extern int mvuart_cnattach(bus_space_tag_t, bus_addr_t, int, 507 uint32_t, int); 508 509 if (mvuart_cnattach(&mvsoc_bs_tag, 510 MARVELL_INTERREGS_PBASE + MVSOC_COM0_BASE, 511 comcnspeed, mvTclk, comcnmode)) 512 panic("can't init serial console"); 513 } 514 #else 515 panic("serial console not configured"); 516 #endif 517 } 518 519 520 static void 521 marvell_device_register(device_t dev, void *aux) 522 { 523 prop_dictionary_t dict = device_properties(dev); 524 525 #if NCOM > 0 526 if (device_is_a(dev, "com") && 527 device_is_a(device_parent(dev), "mvsoc")) 528 prop_dictionary_set_uint32(dict, "frequency", mvTclk); 529 #endif 530 531 if (device_is_a(dev, "gtidmac")) 532 prop_dictionary_set_uint32(dict, 533 "dmb_speed", mvTclk * sizeof(uint32_t)); /* XXXXXX */ 534 535 #if NGTPCI > 0 && defined(ORION) 536 if (device_is_a(dev, "gtpci")) { 537 extern struct bus_space 538 orion_pci_io_bs_tag, orion_pci_mem_bs_tag; 539 extern struct arm32_pci_chipset arm32_gtpci_chipset; 540 541 prop_data_t io_bs_tag, mem_bs_tag, pc; 542 prop_array_t int2gpp; 543 prop_number_t gpp; 544 uint64_t start, end; 545 int i, j; 546 static struct { 547 const char *boardtype; 548 int pin[PCI_INTERRUPT_PIN_MAX]; 549 } hints[] = { 550 { "kuronas_x4", 551 { 11, PCI_INTERRUPT_PIN_NONE } }, 552 553 { NULL, 554 { PCI_INTERRUPT_PIN_NONE } }, 555 }; 556 557 arm32_gtpci_chipset.pc_conf_v = device_private(dev); 558 arm32_gtpci_chipset.pc_intr_v = device_private(dev); 559 560 io_bs_tag = prop_data_create_data_nocopy( 561 &orion_pci_io_bs_tag, sizeof(struct bus_space)); 562 KASSERT(io_bs_tag != NULL); 563 prop_dictionary_set(dict, "io-bus-tag", io_bs_tag); 564 prop_object_release(io_bs_tag); 565 mem_bs_tag = prop_data_create_data_nocopy( 566 &orion_pci_mem_bs_tag, sizeof(struct bus_space)); 567 KASSERT(mem_bs_tag != NULL); 568 prop_dictionary_set(dict, "mem-bus-tag", mem_bs_tag); 569 prop_object_release(mem_bs_tag); 570 571 pc = prop_data_create_data_nocopy(&arm32_gtpci_chipset, 572 sizeof(struct arm32_pci_chipset)); 573 KASSERT(pc != NULL); 574 prop_dictionary_set(dict, "pci-chipset", pc); 575 prop_object_release(pc); 576 577 marvell_startend_by_tag(ORION_TAG_PCI_IO, &start, &end); 578 prop_dictionary_set_uint64(dict, "iostart", start); 579 prop_dictionary_set_uint64(dict, "ioend", end); 580 marvell_startend_by_tag(ORION_TAG_PCI_MEM, &start, &end); 581 prop_dictionary_set_uint64(dict, "memstart", start); 582 prop_dictionary_set_uint64(dict, "memend", end); 583 prop_dictionary_set_uint32(dict, 584 "cache-line-size", arm_dcache_align); 585 586 /* Setup the hint for interrupt-pin. */ 587 #define BDSTR(s) _BDSTR(s) 588 #define _BDSTR(s) #s 589 #define THIS_BOARD(str) (strcmp(str, BDSTR(EVBARM_BOARDTYPE)) == 0) 590 for (i = 0; hints[i].boardtype != NULL; i++) 591 if (THIS_BOARD(hints[i].boardtype)) 592 break; 593 if (hints[i].boardtype == NULL) 594 return; 595 596 int2gpp = 597 prop_array_create_with_capacity(PCI_INTERRUPT_PIN_MAX + 1); 598 599 /* first set dummy */ 600 gpp = prop_number_create_integer(0); 601 prop_array_add(int2gpp, gpp); 602 prop_object_release(gpp); 603 604 for (j = 0; hints[i].pin[j] != PCI_INTERRUPT_PIN_NONE; j++) { 605 gpp = prop_number_create_integer(hints[i].pin[j]); 606 prop_array_add(int2gpp, gpp); 607 prop_object_release(gpp); 608 } 609 prop_dictionary_set(dict, "int2gpp", int2gpp); 610 } 611 #endif /* NGTPCI > 0 && defined(ORION) */ 612 613 #if NMVPEX > 0 614 if (device_is_a(dev, "mvpex")) { 615 #ifdef ORION 616 extern struct bus_space 617 orion_pex0_io_bs_tag, orion_pex0_mem_bs_tag, 618 orion_pex1_io_bs_tag, orion_pex1_mem_bs_tag; 619 #endif 620 #ifdef KIRKWOOD 621 extern struct bus_space 622 kirkwood_pex_io_bs_tag, kirkwood_pex_mem_bs_tag, 623 kirkwood_pex1_io_bs_tag, kirkwood_pex1_mem_bs_tag; 624 #endif 625 #ifdef ARMADAXP 626 extern struct bus_space 627 armadaxp_pex00_io_bs_tag, armadaxp_pex00_mem_bs_tag, 628 armadaxp_pex01_io_bs_tag, armadaxp_pex01_mem_bs_tag, 629 armadaxp_pex02_io_bs_tag, armadaxp_pex02_mem_bs_tag, 630 armadaxp_pex03_io_bs_tag, armadaxp_pex03_mem_bs_tag, 631 armadaxp_pex2_io_bs_tag, armadaxp_pex2_mem_bs_tag, 632 armadaxp_pex3_io_bs_tag, armadaxp_pex3_mem_bs_tag; 633 int i; 634 #endif 635 extern struct arm32_pci_chipset 636 arm32_mvpex0_chipset, arm32_mvpex1_chipset; 637 638 struct marvell_attach_args *mva = aux; 639 struct bus_space *mvpex_io_bs_tag, *mvpex_mem_bs_tag; 640 struct arm32_pci_chipset *arm32_mvpex_chipset; 641 prop_data_t io_bs_tag, mem_bs_tag, pc; 642 uint64_t start, end; 643 int iotag, memtag; 644 645 switch (mvsoc_model()) { 646 #ifdef ORION 647 case MARVELL_ORION_1_88F5180N: 648 case MARVELL_ORION_1_88F5181: 649 case MARVELL_ORION_1_88F5182: 650 case MARVELL_ORION_1_88W8660: 651 case MARVELL_ORION_2_88F5281: 652 if (mva->mva_offset == MVSOC_PEX_BASE) { 653 mvpex_io_bs_tag = &orion_pex0_io_bs_tag; 654 mvpex_mem_bs_tag = &orion_pex0_mem_bs_tag; 655 arm32_mvpex_chipset = &arm32_mvpex0_chipset; 656 iotag = ORION_TAG_PEX0_IO; 657 memtag = ORION_TAG_PEX0_MEM; 658 } else { 659 mvpex_io_bs_tag = &orion_pex1_io_bs_tag; 660 mvpex_mem_bs_tag = &orion_pex1_mem_bs_tag; 661 arm32_mvpex_chipset = &arm32_mvpex1_chipset; 662 iotag = ORION_TAG_PEX1_IO; 663 memtag = ORION_TAG_PEX1_MEM; 664 } 665 break; 666 #endif 667 668 #ifdef KIRKWOOD 669 case MARVELL_KIRKWOOD_88F6282: 670 if (mva->mva_offset != MVSOC_PEX_BASE) { 671 mvpex_io_bs_tag = &kirkwood_pex1_io_bs_tag; 672 mvpex_mem_bs_tag = &kirkwood_pex1_mem_bs_tag; 673 arm32_mvpex_chipset = &arm32_mvpex1_chipset; 674 iotag = KIRKWOOD_TAG_PEX1_IO; 675 memtag = KIRKWOOD_TAG_PEX1_MEM; 676 break; 677 } 678 679 /* FALLTHROUGH */ 680 681 case MARVELL_KIRKWOOD_88F6180: 682 case MARVELL_KIRKWOOD_88F6192: 683 case MARVELL_KIRKWOOD_88F6281: 684 mvpex_io_bs_tag = &kirkwood_pex_io_bs_tag; 685 mvpex_mem_bs_tag = &kirkwood_pex_mem_bs_tag; 686 arm32_mvpex_chipset = &arm32_mvpex0_chipset; 687 iotag = KIRKWOOD_TAG_PEX_IO; 688 memtag = KIRKWOOD_TAG_PEX_MEM; 689 break; 690 #endif 691 692 #ifdef ARMADAXP 693 case MARVELL_ARMADAXP_MV78130: 694 case MARVELL_ARMADAXP_MV78160: 695 case MARVELL_ARMADAXP_MV78230: 696 case MARVELL_ARMADAXP_MV78260: 697 case MARVELL_ARMADAXP_MV78460: 698 699 case MARVELL_ARMADA370_MV6707: 700 case MARVELL_ARMADA370_MV6710: 701 case MARVELL_ARMADA370_MV6W11: 702 { 703 extern struct arm32_pci_chipset 704 arm32_mvpex2_chipset, arm32_mvpex3_chipset, 705 arm32_mvpex4_chipset, arm32_mvpex5_chipset; 706 const struct { 707 bus_size_t offset; 708 struct bus_space *io_bs_tag; 709 struct bus_space *mem_bs_tag; 710 struct arm32_pci_chipset *chipset; 711 int iotag; 712 int memtag; 713 } mvpex_tags[] = { 714 { MVSOC_PEX_BASE, 715 &armadaxp_pex00_io_bs_tag, 716 &armadaxp_pex00_mem_bs_tag, 717 &arm32_mvpex0_chipset, 718 ARMADAXP_TAG_PEX00_IO, 719 ARMADAXP_TAG_PEX00_MEM }, 720 721 { ARMADAXP_PEX01_BASE, 722 &armadaxp_pex01_io_bs_tag, 723 &armadaxp_pex01_mem_bs_tag, 724 &arm32_mvpex1_chipset, 725 ARMADAXP_TAG_PEX01_IO, 726 ARMADAXP_TAG_PEX01_MEM }, 727 728 { ARMADAXP_PEX02_BASE, 729 &armadaxp_pex02_io_bs_tag, 730 &armadaxp_pex02_mem_bs_tag, 731 &arm32_mvpex2_chipset, 732 ARMADAXP_TAG_PEX02_IO, 733 ARMADAXP_TAG_PEX02_MEM }, 734 735 { ARMADAXP_PEX03_BASE, 736 &armadaxp_pex03_io_bs_tag, 737 &armadaxp_pex03_mem_bs_tag, 738 &arm32_mvpex3_chipset, 739 ARMADAXP_TAG_PEX03_IO, 740 ARMADAXP_TAG_PEX03_MEM }, 741 742 { ARMADAXP_PEX2_BASE, 743 &armadaxp_pex2_io_bs_tag, 744 &armadaxp_pex2_mem_bs_tag, 745 &arm32_mvpex4_chipset, 746 ARMADAXP_TAG_PEX2_IO, 747 ARMADAXP_TAG_PEX2_MEM }, 748 749 { ARMADAXP_PEX3_BASE, 750 &armadaxp_pex3_io_bs_tag, 751 &armadaxp_pex3_mem_bs_tag, 752 &arm32_mvpex5_chipset, 753 ARMADAXP_TAG_PEX3_IO, 754 ARMADAXP_TAG_PEX3_MEM }, 755 756 { 0, 0, 0, 0, 0 }, 757 }; 758 759 for (i = 0; mvpex_tags[i].offset != 0; i++) { 760 if (mva->mva_offset != mvpex_tags[i].offset) 761 continue; 762 break; 763 } 764 if (mvpex_tags[i].offset == 0) 765 return; 766 mvpex_io_bs_tag = mvpex_tags[i].io_bs_tag; 767 mvpex_mem_bs_tag = mvpex_tags[i].mem_bs_tag; 768 arm32_mvpex_chipset = mvpex_tags[i].chipset; 769 iotag = mvpex_tags[i].iotag; 770 memtag = mvpex_tags[i].memtag; 771 break; 772 } 773 #endif 774 775 default: 776 return; 777 } 778 779 arm32_mvpex_chipset->pc_conf_v = device_private(dev); 780 arm32_mvpex_chipset->pc_intr_v = device_private(dev); 781 782 io_bs_tag = prop_data_create_data_nocopy( 783 mvpex_io_bs_tag, sizeof(struct bus_space)); 784 KASSERT(io_bs_tag != NULL); 785 prop_dictionary_set(dict, "io-bus-tag", io_bs_tag); 786 prop_object_release(io_bs_tag); 787 mem_bs_tag = prop_data_create_data_nocopy( 788 mvpex_mem_bs_tag, sizeof(struct bus_space)); 789 KASSERT(mem_bs_tag != NULL); 790 prop_dictionary_set(dict, "mem-bus-tag", mem_bs_tag); 791 prop_object_release(mem_bs_tag); 792 793 pc = prop_data_create_data_nocopy(arm32_mvpex_chipset, 794 sizeof(struct arm32_pci_chipset)); 795 KASSERT(pc != NULL); 796 prop_dictionary_set(dict, "pci-chipset", pc); 797 prop_object_release(pc); 798 799 marvell_startend_by_tag(iotag, &start, &end); 800 prop_dictionary_set_uint64(dict, "iostart", start); 801 prop_dictionary_set_uint64(dict, "ioend", end); 802 marvell_startend_by_tag(memtag, &start, &end); 803 prop_dictionary_set_uint64(dict, "memstart", start); 804 prop_dictionary_set_uint64(dict, "memend", end); 805 prop_dictionary_set_uint32(dict, 806 "cache-line-size", arm_dcache_align); 807 } 808 #endif 809 } 810 811 #if NGTPCI > 0 || NMVPEX > 0 812 static void 813 marvell_startend_by_tag(int tag, uint64_t *start, uint64_t *end) 814 { 815 uint32_t base, size; 816 int win; 817 818 win = mvsoc_target(tag, NULL, NULL, &base, &size); 819 if (size != 0) { 820 if (win < nremap) 821 *start = read_mlmbreg(MVSOC_MLMB_WRLR(win)) | 822 ((read_mlmbreg(MVSOC_MLMB_WRHR(win)) << 16) << 16); 823 else 824 *start = base; 825 *end = *start + size - 1; 826 } 827 } 828 #endif 829
Indexes created Thu Oct 02 01:09:59 GMT 2025