marvell_machdep.c revision 1.30.2.1
1 /* $NetBSD: marvell_machdep.c,v 1.30.2.1 2015/06/06 14:39:58 skrll Exp $ */ 2 /* 3 * Copyright (c) 2007, 2008, 2010 KIYOHARA Takashi 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 17 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 18 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 19 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 20 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 21 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 23 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 24 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 */ 27 #include <sys/cdefs.h> 28 __KERNEL_RCSID(0, "$NetBSD: marvell_machdep.c,v 1.30.2.1 2015/06/06 14:39:58 skrll Exp $"); 29 30 #include "opt_evbarm_boardtype.h" 31 #include "opt_ddb.h" 32 #include "opt_pci.h" 33 #include "opt_mvsoc.h" 34 #include "com.h" 35 #include "gtpci.h" 36 #include "mvpex.h" 37 38 #include <sys/param.h> 39 #include <sys/kernel.h> 40 #include <sys/reboot.h> 41 #include <sys/systm.h> 42 #include <sys/termios.h> 43 44 #include <prop/proplib.h> 45 46 #include <dev/cons.h> 47 #include <dev/md.h> 48 49 #include <dev/marvell/marvellreg.h> 50 #include <dev/marvell/marvellvar.h> 51 #include <dev/pci/pcireg.h> 52 #include <dev/pci/pcivar.h> 53 54 #include <machine/autoconf.h> 55 #include <machine/bootconfig.h> 56 #include <machine/pci_machdep.h> 57 58 #include <uvm/uvm_extern.h> 59 60 #include <arm/db_machdep.h> 61 #include <arm/undefined.h> 62 #include <arm/arm32/machdep.h> 63 64 #include <arm/marvell/mvsocreg.h> 65 #include <arm/marvell/mvsocvar.h> 66 #include <arm/marvell/orionreg.h> 67 #include <arm/marvell/kirkwoodreg.h> 68 #include <arm/marvell/mv78xx0reg.h> 69 #include <arm/marvell/armadaxpreg.h> 70 #include <arm/marvell/armadaxpvar.h> 71 #include <arm/marvell/mvsocgppvar.h> 72 73 #include <evbarm/marvell/marvellreg.h> 74 #include <evbarm/marvell/marvellvar.h> 75 76 #include <ddb/db_extern.h> 77 #include <ddb/db_sym.h> 78 79 #include "ksyms.h" 80 81 82 /* 83 * The range 0xc2000000 - 0xdfffffff is available for kernel VM space 84 * Core-logic registers and I/O mappings occupy 0xfe000000 - 0xffffffff 85 */ 86 #if (KERNEL_BASE & 0xf0000000) == 0x80000000 87 #define KERNEL_VM_BASE (KERNEL_BASE + 0x42000000) 88 #else 89 #define KERNEL_VM_BASE (KERNEL_BASE + 0x02000000) 90 #endif 91 #define KERNEL_VM_SIZE 0x1e000000 92 93 BootConfig bootconfig; /* Boot config storage */ 94 static char bootargs[MAX_BOOT_STRING]; 95 char *boot_args = NULL; 96 97 extern int KERNEL_BASE_phys[]; 98 extern char _end[]; 99 100 /* 101 * Macros to translate between physical and virtual for a subset of the 102 * kernel address space. *Not* for general use. 103 */ 104 #define KERNEL_BASE_PHYS physical_start 105 106 107 #include "com.h" 108 #if NCOM > 0 109 #include <dev/ic/comreg.h> 110 #include <dev/ic/comvar.h> 111 #endif 112 113 #ifndef CONSPEED 114 #define CONSPEED B115200 /* It's a setting of the default of u-boot */ 115 #endif 116 #ifndef CONMODE 117 #define CONMODE ((TTYDEF_CFLAG & ~(CSIZE | CSTOPB | PARENB)) | CS8) /* 8N1 */ 118 119 int comcnspeed = CONSPEED; 120 int comcnmode = CONMODE; 121 #endif 122 123 #include "opt_kgdb.h" 124 #ifdef KGDB 125 #include <sys/kgdb.h> 126 #endif 127 128 static void marvell_device_register(device_t, void *); 129 #if NGTPCI > 0 || NMVPEX > 0 130 static void marvell_startend_by_tag(int, uint64_t *, uint64_t *); 131 #endif 132 133 static void 134 marvell_fixup_mbus_pex(int memtag, int iotag) 135 { 136 uint32_t target, attr; 137 int window; 138 139 /* Reset PCI-Express space to window register. */ 140 window = mvsoc_target(memtag, &target, &attr, NULL, NULL); 141 write_mlmbreg(MVSOC_MLMB_WCR(window), 142 MVSOC_MLMB_WCR_WINEN | 143 MVSOC_MLMB_WCR_TARGET(target) | 144 MVSOC_MLMB_WCR_ATTR(attr) | 145 MVSOC_MLMB_WCR_SIZE(MARVELL_PEXMEM_SIZE)); 146 write_mlmbreg(MVSOC_MLMB_WBR(window), 147 MARVELL_PEXMEM_PBASE & MVSOC_MLMB_WBR_BASE_MASK); 148 #ifdef PCI_NETBSD_CONFIGURE 149 if (window < nremap) { 150 write_mlmbreg(MVSOC_MLMB_WRLR(window), 151 MARVELL_PEXMEM_PBASE & MVSOC_MLMB_WRLR_REMAP_MASK); 152 write_mlmbreg(MVSOC_MLMB_WRHR(window), 0); 153 } 154 #endif 155 window = mvsoc_target(iotag, &target, &attr, NULL, NULL); 156 write_mlmbreg(MVSOC_MLMB_WCR(window), 157 MVSOC_MLMB_WCR_WINEN | 158 MVSOC_MLMB_WCR_TARGET(target) | 159 MVSOC_MLMB_WCR_ATTR(attr) | 160 MVSOC_MLMB_WCR_SIZE(MARVELL_PEXIO_SIZE)); 161 write_mlmbreg(MVSOC_MLMB_WBR(window), 162 MARVELL_PEXIO_PBASE & MVSOC_MLMB_WBR_BASE_MASK); 163 #ifdef PCI_NETBSD_CONFIGURE 164 if (window < nremap) { 165 write_mlmbreg(MVSOC_MLMB_WRLR(window), 166 MARVELL_PEXIO_PBASE & MVSOC_MLMB_WRLR_REMAP_MASK); 167 write_mlmbreg(MVSOC_MLMB_WRHR(window), 0); 168 } 169 #endif 170 } 171 172 #if defined(ORION) || defined(KIRKWOOD) || defined(MV78XX0) 173 static void 174 marvell_system_reset(void) 175 { 176 /* unmask soft reset */ 177 write_mlmbreg(MVSOC_MLMB_RSTOUTNMASKR, 178 MVSOC_MLMB_RSTOUTNMASKR_SOFTRSTOUTEN); 179 /* assert soft reset */ 180 write_mlmbreg(MVSOC_MLMB_SSRR, MVSOC_MLMB_SSRR_SYSTEMSOFTRST); 181 182 /* if we're still running, jump to the reset address */ 183 cpu_reset_address = 0; 184 cpu_reset_address_paddr = 0xffff0000; 185 cpu_reset(); 186 /*NOTREACHED*/ 187 } 188 189 static void 190 marvell_fixup_mbus(int memtag, int iotag) 191 { 192 /* assume u-boot initializes mbus registers correctly */ 193 194 /* set marvell common PEX params */ 195 marvell_fixup_mbus_pex(memtag, iotag); 196 197 /* other configurations? */ 198 } 199 #endif 200 201 202 #if defined(ARMADAXP) 203 static void 204 armadaxp_system_reset(void) 205 { 206 extern vaddr_t misc_base; 207 208 #define write_miscreg(r, v) (*(volatile uint32_t *)(misc_base + (r)) = (v)) 209 210 /* Unmask soft reset */ 211 write_miscreg(ARMADAXP_MISC_RSTOUTNMASKR, 212 ARMADAXP_MISC_RSTOUTNMASKR_GLOBALSOFTRSTOUTEN); 213 /* Assert soft reset */ 214 write_miscreg(ARMADAXP_MISC_SSRR, ARMADAXP_MISC_SSRR_GLOBALSOFTRST); 215 216 while (1); 217 218 /*NOTREACHED*/ 219 } 220 221 static void 222 armadaxp_fixup_mbus(int memtag, int iotag) 223 { 224 /* force set SoC default parameters */ 225 armadaxp_init_mbus(); 226 227 /* set marvell common PEX params */ 228 marvell_fixup_mbus_pex(memtag, iotag); 229 230 /* other configurations? */ 231 } 232 #endif 233 234 235 static inline pd_entry_t * 236 read_ttb(void) 237 { 238 239 return (pd_entry_t *)(armreg_ttbr_read() & ~((1<<14)-1)); 240 } 241 242 /* 243 * Static device mappings. These peripheral registers are mapped at 244 * fixed virtual addresses very early in initarm() so that we can use 245 * them while booting the kernel, and stay at the same address 246 * throughout whole kernel's life time. 247 * 248 * We use this table twice; once with bootstrap page table, and once 249 * with kernel's page table which we build up in initarm(). 250 * 251 * Since we map these registers into the bootstrap page table using 252 * pmap_devmap_bootstrap() which calls pmap_map_chunk(), we map 253 * registers segment-aligned and segment-rounded in order to avoid 254 * using the 2nd page tables. 255 */ 256 #define _A(a) ((a) & ~L1_S_OFFSET) 257 #define _S(s) (((s) + L1_S_SIZE - 1) & ~(L1_S_SIZE-1)) 258 259 static struct pmap_devmap marvell_devmap[] = { 260 { 261 MARVELL_INTERREGS_VBASE, 262 _A(MARVELL_INTERREGS_PBASE), 263 _S(MARVELL_INTERREGS_SIZE), 264 VM_PROT_READ|VM_PROT_WRITE, 265 PTE_NOCACHE, 266 }, 267 268 { 0, 0, 0, 0, 0 } 269 }; 270 271 extern uint32_t *u_boot_args[]; 272 273 /* 274 * u_int initarm(...) 275 * 276 * Initial entry point on startup. This gets called before main() is 277 * entered. 278 * It should be responsible for setting up everything that must be 279 * in place when main is called. 280 * This includes 281 * Taking a copy of the boot configuration structure. 282 * Initialising the physical console so characters can be printed. 283 * Setting up page tables for the kernel 284 * Relocating the kernel to the bottom of physical memory 285 */ 286 u_int 287 initarm(void *arg) 288 { 289 int cs, cs_end, memtag = 0, iotag = 0; 290 291 mvsoc_bootstrap(MARVELL_INTERREGS_VBASE); 292 293 /* 294 * Heads up ... Setup the CPU / MMU / TLB functions 295 */ 296 if (set_cpufuncs()) 297 panic("cpu not recognized!"); 298 299 /* map some peripheral registers */ 300 pmap_devmap_bootstrap((vaddr_t)read_ttb(), marvell_devmap); 301 302 /* 303 * U-Boot doesn't use the virtual memory. 304 * 305 * Physical Address Range Description 306 * ----------------------- ---------------------------------- 307 * 0x00000000 - 0x0fffffff SDRAM Bank 0 (max 256MB) 308 * 0x10000000 - 0x1fffffff SDRAM Bank 1 (max 256MB) 309 * 0x20000000 - 0x2fffffff SDRAM Bank 2 (max 256MB) 310 * 0x30000000 - 0x3fffffff SDRAM Bank 3 (max 256MB) 311 * 0xf1000000 - 0xf10fffff SoC Internal Registers 312 */ 313 314 cpu_domains((DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL*2)) | DOMAIN_CLIENT); 315 316 /* Get ready for splfoo() */ 317 switch (mvsoc_model()) { 318 #ifdef ORION 319 case MARVELL_ORION_1_88F1181: 320 case MARVELL_ORION_1_88F5082: 321 case MARVELL_ORION_1_88F5180N: 322 case MARVELL_ORION_1_88F5181: 323 case MARVELL_ORION_1_88F5182: 324 case MARVELL_ORION_1_88F6082: 325 case MARVELL_ORION_1_88F6183: 326 case MARVELL_ORION_1_88W8660: 327 case MARVELL_ORION_2_88F1281: 328 case MARVELL_ORION_2_88F5281: 329 cpu_reset_address = marvell_system_reset; 330 331 orion_intr_bootstrap(); 332 333 memtag = ORION_TAG_PEX0_MEM; 334 iotag = ORION_TAG_PEX0_IO; 335 nwindow = ORION_MLMB_NWINDOW; 336 nremap = ORION_MLMB_NREMAP; 337 338 cs = MARVELL_TAG_SDRAM_CS0; 339 cs_end = MARVELL_TAG_SDRAM_CS3; 340 341 orion_getclks(MARVELL_INTERREGS_VBASE); 342 marvell_fixup_mbus(memtag, iotag); 343 break; 344 #endif /* ORION */ 345 346 #ifdef KIRKWOOD 347 case MARVELL_KIRKWOOD_88F6180: 348 case MARVELL_KIRKWOOD_88F6192: 349 case MARVELL_KIRKWOOD_88F6281: 350 case MARVELL_KIRKWOOD_88F6282: 351 cpu_reset_address = marvell_system_reset; 352 353 kirkwood_intr_bootstrap(); 354 355 memtag = KIRKWOOD_TAG_PEX_MEM; 356 iotag = KIRKWOOD_TAG_PEX_IO; 357 nwindow = KIRKWOOD_MLMB_NWINDOW; 358 nremap = KIRKWOOD_MLMB_NREMAP; 359 360 cs = MARVELL_TAG_SDRAM_CS0; 361 cs_end = MARVELL_TAG_SDRAM_CS3; 362 363 kirkwood_getclks(MARVELL_INTERREGS_VBASE); 364 mvsoc_clkgating = kirkwood_clkgating; 365 marvell_fixup_mbus(memtag, iotag); 366 break; 367 #endif /* KIRKWOOD */ 368 369 #ifdef MV78XX0 370 case MARVELL_MV78XX0_MV78100: 371 case MARVELL_MV78XX0_MV78200: 372 cpu_reset_address = marvell_system_reset; 373 374 mv78xx0_intr_bootstrap(); 375 376 memtag = MV78XX0_TAG_PEX0_MEM; 377 iotag = MV78XX0_TAG_PEX0_IO; 378 nwindow = MV78XX0_MLMB_NWINDOW; 379 nremap = MV78XX0_MLMB_NREMAP; 380 381 cs = MARVELL_TAG_SDRAM_CS0; 382 cs_end = MARVELL_TAG_SDRAM_CS3; 383 384 mv78xx0_getclks(MARVELL_INTERREGS_VBASE); 385 marvell_fixup_mbus(memtag, iotag); 386 break; 387 #endif /* MV78XX0 */ 388 389 #ifdef ARMADAXP 390 case MARVELL_ARMADAXP_MV78130: 391 case MARVELL_ARMADAXP_MV78160: 392 case MARVELL_ARMADAXP_MV78230: 393 case MARVELL_ARMADAXP_MV78260: 394 case MARVELL_ARMADAXP_MV78460: 395 cpu_reset_address = armadaxp_system_reset; 396 397 armadaxp_intr_bootstrap(MARVELL_INTERREGS_PBASE); 398 399 memtag = ARMADAXP_TAG_PEX00_MEM; 400 iotag = ARMADAXP_TAG_PEX00_IO; 401 nwindow = ARMADAXP_MLMB_NWINDOW; 402 nremap = ARMADAXP_MLMB_NREMAP; 403 404 cs = MARVELL_TAG_DDR3_CS0; 405 cs_end = MARVELL_TAG_DDR3_CS3; 406 407 extern vaddr_t misc_base; 408 misc_base = MARVELL_INTERREGS_VBASE + ARMADAXP_MISC_BASE; 409 armadaxp_getclks(); 410 mvsoc_clkgating = armadaxp_clkgating; 411 armadaxp_fixup_mbus(memtag, iotag); 412 413 #ifdef L2CACHE_ENABLE 414 /* Initialize L2 Cache */ 415 armadaxp_l2_init(MARVELL_INTERREGS_PBASE); 416 #endif 417 418 #ifdef AURORA_IO_CACHE_COHERENCY 419 /* Initialize cache coherency */ 420 armadaxp_io_coherency_init(); 421 #endif 422 break; 423 424 case MARVELL_ARMADA370_MV6707: 425 case MARVELL_ARMADA370_MV6710: 426 case MARVELL_ARMADA370_MV6W11: 427 cpu_reset_address = armadaxp_system_reset; 428 429 armadaxp_intr_bootstrap(MARVELL_INTERREGS_PBASE); 430 431 memtag = ARMADAXP_TAG_PEX00_MEM; 432 iotag = ARMADAXP_TAG_PEX00_IO; 433 nwindow = ARMADAXP_MLMB_NWINDOW; 434 nremap = ARMADAXP_MLMB_NREMAP; 435 436 cs = MARVELL_TAG_DDR3_CS0; 437 cs_end = MARVELL_TAG_DDR3_CS3; 438 439 extern vaddr_t misc_base; 440 misc_base = MARVELL_INTERREGS_VBASE + ARMADAXP_MISC_BASE; 441 armada370_getclks(); 442 mvsoc_clkgating = armadaxp_clkgating; 443 armadaxp_fixup_mbus(memtag, iotag); 444 445 #ifdef L2CACHE_ENABLE 446 /* Initialize L2 Cache */ 447 (void)armadaxp_l2_init(MARVELL_INTERREGS_PBASE); 448 #endif 449 450 #ifdef AURORA_IO_CACHE_COHERENCY 451 /* Initialize cache coherency */ 452 armadaxp_io_coherency_init(); 453 #endif 454 break; 455 #endif /* ARMADAXP */ 456 457 default: 458 /* We can't output console here yet... */ 459 panic("unknown model...\n"); 460 461 /* NOTREACHED */ 462 } 463 464 consinit(); 465 466 /* Talk to the user */ 467 #ifndef EVBARM_BOARDTYPE 468 #define EVBARM_BOARDTYPE Marvell 469 #endif 470 #define BDSTR(s) _BDSTR(s) 471 #define _BDSTR(s) #s 472 printf("\nNetBSD/evbarm (" BDSTR(EVBARM_BOARDTYPE) ") booting ...\n"); 473 474 /* copy command line U-Boot gave us, if args is valid. */ 475 if (u_boot_args[3] != 0) /* XXXXX: need more check?? */ 476 strncpy(bootargs, (char *)u_boot_args[3], sizeof(bootargs)); 477 478 #ifdef VERBOSE_INIT_ARM 479 printf("initarm: Configuring system ...\n"); 480 #endif 481 482 bootconfig.dramblocks = 0; 483 paddr_t segment_end; 484 segment_end = physmem = 0; 485 for ( ; cs <= cs_end; cs++) { 486 uint32_t target, attr, base, size; 487 488 mvsoc_target(cs, &target, &attr, &base, &size); 489 if (size == 0) 490 continue; 491 492 bootconfig.dram[bootconfig.dramblocks].address = base; 493 bootconfig.dram[bootconfig.dramblocks].pages = size / PAGE_SIZE; 494 495 if (base != segment_end) 496 panic("memory hole not support"); 497 498 segment_end += size; 499 physmem += size / PAGE_SIZE; 500 501 bootconfig.dramblocks++; 502 } 503 504 #ifdef __HAVE_MM_MD_DIRECT_MAPPED_PHYS 505 const bool mapallmem_p = true; 506 #else 507 const bool mapallmem_p = false; 508 #endif 509 510 arm32_bootmem_init(0, segment_end, (uintptr_t) KERNEL_BASE_phys); 511 arm32_kernel_vm_init(KERNEL_VM_BASE, ARM_VECTORS_HIGH, 0, 512 marvell_devmap, mapallmem_p); 513 514 /* we've a specific device_register routine */ 515 evbarm_device_register = marvell_device_register; 516 517 /* parse bootargs from U-Boot */ 518 boot_args = bootargs; 519 parse_mi_bootargs(boot_args); 520 521 return initarm_common(KERNEL_VM_BASE, KERNEL_VM_SIZE, NULL, 0); 522 } 523 524 void 525 consinit(void) 526 { 527 static int consinit_called = 0; 528 529 if (consinit_called != 0) 530 return; 531 532 consinit_called = 1; 533 534 #if NCOM > 0 535 { 536 extern int mvuart_cnattach(bus_space_tag_t, bus_addr_t, int, 537 uint32_t, int); 538 539 if (mvuart_cnattach(&mvsoc_bs_tag, 540 MARVELL_INTERREGS_PBASE + MVSOC_COM0_BASE, 541 comcnspeed, mvTclk, comcnmode)) 542 panic("can't init serial console"); 543 } 544 #else 545 panic("serial console not configured"); 546 #endif 547 } 548 549 550 static void 551 marvell_device_register(device_t dev, void *aux) 552 { 553 prop_dictionary_t dict = device_properties(dev); 554 555 #if NCOM > 0 556 if (device_is_a(dev, "com") && 557 device_is_a(device_parent(dev), "mvsoc")) 558 prop_dictionary_set_uint32(dict, "frequency", mvTclk); 559 #endif 560 561 if (device_is_a(dev, "gtidmac")) 562 prop_dictionary_set_uint32(dict, 563 "dmb_speed", mvTclk * sizeof(uint32_t)); /* XXXXXX */ 564 565 #if NGTPCI > 0 && defined(ORION) 566 if (device_is_a(dev, "gtpci")) { 567 extern struct bus_space 568 orion_pci_io_bs_tag, orion_pci_mem_bs_tag; 569 extern struct arm32_pci_chipset arm32_gtpci_chipset; 570 571 prop_data_t io_bs_tag, mem_bs_tag, pc; 572 prop_array_t int2gpp; 573 prop_number_t gpp; 574 uint64_t start, end; 575 int i, j; 576 static struct { 577 const char *boardtype; 578 int pin[PCI_INTERRUPT_PIN_MAX]; 579 } hints[] = { 580 { "kuronas_x4", 581 { 11, PCI_INTERRUPT_PIN_NONE } }, 582 583 { NULL, 584 { PCI_INTERRUPT_PIN_NONE } }, 585 }; 586 587 arm32_gtpci_chipset.pc_conf_v = device_private(dev); 588 arm32_gtpci_chipset.pc_intr_v = device_private(dev); 589 590 io_bs_tag = prop_data_create_data_nocopy( 591 &orion_pci_io_bs_tag, sizeof(struct bus_space)); 592 KASSERT(io_bs_tag != NULL); 593 prop_dictionary_set(dict, "io-bus-tag", io_bs_tag); 594 prop_object_release(io_bs_tag); 595 mem_bs_tag = prop_data_create_data_nocopy( 596 &orion_pci_mem_bs_tag, sizeof(struct bus_space)); 597 KASSERT(mem_bs_tag != NULL); 598 prop_dictionary_set(dict, "mem-bus-tag", mem_bs_tag); 599 prop_object_release(mem_bs_tag); 600 601 pc = prop_data_create_data_nocopy(&arm32_gtpci_chipset, 602 sizeof(struct arm32_pci_chipset)); 603 KASSERT(pc != NULL); 604 prop_dictionary_set(dict, "pci-chipset", pc); 605 prop_object_release(pc); 606 607 marvell_startend_by_tag(ORION_TAG_PCI_IO, &start, &end); 608 prop_dictionary_set_uint64(dict, "iostart", start); 609 prop_dictionary_set_uint64(dict, "ioend", end); 610 marvell_startend_by_tag(ORION_TAG_PCI_MEM, &start, &end); 611 prop_dictionary_set_uint64(dict, "memstart", start); 612 prop_dictionary_set_uint64(dict, "memend", end); 613 prop_dictionary_set_uint32(dict, 614 "cache-line-size", arm_dcache_align); 615 616 /* Setup the hint for interrupt-pin. */ 617 #define BDSTR(s) _BDSTR(s) 618 #define _BDSTR(s) #s 619 #define THIS_BOARD(str) (strcmp(str, BDSTR(EVBARM_BOARDTYPE)) == 0) 620 for (i = 0; hints[i].boardtype != NULL; i++) 621 if (THIS_BOARD(hints[i].boardtype)) 622 break; 623 if (hints[i].boardtype == NULL) 624 return; 625 626 int2gpp = 627 prop_array_create_with_capacity(PCI_INTERRUPT_PIN_MAX + 1); 628 629 /* first set dummy */ 630 gpp = prop_number_create_integer(0); 631 prop_array_add(int2gpp, gpp); 632 prop_object_release(gpp); 633 634 for (j = 0; hints[i].pin[j] != PCI_INTERRUPT_PIN_NONE; j++) { 635 gpp = prop_number_create_integer(hints[i].pin[j]); 636 prop_array_add(int2gpp, gpp); 637 prop_object_release(gpp); 638 } 639 prop_dictionary_set(dict, "int2gpp", int2gpp); 640 } 641 #endif /* NGTPCI > 0 && defined(ORION) */ 642 643 #if NMVPEX > 0 644 if (device_is_a(dev, "mvpex")) { 645 #ifdef ORION 646 extern struct bus_space 647 orion_pex0_io_bs_tag, orion_pex0_mem_bs_tag, 648 orion_pex1_io_bs_tag, orion_pex1_mem_bs_tag; 649 #endif 650 #ifdef KIRKWOOD 651 extern struct bus_space 652 kirkwood_pex_io_bs_tag, kirkwood_pex_mem_bs_tag, 653 kirkwood_pex1_io_bs_tag, kirkwood_pex1_mem_bs_tag; 654 #endif 655 #ifdef ARMADAXP 656 extern struct bus_space 657 armadaxp_pex00_io_bs_tag, armadaxp_pex00_mem_bs_tag, 658 armadaxp_pex01_io_bs_tag, armadaxp_pex01_mem_bs_tag, 659 armadaxp_pex02_io_bs_tag, armadaxp_pex02_mem_bs_tag, 660 armadaxp_pex03_io_bs_tag, armadaxp_pex03_mem_bs_tag, 661 armadaxp_pex2_io_bs_tag, armadaxp_pex2_mem_bs_tag, 662 armadaxp_pex3_io_bs_tag, armadaxp_pex3_mem_bs_tag; 663 int i; 664 #endif 665 extern struct arm32_pci_chipset 666 arm32_mvpex0_chipset, arm32_mvpex1_chipset; 667 668 struct marvell_attach_args *mva = aux; 669 struct bus_space *mvpex_io_bs_tag, *mvpex_mem_bs_tag; 670 struct arm32_pci_chipset *arm32_mvpex_chipset; 671 prop_data_t io_bs_tag, mem_bs_tag, pc; 672 uint64_t start, end; 673 int iotag, memtag; 674 675 switch (mvsoc_model()) { 676 #ifdef ORION 677 case MARVELL_ORION_1_88F5180N: 678 case MARVELL_ORION_1_88F5181: 679 case MARVELL_ORION_1_88F5182: 680 case MARVELL_ORION_1_88W8660: 681 case MARVELL_ORION_2_88F5281: 682 if (mva->mva_offset == MVSOC_PEX_BASE) { 683 mvpex_io_bs_tag = &orion_pex0_io_bs_tag; 684 mvpex_mem_bs_tag = &orion_pex0_mem_bs_tag; 685 arm32_mvpex_chipset = &arm32_mvpex0_chipset; 686 iotag = ORION_TAG_PEX0_IO; 687 memtag = ORION_TAG_PEX0_MEM; 688 } else { 689 mvpex_io_bs_tag = &orion_pex1_io_bs_tag; 690 mvpex_mem_bs_tag = &orion_pex1_mem_bs_tag; 691 arm32_mvpex_chipset = &arm32_mvpex1_chipset; 692 iotag = ORION_TAG_PEX1_IO; 693 memtag = ORION_TAG_PEX1_MEM; 694 } 695 break; 696 #endif 697 698 #ifdef KIRKWOOD 699 case MARVELL_KIRKWOOD_88F6282: 700 if (mva->mva_offset != MVSOC_PEX_BASE) { 701 mvpex_io_bs_tag = &kirkwood_pex1_io_bs_tag; 702 mvpex_mem_bs_tag = &kirkwood_pex1_mem_bs_tag; 703 arm32_mvpex_chipset = &arm32_mvpex1_chipset; 704 iotag = KIRKWOOD_TAG_PEX1_IO; 705 memtag = KIRKWOOD_TAG_PEX1_MEM; 706 break; 707 } 708 709 /* FALLTHROUGH */ 710 711 case MARVELL_KIRKWOOD_88F6180: 712 case MARVELL_KIRKWOOD_88F6192: 713 case MARVELL_KIRKWOOD_88F6281: 714 mvpex_io_bs_tag = &kirkwood_pex_io_bs_tag; 715 mvpex_mem_bs_tag = &kirkwood_pex_mem_bs_tag; 716 arm32_mvpex_chipset = &arm32_mvpex0_chipset; 717 iotag = KIRKWOOD_TAG_PEX_IO; 718 memtag = KIRKWOOD_TAG_PEX_MEM; 719 break; 720 #endif 721 722 #ifdef ARMADAXP 723 case MARVELL_ARMADAXP_MV78130: 724 case MARVELL_ARMADAXP_MV78160: 725 case MARVELL_ARMADAXP_MV78230: 726 case MARVELL_ARMADAXP_MV78260: 727 case MARVELL_ARMADAXP_MV78460: 728 729 case MARVELL_ARMADA370_MV6707: 730 case MARVELL_ARMADA370_MV6710: 731 case MARVELL_ARMADA370_MV6W11: 732 { 733 extern struct arm32_pci_chipset 734 arm32_mvpex2_chipset, arm32_mvpex3_chipset, 735 arm32_mvpex4_chipset, arm32_mvpex5_chipset; 736 const struct { 737 bus_size_t offset; 738 struct bus_space *io_bs_tag; 739 struct bus_space *mem_bs_tag; 740 struct arm32_pci_chipset *chipset; 741 int iotag; 742 int memtag; 743 } mvpex_tags[] = { 744 { MVSOC_PEX_BASE, 745 &armadaxp_pex00_io_bs_tag, 746 &armadaxp_pex00_mem_bs_tag, 747 &arm32_mvpex0_chipset, 748 ARMADAXP_TAG_PEX00_IO, 749 ARMADAXP_TAG_PEX00_MEM }, 750 751 { ARMADAXP_PEX01_BASE, 752 &armadaxp_pex01_io_bs_tag, 753 &armadaxp_pex01_mem_bs_tag, 754 &arm32_mvpex1_chipset, 755 ARMADAXP_TAG_PEX01_IO, 756 ARMADAXP_TAG_PEX01_MEM }, 757 758 { ARMADAXP_PEX02_BASE, 759 &armadaxp_pex02_io_bs_tag, 760 &armadaxp_pex02_mem_bs_tag, 761 &arm32_mvpex2_chipset, 762 ARMADAXP_TAG_PEX02_IO, 763 ARMADAXP_TAG_PEX02_MEM }, 764 765 { ARMADAXP_PEX03_BASE, 766 &armadaxp_pex03_io_bs_tag, 767 &armadaxp_pex03_mem_bs_tag, 768 &arm32_mvpex3_chipset, 769 ARMADAXP_TAG_PEX03_IO, 770 ARMADAXP_TAG_PEX03_MEM }, 771 772 { ARMADAXP_PEX2_BASE, 773 &armadaxp_pex2_io_bs_tag, 774 &armadaxp_pex2_mem_bs_tag, 775 &arm32_mvpex4_chipset, 776 ARMADAXP_TAG_PEX2_IO, 777 ARMADAXP_TAG_PEX2_MEM }, 778 779 { ARMADAXP_PEX3_BASE, 780 &armadaxp_pex3_io_bs_tag, 781 &armadaxp_pex3_mem_bs_tag, 782 &arm32_mvpex5_chipset, 783 ARMADAXP_TAG_PEX3_IO, 784 ARMADAXP_TAG_PEX3_MEM }, 785 786 { 0, 0, 0, 0, 0 }, 787 }; 788 789 for (i = 0; mvpex_tags[i].offset != 0; i++) { 790 if (mva->mva_offset != mvpex_tags[i].offset) 791 continue; 792 break; 793 } 794 if (mvpex_tags[i].offset == 0) 795 return; 796 mvpex_io_bs_tag = mvpex_tags[i].io_bs_tag; 797 mvpex_mem_bs_tag = mvpex_tags[i].mem_bs_tag; 798 arm32_mvpex_chipset = mvpex_tags[i].chipset; 799 iotag = mvpex_tags[i].iotag; 800 memtag = mvpex_tags[i].memtag; 801 break; 802 } 803 #endif 804 805 default: 806 return; 807 } 808 809 arm32_mvpex_chipset->pc_conf_v = device_private(dev); 810 arm32_mvpex_chipset->pc_intr_v = device_private(dev); 811 812 io_bs_tag = prop_data_create_data_nocopy( 813 mvpex_io_bs_tag, sizeof(struct bus_space)); 814 KASSERT(io_bs_tag != NULL); 815 prop_dictionary_set(dict, "io-bus-tag", io_bs_tag); 816 prop_object_release(io_bs_tag); 817 mem_bs_tag = prop_data_create_data_nocopy( 818 mvpex_mem_bs_tag, sizeof(struct bus_space)); 819 KASSERT(mem_bs_tag != NULL); 820 prop_dictionary_set(dict, "mem-bus-tag", mem_bs_tag); 821 prop_object_release(mem_bs_tag); 822 823 pc = prop_data_create_data_nocopy(arm32_mvpex_chipset, 824 sizeof(struct arm32_pci_chipset)); 825 KASSERT(pc != NULL); 826 prop_dictionary_set(dict, "pci-chipset", pc); 827 prop_object_release(pc); 828 829 marvell_startend_by_tag(iotag, &start, &end); 830 prop_dictionary_set_uint64(dict, "iostart", start); 831 prop_dictionary_set_uint64(dict, "ioend", end); 832 marvell_startend_by_tag(memtag, &start, &end); 833 prop_dictionary_set_uint64(dict, "memstart", start); 834 prop_dictionary_set_uint64(dict, "memend", end); 835 prop_dictionary_set_uint32(dict, 836 "cache-line-size", arm_dcache_align); 837 } 838 #endif 839 } 840 841 #if NGTPCI > 0 || NMVPEX > 0 842 static void 843 marvell_startend_by_tag(int tag, uint64_t *start, uint64_t *end) 844 { 845 uint32_t base, size; 846 int win; 847 848 win = mvsoc_target(tag, NULL, NULL, &base, &size); 849 if (size != 0) { 850 if (win < nremap) 851 *start = read_mlmbreg(MVSOC_MLMB_WRLR(win)) | 852 ((read_mlmbreg(MVSOC_MLMB_WRHR(win)) << 16) << 16); 853 else 854 *start = base; 855 *end = *start + size - 1; 856 } 857 } 858 #endif 859
Indexes created Sat Oct 25 16:10:12 GMT 2025