marvell_machdep.c revision 1.34
1 /* $NetBSD: marvell_machdep.c,v 1.34 2018/07/31 06:46:27 skrll Exp $ */ 2 /* 3 * Copyright (c) 2007, 2008, 2010 KIYOHARA Takashi 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 17 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 18 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 19 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 20 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 21 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 23 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 24 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 */ 27 #include <sys/cdefs.h> 28 __KERNEL_RCSID(0, "$NetBSD: marvell_machdep.c,v 1.34 2018/07/31 06:46:27 skrll Exp $"); 29 30 #include "opt_arm_debug.h" 31 #include "opt_evbarm_boardtype.h" 32 #include "opt_ddb.h" 33 #include "opt_pci.h" 34 #include "opt_mvsoc.h" 35 #include "com.h" 36 #include "gtpci.h" 37 #include "mvpex.h" 38 39 #include <sys/param.h> 40 #include <sys/kernel.h> 41 #include <sys/reboot.h> 42 #include <sys/systm.h> 43 #include <sys/termios.h> 44 45 #include <prop/proplib.h> 46 47 #include <dev/cons.h> 48 #include <dev/md.h> 49 50 #include <dev/marvell/marvellreg.h> 51 #include <dev/marvell/marvellvar.h> 52 #include <dev/pci/pcireg.h> 53 #include <dev/pci/pcivar.h> 54 55 #include <machine/autoconf.h> 56 #include <machine/bootconfig.h> 57 #include <machine/pci_machdep.h> 58 59 #include <uvm/uvm_extern.h> 60 61 #include <arm/db_machdep.h> 62 #include <arm/undefined.h> 63 #include <arm/arm32/machdep.h> 64 65 #include <arm/marvell/mvsocreg.h> 66 #include <arm/marvell/mvsocvar.h> 67 #include <arm/marvell/orionreg.h> 68 #include <arm/marvell/kirkwoodreg.h> 69 #include <arm/marvell/mv78xx0reg.h> 70 #include <arm/marvell/dovereg.h> 71 #include <arm/marvell/armadaxpreg.h> 72 #include <arm/marvell/armadaxpvar.h> 73 #include <arm/marvell/mvsocgppvar.h> 74 75 #include <evbarm/marvell/marvellreg.h> 76 #include <evbarm/marvell/marvellvar.h> 77 78 #include <ddb/db_extern.h> 79 #include <ddb/db_sym.h> 80 81 #include "ksyms.h" 82 83 84 /* 85 * The range 0xc2000000 - 0xdfffffff is available for kernel VM space 86 * Core-logic registers and I/O mappings occupy 0xfe000000 - 0xffffffff 87 */ 88 #if (KERNEL_BASE & 0xf0000000) == 0x80000000 89 #define KERNEL_VM_BASE (KERNEL_BASE + 0x42000000) 90 #else 91 #define KERNEL_VM_BASE (KERNEL_BASE + 0x02000000) 92 #endif 93 #define KERNEL_VM_SIZE 0x1e000000 94 95 BootConfig bootconfig; /* Boot config storage */ 96 static char bootargs[MAX_BOOT_STRING]; 97 char *boot_args = NULL; 98 99 extern int KERNEL_BASE_phys[]; 100 extern char _end[]; 101 102 /* 103 * Macros to translate between physical and virtual for a subset of the 104 * kernel address space. *Not* for general use. 105 */ 106 #define KERNEL_BASE_PHYS physical_start 107 108 109 #include "com.h" 110 #if NCOM > 0 111 #include <dev/ic/comreg.h> 112 #include <dev/ic/comvar.h> 113 #endif 114 115 #ifndef CONSPEED 116 #define CONSPEED B115200 /* It's a setting of the default of u-boot */ 117 #endif 118 #ifndef CONMODE 119 #define CONMODE ((TTYDEF_CFLAG & ~(CSIZE | CSTOPB | PARENB)) | CS8) /* 8N1 */ 120 121 int comcnspeed = CONSPEED; 122 int comcnmode = CONMODE; 123 #endif 124 125 #include "opt_kgdb.h" 126 #ifdef KGDB 127 #include <sys/kgdb.h> 128 #endif 129 130 static void marvell_device_register(device_t, void *); 131 #if NGTPCI > 0 || NMVPEX > 0 132 static void marvell_startend_by_tag(int, uint64_t *, uint64_t *); 133 #endif 134 135 static void 136 marvell_fixup_mbus_pex(int memtag, int iotag) 137 { 138 uint32_t target, attr; 139 int window; 140 141 /* Reset PCI-Express space to window register. */ 142 window = mvsoc_target(memtag, &target, &attr, NULL, NULL); 143 write_mlmbreg(MVSOC_MLMB_WCR(window), 144 MVSOC_MLMB_WCR_WINEN | 145 MVSOC_MLMB_WCR_TARGET(target) | 146 MVSOC_MLMB_WCR_ATTR(attr) | 147 MVSOC_MLMB_WCR_SIZE(MARVELL_PEXMEM_SIZE)); 148 write_mlmbreg(MVSOC_MLMB_WBR(window), 149 MARVELL_PEXMEM_PBASE & MVSOC_MLMB_WBR_BASE_MASK); 150 #ifdef PCI_NETBSD_CONFIGURE 151 if (window < nremap) { 152 write_mlmbreg(MVSOC_MLMB_WRLR(window), 153 MARVELL_PEXMEM_PBASE & MVSOC_MLMB_WRLR_REMAP_MASK); 154 write_mlmbreg(MVSOC_MLMB_WRHR(window), 0); 155 } 156 #endif 157 window = mvsoc_target(iotag, &target, &attr, NULL, NULL); 158 write_mlmbreg(MVSOC_MLMB_WCR(window), 159 MVSOC_MLMB_WCR_WINEN | 160 MVSOC_MLMB_WCR_TARGET(target) | 161 MVSOC_MLMB_WCR_ATTR(attr) | 162 MVSOC_MLMB_WCR_SIZE(MARVELL_PEXIO_SIZE)); 163 write_mlmbreg(MVSOC_MLMB_WBR(window), 164 MARVELL_PEXIO_PBASE & MVSOC_MLMB_WBR_BASE_MASK); 165 #ifdef PCI_NETBSD_CONFIGURE 166 if (window < nremap) { 167 write_mlmbreg(MVSOC_MLMB_WRLR(window), 168 MARVELL_PEXIO_PBASE & MVSOC_MLMB_WRLR_REMAP_MASK); 169 write_mlmbreg(MVSOC_MLMB_WRHR(window), 0); 170 } 171 #endif 172 } 173 174 #if defined(ORION) || defined(KIRKWOOD) || defined(MV78XX0) || defined(DOVE) 175 static void 176 marvell_system_reset(void) 177 { 178 /* unmask soft reset */ 179 write_mlmbreg(MVSOC_MLMB_RSTOUTNMASKR, 180 MVSOC_MLMB_RSTOUTNMASKR_SOFTRSTOUTEN); 181 /* assert soft reset */ 182 write_mlmbreg(MVSOC_MLMB_SSRR, MVSOC_MLMB_SSRR_SYSTEMSOFTRST); 183 184 /* if we're still running, jump to the reset address */ 185 cpu_reset_address = 0; 186 cpu_reset_address_paddr = 0xffff0000; 187 cpu_reset(); 188 /*NOTREACHED*/ 189 } 190 191 static void 192 marvell_fixup_mbus(int memtag, int iotag) 193 { 194 /* assume u-boot initializes mbus registers correctly */ 195 196 /* set marvell common PEX params */ 197 marvell_fixup_mbus_pex(memtag, iotag); 198 199 /* other configurations? */ 200 } 201 #endif 202 203 204 #if defined(ARMADAXP) 205 static void 206 armadaxp_system_reset(void) 207 { 208 extern vaddr_t misc_base; 209 210 #define write_miscreg(r, v) (*(volatile uint32_t *)(misc_base + (r)) = (v)) 211 212 /* Unmask soft reset */ 213 write_miscreg(ARMADAXP_MISC_RSTOUTNMASKR, 214 ARMADAXP_MISC_RSTOUTNMASKR_GLOBALSOFTRSTOUTEN); 215 /* Assert soft reset */ 216 write_miscreg(ARMADAXP_MISC_SSRR, ARMADAXP_MISC_SSRR_GLOBALSOFTRST); 217 218 while (1); 219 220 /*NOTREACHED*/ 221 } 222 223 static void 224 armadaxp_fixup_mbus(int memtag, int iotag) 225 { 226 /* force set SoC default parameters */ 227 armadaxp_init_mbus(); 228 229 /* set marvell common PEX params */ 230 marvell_fixup_mbus_pex(memtag, iotag); 231 232 /* other configurations? */ 233 } 234 #endif 235 236 237 static inline pd_entry_t * 238 read_ttb(void) 239 { 240 241 return (pd_entry_t *)(armreg_ttbr_read() & ~((1<<14)-1)); 242 } 243 244 /* 245 * Static device mappings. These peripheral registers are mapped at 246 * fixed virtual addresses very early in initarm() so that we can use 247 * them while booting the kernel, and stay at the same address 248 * throughout whole kernel's life time. 249 * 250 * We use this table twice; once with bootstrap page table, and once 251 * with kernel's page table which we build up in initarm(). 252 * 253 * Since we map these registers into the bootstrap page table using 254 * pmap_devmap_bootstrap() which calls pmap_map_chunk(), we map 255 * registers segment-aligned and segment-rounded in order to avoid 256 * using the 2nd page tables. 257 */ 258 #define _A(a) ((a) & ~L1_S_OFFSET) 259 #define _S(s) (((s) + L1_S_SIZE - 1) & ~(L1_S_SIZE-1)) 260 261 static struct pmap_devmap marvell_devmap[] = { 262 { 263 MARVELL_INTERREGS_VBASE, 264 _A(MARVELL_INTERREGS_PBASE), 265 _S(MVSOC_INTERREGS_SIZE), 266 VM_PROT_READ|VM_PROT_WRITE, 267 PTE_NOCACHE, 268 }, 269 270 { 0, 0, 0, 0, 0 } 271 }; 272 273 extern uint32_t *u_boot_args[]; 274 275 /* 276 * u_int initarm(...) 277 * 278 * Initial entry point on startup. This gets called before main() is 279 * entered. 280 * It should be responsible for setting up everything that must be 281 * in place when main is called. 282 * This includes 283 * Taking a copy of the boot configuration structure. 284 * Initialising the physical console so characters can be printed. 285 * Setting up page tables for the kernel 286 * Relocating the kernel to the bottom of physical memory 287 */ 288 u_int 289 initarm(void *arg) 290 { 291 int cs, cs_end, memtag = 0, iotag = 0; 292 293 mvsoc_bootstrap(MARVELL_INTERREGS_VBASE); 294 295 /* 296 * Heads up ... Setup the CPU / MMU / TLB functions 297 */ 298 if (set_cpufuncs()) 299 panic("cpu not recognized!"); 300 301 /* map some peripheral registers */ 302 pmap_devmap_bootstrap((vaddr_t)read_ttb(), marvell_devmap); 303 304 /* 305 * U-Boot doesn't use the virtual memory. 306 * 307 * Physical Address Range Description 308 * ----------------------- ---------------------------------- 309 * 0x00000000 - 0x0fffffff SDRAM Bank 0 (max 256MB) 310 * 0x10000000 - 0x1fffffff SDRAM Bank 1 (max 256MB) 311 * 0x20000000 - 0x2fffffff SDRAM Bank 2 (max 256MB) 312 * 0x30000000 - 0x3fffffff SDRAM Bank 3 (max 256MB) 313 * 0xf1000000 - 0xf10fffff SoC Internal Registers 314 */ 315 316 cpu_domains((DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL*2)) | DOMAIN_CLIENT); 317 318 /* Get ready for splfoo() */ 319 switch (mvsoc_model()) { 320 #ifdef ORION 321 case MARVELL_ORION_1_88F1181: 322 case MARVELL_ORION_1_88F5082: 323 case MARVELL_ORION_1_88F5180N: 324 case MARVELL_ORION_1_88F5181: 325 case MARVELL_ORION_1_88F5182: 326 case MARVELL_ORION_1_88F6082: 327 case MARVELL_ORION_1_88F6183: 328 case MARVELL_ORION_1_88W8660: 329 case MARVELL_ORION_2_88F1281: 330 case MARVELL_ORION_2_88F5281: 331 cpu_reset_address = marvell_system_reset; 332 333 orion_bootstrap(MARVELL_INTERREGS_VBASE); 334 335 memtag = ORION_TAG_PEX0_MEM; 336 iotag = ORION_TAG_PEX0_IO; 337 nwindow = ORION_MLMB_NWINDOW; 338 nremap = ORION_MLMB_NREMAP; 339 340 cs = MARVELL_TAG_SDRAM_CS0; 341 cs_end = MARVELL_TAG_SDRAM_CS3; 342 343 marvell_fixup_mbus(memtag, iotag); 344 break; 345 #endif /* ORION */ 346 347 #ifdef KIRKWOOD 348 case MARVELL_KIRKWOOD_88F6180: 349 case MARVELL_KIRKWOOD_88F6192: 350 case MARVELL_KIRKWOOD_88F6281: 351 case MARVELL_KIRKWOOD_88F6282: 352 cpu_reset_address = marvell_system_reset; 353 354 kirkwood_bootstrap(MARVELL_INTERREGS_VBASE); 355 356 memtag = KIRKWOOD_TAG_PEX_MEM; 357 iotag = KIRKWOOD_TAG_PEX_IO; 358 nwindow = KIRKWOOD_MLMB_NWINDOW; 359 nremap = KIRKWOOD_MLMB_NREMAP; 360 361 cs = MARVELL_TAG_SDRAM_CS0; 362 cs_end = MARVELL_TAG_SDRAM_CS3; 363 364 marvell_fixup_mbus(memtag, iotag); 365 break; 366 #endif /* KIRKWOOD */ 367 368 #ifdef MV78XX0 369 case MARVELL_MV78XX0_MV78100: 370 case MARVELL_MV78XX0_MV78200: 371 cpu_reset_address = marvell_system_reset; 372 373 mv78xx0_bootstrap(MARVELL_INTERREGS_VBASE); 374 375 memtag = MV78XX0_TAG_PEX0_MEM; 376 iotag = MV78XX0_TAG_PEX0_IO; 377 nwindow = MV78XX0_MLMB_NWINDOW; 378 nremap = MV78XX0_MLMB_NREMAP; 379 380 cs = MARVELL_TAG_SDRAM_CS0; 381 cs_end = MARVELL_TAG_SDRAM_CS3; 382 383 marvell_fixup_mbus(memtag, iotag); 384 break; 385 #endif /* MV78XX0 */ 386 387 #ifdef DOVE 388 case MARVELL_DOVE_88AP510: 389 cpu_reset_address = marvell_system_reset; 390 391 dove_bootstrap(MARVELL_INTERREGS_VBASE); 392 393 memtag = DOVE_TAG_PEX0_MEM; 394 iotag = DOVE_TAG_PEX0_IO; 395 nwindow = DOVE_DB_NWINDOW; 396 nremap = DOVE_DB_NREMAP; 397 398 cs = MARVELL_TAG_AXI_CS0; 399 cs_end = MARVELL_TAG_AXI_CS1; 400 401 marvell_fixup_mbus(memtag, iotag); 402 break; 403 #endif /* DOVE */ 404 405 #ifdef ARMADAXP 406 case MARVELL_ARMADAXP_MV78130: 407 case MARVELL_ARMADAXP_MV78160: 408 case MARVELL_ARMADAXP_MV78230: 409 case MARVELL_ARMADAXP_MV78260: 410 case MARVELL_ARMADAXP_MV78460: 411 case MARVELL_ARMADA370_MV6707: 412 case MARVELL_ARMADA370_MV6710: 413 case MARVELL_ARMADA370_MV6W11: 414 cpu_reset_address = armadaxp_system_reset; 415 416 armadaxp_bootstrap( 417 MARVELL_INTERREGS_VBASE, 418 MARVELL_INTERREGS_PBASE); 419 420 memtag = ARMADAXP_TAG_PEX00_MEM; 421 iotag = ARMADAXP_TAG_PEX00_IO; 422 nwindow = ARMADAXP_MLMB_NWINDOW; 423 nremap = ARMADAXP_MLMB_NREMAP; 424 425 cs = MARVELL_TAG_DDR3_CS0; 426 cs_end = MARVELL_TAG_DDR3_CS3; 427 428 armadaxp_fixup_mbus(memtag, iotag); 429 break; 430 #endif /* ARMADAXP */ 431 432 default: 433 /* We can't output console here yet... */ 434 panic("unknown model...\n"); 435 436 /* NOTREACHED */ 437 } 438 439 consinit(); 440 441 /* Talk to the user */ 442 #ifndef EVBARM_BOARDTYPE 443 #define EVBARM_BOARDTYPE Marvell 444 #endif 445 #define BDSTR(s) _BDSTR(s) 446 #define _BDSTR(s) #s 447 printf("\nNetBSD/evbarm (" BDSTR(EVBARM_BOARDTYPE) ") booting ...\n"); 448 449 /* copy command line U-Boot gave us, if args is valid. */ 450 if (u_boot_args[3] != 0) /* XXXXX: need more check?? */ 451 strncpy(bootargs, (char *)u_boot_args[3], sizeof(bootargs)); 452 453 #ifdef VERBOSE_INIT_ARM 454 printf("initarm: Configuring system ...\n"); 455 #endif 456 457 bootconfig.dramblocks = 0; 458 paddr_t segment_end; 459 segment_end = physmem = 0; 460 for ( ; cs <= cs_end; cs++) { 461 uint32_t base, size; 462 463 mvsoc_target(cs, NULL, NULL, &base, &size); 464 if (size == 0) 465 continue; 466 467 bootconfig.dram[bootconfig.dramblocks].address = base; 468 bootconfig.dram[bootconfig.dramblocks].pages = size / PAGE_SIZE; 469 470 if (base != segment_end) 471 panic("memory hole not support"); 472 473 segment_end += size; 474 physmem += size / PAGE_SIZE; 475 476 bootconfig.dramblocks++; 477 } 478 479 #ifdef __HAVE_MM_MD_DIRECT_MAPPED_PHYS 480 const bool mapallmem_p = true; 481 #else 482 const bool mapallmem_p = false; 483 #endif 484 485 arm32_bootmem_init(0, segment_end, (uintptr_t) KERNEL_BASE_phys); 486 arm32_kernel_vm_init(KERNEL_VM_BASE, ARM_VECTORS_HIGH, 0, 487 marvell_devmap, mapallmem_p); 488 489 /* we've a specific device_register routine */ 490 evbarm_device_register = marvell_device_register; 491 492 /* parse bootargs from U-Boot */ 493 boot_args = bootargs; 494 parse_mi_bootargs(boot_args); 495 496 return initarm_common(KERNEL_VM_BASE, KERNEL_VM_SIZE, NULL, 0); 497 } 498 499 void 500 consinit(void) 501 { 502 static int consinit_called = 0; 503 504 if (consinit_called != 0) 505 return; 506 507 consinit_called = 1; 508 509 #if NCOM > 0 510 { 511 extern int mvuart_cnattach(bus_space_tag_t, bus_addr_t, int, 512 uint32_t, int); 513 514 if (mvuart_cnattach(&mvsoc_bs_tag, 515 MARVELL_INTERREGS_PBASE + MVSOC_COM0_BASE, 516 comcnspeed, mvTclk, comcnmode)) 517 panic("can't init serial console"); 518 } 519 #else 520 panic("serial console not configured"); 521 #endif 522 } 523 524 525 static void 526 marvell_device_register(device_t dev, void *aux) 527 { 528 prop_dictionary_t dict = device_properties(dev); 529 530 #if NCOM > 0 531 if (device_is_a(dev, "com") && 532 device_is_a(device_parent(dev), "mvsoc")) 533 prop_dictionary_set_uint32(dict, "frequency", mvTclk); 534 #endif 535 536 if (device_is_a(dev, "gtidmac")) 537 prop_dictionary_set_uint32(dict, 538 "dmb_speed", mvTclk * sizeof(uint32_t)); /* XXXXXX */ 539 540 #if NGTPCI > 0 && defined(ORION) 541 if (device_is_a(dev, "gtpci")) { 542 extern struct bus_space 543 orion_pci_io_bs_tag, orion_pci_mem_bs_tag; 544 extern struct arm32_pci_chipset arm32_gtpci_chipset; 545 546 prop_data_t io_bs_tag, mem_bs_tag, pc; 547 prop_array_t int2gpp; 548 prop_number_t gpp; 549 uint64_t start, end; 550 int i, j; 551 static struct { 552 const char *boardtype; 553 int pin[PCI_INTERRUPT_PIN_MAX]; 554 } hints[] = { 555 { "kuronas_x4", 556 { 11, PCI_INTERRUPT_PIN_NONE } }, 557 558 { NULL, 559 { PCI_INTERRUPT_PIN_NONE } }, 560 }; 561 562 arm32_gtpci_chipset.pc_conf_v = device_private(dev); 563 arm32_gtpci_chipset.pc_intr_v = device_private(dev); 564 565 io_bs_tag = prop_data_create_data_nocopy( 566 &orion_pci_io_bs_tag, sizeof(struct bus_space)); 567 KASSERT(io_bs_tag != NULL); 568 prop_dictionary_set(dict, "io-bus-tag", io_bs_tag); 569 prop_object_release(io_bs_tag); 570 mem_bs_tag = prop_data_create_data_nocopy( 571 &orion_pci_mem_bs_tag, sizeof(struct bus_space)); 572 KASSERT(mem_bs_tag != NULL); 573 prop_dictionary_set(dict, "mem-bus-tag", mem_bs_tag); 574 prop_object_release(mem_bs_tag); 575 576 pc = prop_data_create_data_nocopy(&arm32_gtpci_chipset, 577 sizeof(struct arm32_pci_chipset)); 578 KASSERT(pc != NULL); 579 prop_dictionary_set(dict, "pci-chipset", pc); 580 prop_object_release(pc); 581 582 marvell_startend_by_tag(ORION_TAG_PCI_IO, &start, &end); 583 prop_dictionary_set_uint64(dict, "iostart", start); 584 prop_dictionary_set_uint64(dict, "ioend", end); 585 marvell_startend_by_tag(ORION_TAG_PCI_MEM, &start, &end); 586 prop_dictionary_set_uint64(dict, "memstart", start); 587 prop_dictionary_set_uint64(dict, "memend", end); 588 prop_dictionary_set_uint32(dict, 589 "cache-line-size", arm_dcache_align); 590 591 /* Setup the hint for interrupt-pin. */ 592 #define BDSTR(s) _BDSTR(s) 593 #define _BDSTR(s) #s 594 #define THIS_BOARD(str) (strcmp(str, BDSTR(EVBARM_BOARDTYPE)) == 0) 595 for (i = 0; hints[i].boardtype != NULL; i++) 596 if (THIS_BOARD(hints[i].boardtype)) 597 break; 598 if (hints[i].boardtype == NULL) 599 return; 600 601 int2gpp = 602 prop_array_create_with_capacity(PCI_INTERRUPT_PIN_MAX + 1); 603 604 /* first set dummy */ 605 gpp = prop_number_create_integer(0); 606 prop_array_add(int2gpp, gpp); 607 prop_object_release(gpp); 608 609 for (j = 0; hints[i].pin[j] != PCI_INTERRUPT_PIN_NONE; j++) { 610 gpp = prop_number_create_integer(hints[i].pin[j]); 611 prop_array_add(int2gpp, gpp); 612 prop_object_release(gpp); 613 } 614 prop_dictionary_set(dict, "int2gpp", int2gpp); 615 } 616 #endif /* NGTPCI > 0 && defined(ORION) */ 617 618 #if NMVPEX > 0 619 if (device_is_a(dev, "mvpex")) { 620 #ifdef ORION 621 extern struct bus_space 622 orion_pex0_io_bs_tag, orion_pex0_mem_bs_tag, 623 orion_pex1_io_bs_tag, orion_pex1_mem_bs_tag; 624 #endif 625 #ifdef KIRKWOOD 626 extern struct bus_space 627 kirkwood_pex_io_bs_tag, kirkwood_pex_mem_bs_tag, 628 kirkwood_pex1_io_bs_tag, kirkwood_pex1_mem_bs_tag; 629 #endif 630 #ifdef DOVE 631 extern struct bus_space 632 dove_pex0_io_bs_tag, dove_pex0_mem_bs_tag, 633 dove_pex1_io_bs_tag, dove_pex1_mem_bs_tag; 634 #endif 635 #ifdef ARMADAXP 636 extern struct bus_space 637 armadaxp_pex00_io_bs_tag, armadaxp_pex00_mem_bs_tag, 638 armadaxp_pex01_io_bs_tag, armadaxp_pex01_mem_bs_tag, 639 armadaxp_pex02_io_bs_tag, armadaxp_pex02_mem_bs_tag, 640 armadaxp_pex03_io_bs_tag, armadaxp_pex03_mem_bs_tag, 641 armadaxp_pex2_io_bs_tag, armadaxp_pex2_mem_bs_tag, 642 armadaxp_pex3_io_bs_tag, armadaxp_pex3_mem_bs_tag; 643 int i; 644 #endif 645 extern struct arm32_pci_chipset 646 arm32_mvpex0_chipset, arm32_mvpex1_chipset; 647 648 struct marvell_attach_args *mva = aux; 649 struct bus_space *mvpex_io_bs_tag, *mvpex_mem_bs_tag; 650 struct arm32_pci_chipset *arm32_mvpex_chipset; 651 prop_data_t io_bs_tag, mem_bs_tag, pc; 652 uint64_t start, end; 653 int iotag, memtag; 654 655 switch (mvsoc_model()) { 656 #ifdef ORION 657 case MARVELL_ORION_1_88F5180N: 658 case MARVELL_ORION_1_88F5181: 659 case MARVELL_ORION_1_88F5182: 660 case MARVELL_ORION_1_88W8660: 661 case MARVELL_ORION_2_88F5281: 662 if (mva->mva_offset == MVSOC_PEX_BASE) { 663 mvpex_io_bs_tag = &orion_pex0_io_bs_tag; 664 mvpex_mem_bs_tag = &orion_pex0_mem_bs_tag; 665 arm32_mvpex_chipset = &arm32_mvpex0_chipset; 666 iotag = ORION_TAG_PEX0_IO; 667 memtag = ORION_TAG_PEX0_MEM; 668 } else { 669 mvpex_io_bs_tag = &orion_pex1_io_bs_tag; 670 mvpex_mem_bs_tag = &orion_pex1_mem_bs_tag; 671 arm32_mvpex_chipset = &arm32_mvpex1_chipset; 672 iotag = ORION_TAG_PEX1_IO; 673 memtag = ORION_TAG_PEX1_MEM; 674 } 675 break; 676 #endif 677 678 #ifdef KIRKWOOD 679 case MARVELL_KIRKWOOD_88F6282: 680 if (mva->mva_offset != MVSOC_PEX_BASE) { 681 mvpex_io_bs_tag = &kirkwood_pex1_io_bs_tag; 682 mvpex_mem_bs_tag = &kirkwood_pex1_mem_bs_tag; 683 arm32_mvpex_chipset = &arm32_mvpex1_chipset; 684 iotag = KIRKWOOD_TAG_PEX1_IO; 685 memtag = KIRKWOOD_TAG_PEX1_MEM; 686 break; 687 } 688 689 /* FALLTHROUGH */ 690 691 case MARVELL_KIRKWOOD_88F6180: 692 case MARVELL_KIRKWOOD_88F6192: 693 case MARVELL_KIRKWOOD_88F6281: 694 mvpex_io_bs_tag = &kirkwood_pex_io_bs_tag; 695 mvpex_mem_bs_tag = &kirkwood_pex_mem_bs_tag; 696 arm32_mvpex_chipset = &arm32_mvpex0_chipset; 697 iotag = KIRKWOOD_TAG_PEX_IO; 698 memtag = KIRKWOOD_TAG_PEX_MEM; 699 break; 700 #endif 701 702 #ifdef DOVE 703 case MARVELL_DOVE_88AP510: 704 if (mva->mva_offset == MVSOC_PEX_BASE) { 705 mvpex_io_bs_tag = &dove_pex0_io_bs_tag; 706 mvpex_mem_bs_tag = &dove_pex0_mem_bs_tag; 707 arm32_mvpex_chipset = &arm32_mvpex0_chipset; 708 iotag = DOVE_TAG_PEX0_IO; 709 memtag = DOVE_TAG_PEX0_MEM; 710 } else { 711 mvpex_io_bs_tag = &dove_pex1_io_bs_tag; 712 mvpex_mem_bs_tag = &dove_pex1_mem_bs_tag; 713 arm32_mvpex_chipset = &arm32_mvpex1_chipset; 714 iotag = DOVE_TAG_PEX1_IO; 715 memtag = DOVE_TAG_PEX1_MEM; 716 } 717 break; 718 #endif 719 720 #ifdef ARMADAXP 721 case MARVELL_ARMADAXP_MV78130: 722 case MARVELL_ARMADAXP_MV78160: 723 case MARVELL_ARMADAXP_MV78230: 724 case MARVELL_ARMADAXP_MV78260: 725 case MARVELL_ARMADAXP_MV78460: 726 727 case MARVELL_ARMADA370_MV6707: 728 case MARVELL_ARMADA370_MV6710: 729 case MARVELL_ARMADA370_MV6W11: 730 { 731 extern struct arm32_pci_chipset 732 arm32_mvpex2_chipset, arm32_mvpex3_chipset, 733 arm32_mvpex4_chipset, arm32_mvpex5_chipset; 734 const struct { 735 bus_size_t offset; 736 struct bus_space *io_bs_tag; 737 struct bus_space *mem_bs_tag; 738 struct arm32_pci_chipset *chipset; 739 int iotag; 740 int memtag; 741 } mvpex_tags[] = { 742 { MVSOC_PEX_BASE, 743 &armadaxp_pex00_io_bs_tag, 744 &armadaxp_pex00_mem_bs_tag, 745 &arm32_mvpex0_chipset, 746 ARMADAXP_TAG_PEX00_IO, 747 ARMADAXP_TAG_PEX00_MEM }, 748 749 { ARMADAXP_PEX01_BASE, 750 &armadaxp_pex01_io_bs_tag, 751 &armadaxp_pex01_mem_bs_tag, 752 &arm32_mvpex1_chipset, 753 ARMADAXP_TAG_PEX01_IO, 754 ARMADAXP_TAG_PEX01_MEM }, 755 756 { ARMADAXP_PEX02_BASE, 757 &armadaxp_pex02_io_bs_tag, 758 &armadaxp_pex02_mem_bs_tag, 759 &arm32_mvpex2_chipset, 760 ARMADAXP_TAG_PEX02_IO, 761 ARMADAXP_TAG_PEX02_MEM }, 762 763 { ARMADAXP_PEX03_BASE, 764 &armadaxp_pex03_io_bs_tag, 765 &armadaxp_pex03_mem_bs_tag, 766 &arm32_mvpex3_chipset, 767 ARMADAXP_TAG_PEX03_IO, 768 ARMADAXP_TAG_PEX03_MEM }, 769 770 { ARMADAXP_PEX2_BASE, 771 &armadaxp_pex2_io_bs_tag, 772 &armadaxp_pex2_mem_bs_tag, 773 &arm32_mvpex4_chipset, 774 ARMADAXP_TAG_PEX2_IO, 775 ARMADAXP_TAG_PEX2_MEM }, 776 777 { ARMADAXP_PEX3_BASE, 778 &armadaxp_pex3_io_bs_tag, 779 &armadaxp_pex3_mem_bs_tag, 780 &arm32_mvpex5_chipset, 781 ARMADAXP_TAG_PEX3_IO, 782 ARMADAXP_TAG_PEX3_MEM }, 783 784 { 0, 0, 0, 0, 0 }, 785 }; 786 787 for (i = 0; mvpex_tags[i].offset != 0; i++) { 788 if (mva->mva_offset != mvpex_tags[i].offset) 789 continue; 790 break; 791 } 792 if (mvpex_tags[i].offset == 0) 793 return; 794 mvpex_io_bs_tag = mvpex_tags[i].io_bs_tag; 795 mvpex_mem_bs_tag = mvpex_tags[i].mem_bs_tag; 796 arm32_mvpex_chipset = mvpex_tags[i].chipset; 797 iotag = mvpex_tags[i].iotag; 798 memtag = mvpex_tags[i].memtag; 799 break; 800 } 801 #endif 802 803 default: 804 return; 805 } 806 807 arm32_mvpex_chipset->pc_conf_v = device_private(dev); 808 arm32_mvpex_chipset->pc_intr_v = device_private(dev); 809 810 io_bs_tag = prop_data_create_data_nocopy( 811 mvpex_io_bs_tag, sizeof(struct bus_space)); 812 KASSERT(io_bs_tag != NULL); 813 prop_dictionary_set(dict, "io-bus-tag", io_bs_tag); 814 prop_object_release(io_bs_tag); 815 mem_bs_tag = prop_data_create_data_nocopy( 816 mvpex_mem_bs_tag, sizeof(struct bus_space)); 817 KASSERT(mem_bs_tag != NULL); 818 prop_dictionary_set(dict, "mem-bus-tag", mem_bs_tag); 819 prop_object_release(mem_bs_tag); 820 821 pc = prop_data_create_data_nocopy(arm32_mvpex_chipset, 822 sizeof(struct arm32_pci_chipset)); 823 KASSERT(pc != NULL); 824 prop_dictionary_set(dict, "pci-chipset", pc); 825 prop_object_release(pc); 826 827 marvell_startend_by_tag(iotag, &start, &end); 828 prop_dictionary_set_uint64(dict, "iostart", start); 829 prop_dictionary_set_uint64(dict, "ioend", end); 830 marvell_startend_by_tag(memtag, &start, &end); 831 prop_dictionary_set_uint64(dict, "memstart", start); 832 prop_dictionary_set_uint64(dict, "memend", end); 833 prop_dictionary_set_uint32(dict, 834 "cache-line-size", arm_dcache_align); 835 } 836 #endif 837 } 838 839 #if NGTPCI > 0 || NMVPEX > 0 840 static void 841 marvell_startend_by_tag(int tag, uint64_t *start, uint64_t *end) 842 { 843 uint32_t base, size; 844 int win; 845 846 win = mvsoc_target(tag, NULL, NULL, &base, &size); 847 if (size != 0) { 848 if (win < nremap) 849 *start = read_mlmbreg(MVSOC_MLMB_WRLR(win)) | 850 ((read_mlmbreg(MVSOC_MLMB_WRHR(win)) << 16) << 16); 851 else 852 *start = base; 853 *end = *start + size - 1; 854 } 855 } 856 #endif 857
Indexes created Thu Oct 02 14:10:14 GMT 2025