1 1.2 matt /* $Id: mpcsa_io.h,v 1.2 2008/07/03 01:15:39 matt Exp $ */ 2 1.2 matt 3 1.2 matt #ifndef _mpcsa_io_h_ 4 1.2 matt #define _mpcsa_io_h_ 1 5 1.2 matt 6 1.2 matt /* port A pins (bit numbers): */ 7 1.2 matt #define PA_RTSD 29U 8 1.2 matt #define PA_CTSD 28U 9 1.2 matt #define PA_GSMOFF 27U 10 1.2 matt #define PA_SCL 26U 11 1.2 matt #define PA_SDA 25U 12 1.2 matt #define PA_GSMON 24U 13 1.2 matt #define PA_EXP1 9U 14 1.2 matt #define PA_EXP0 8U 15 1.2 matt #define PA_TXD4 5U 16 1.2 matt #define PA_SPICS1 4U 17 1.2 matt #define PA_SPICS0 3U 18 1.2 matt #define PA_SPCK 2U 19 1.2 matt #define PA_MOSI 1U 20 1.2 matt #define PA_MISO 0U 21 1.2 matt 22 1.2 matt /* port B pins: */ 23 1.2 matt #define PB_CTS4 29U 24 1.2 matt #define PB_CTS3 28U 25 1.2 matt #define PB_CTS2 27U 26 1.2 matt #define PB_CTS1 26U 27 1.2 matt #define PB_RTS4 25U 28 1.2 matt #define PB_RTS3 24U 29 1.2 matt #define PB_RTS2 23U 30 1.2 matt #define PB_RTS1 22U 31 1.2 matt #define PB_DIN4 14U 32 1.2 matt #define PB_DIN3 13U 33 1.2 matt #define PB_DIN2 12U 34 1.2 matt #define PB_DIN1 11U 35 1.2 matt #define PB_RXD6 10U 36 1.2 matt #define PB_TXE6 9U 37 1.2 matt #define PB_TXE5 7U 38 1.2 matt #define PB_RXD5 6U 39 1.2 matt #define PB_S_RF 5U 40 1.2 matt #define PB_S_RK 4U 41 1.2 matt #define PB_S_RD 3U 42 1.2 matt #define PB_S_TD 2U 43 1.2 matt #define PB_S_TK 1U 44 1.2 matt #define PB_S_TF 0U 45 1.2 matt 46 1.2 matt /* port C pins: */ 47 1.2 matt #define PC_CFRESET 5U 48 1.2 matt #define PC_CFCD 4U 49 1.2 matt #define PC_CFIRQ 3U 50 1.2 matt #define PC_DSRD 1U 51 1.2 matt #define PC_DTRD 0U 52 1.2 matt 53 1.2 matt /* port D pins: */ 54 1.2 matt #define PD_DSR4 27U 55 1.2 matt #define PD_DSR3 26U 56 1.2 matt #define PD_DSR2 25U 57 1.2 matt #define PD_DSR1 24U 58 1.2 matt #define PD_DTR4 23U 59 1.2 matt #define PD_DTR3 22U 60 1.2 matt #define PD_DTR2 21U 61 1.2 matt #define PD_DTR1 20U 62 1.2 matt #define PD_SPICS2 19U 63 1.2 matt #define PD_DCD4 18U 64 1.2 matt #define PD_K702 17U 65 1.2 matt #define PD_K701 16U 66 1.2 matt #define PD_SW1 15U 67 1.2 matt #define PD_SW2 14U 68 1.2 matt #define PD_SW3 13U 69 1.2 matt #define PD_SW4 12U 70 1.2 matt #define PD_RESET_OUT 6U 71 1.2 matt 72 1.2 matt /* Leds behind SPI: */ 73 1.2 matt #define PSPI_ELED43 11U 74 1.2 matt #define PSPI_ELED33 10U 75 1.2 matt #define PSPI_ELED23 9U 76 1.2 matt #define PSPI_ELED13 8U 77 1.2 matt #define PSPI_RLED1 7U 78 1.2 matt #define PSPI_GLED2 6U 79 1.2 matt #define PSPI_GLED1 5U 80 1.2 matt #define PSPI_SLED5 4U 81 1.2 matt #define PSPI_SLED4 3U 82 1.2 matt #define PSPI_SLED3 2U 83 1.2 matt #define PSPI_SLED2 1U 84 1.2 matt #define PSPI_SLED1 0U 85 1.2 matt 86 1.2 matt 87 1.2 matt /* led numbers: */ 88 1.2 matt enum { 89 1.2 matt LED_SER1 = 1, 90 1.2 matt LED_SER2, 91 1.2 matt LED_SER3, 92 1.2 matt LED_SER4, 93 1.2 matt LED_SER5, 94 1.2 matt LED_SER_MAX = LED_SER5, 95 1.2 matt LED_GSM, 96 1.2 matt LED_GSM_LINK, 97 1.2 matt LED_HB, 98 1.2 matt LED_ETH1, 99 1.2 matt LED_ETH2, 100 1.2 matt LED_ETH3, 101 1.2 matt LED_ETH4, 102 1.2 matt LED_MAX 103 1.2 matt }; 104 1.2 matt 105 1.2 matt #define NUM_ETH_PORTS 4 // amount of ethernet ports 106 1.2 matt 107 1.2 matt #endif /* _mpcsa_io_h_ */ 108