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smdk2800_ram_init.S revision 1.1.4.2 
      1  1.1.4.2  skrll /* $NetBSD: smdk2800_ram_init.S,v 1.1.4.2 2004/08/03 10:34:08 skrll Exp $	*/
      2  1.1.4.2  skrll 
      3  1.1.4.2  skrll /*
      4  1.1.4.2  skrll  * Copyright (c) 2002, 2003 Fujitsu Component Limited
      5  1.1.4.2  skrll  * Copyright (c) 2002, 2003 Genetec Corporation
      6  1.1.4.2  skrll  * All rights reserved.
      7  1.1.4.2  skrll  *
      8  1.1.4.2  skrll  * Redistribution and use in source and binary forms, with or without
      9  1.1.4.2  skrll  * modification, are permitted provided that the following conditions
     10  1.1.4.2  skrll  * are met:
     11  1.1.4.2  skrll  * 1. Redistributions of source code must retain the above copyright
     12  1.1.4.2  skrll  *    notice, this list of conditions and the following disclaimer.
     13  1.1.4.2  skrll  * 2. Redistributions in binary form must reproduce the above copyright
     14  1.1.4.2  skrll  *    notice, this list of conditions and the following disclaimer in the
     15  1.1.4.2  skrll  *    documentation and/or other materials provided with the distribution.
     16  1.1.4.2  skrll  * 3. Neither the name of The Fujitsu Component Limited nor the name of
     17  1.1.4.2  skrll  *    Genetec corporation may not be used to endorse or promote products
     18  1.1.4.2  skrll  *    derived from this software without specific prior written permission.
     19  1.1.4.2  skrll  *
     20  1.1.4.2  skrll  * THIS SOFTWARE IS PROVIDED BY FUJITSU COMPONENT LIMITED AND GENETEC
     21  1.1.4.2  skrll  * CORPORATION ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES,
     22  1.1.4.2  skrll  * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
     23  1.1.4.2  skrll  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
     24  1.1.4.2  skrll  * DISCLAIMED.  IN NO EVENT SHALL FUJITSU COMPONENT LIMITED OR GENETEC
     25  1.1.4.2  skrll  * CORPORATION BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
     26  1.1.4.2  skrll  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
     27  1.1.4.2  skrll  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
     28  1.1.4.2  skrll  * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
     29  1.1.4.2  skrll  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
     30  1.1.4.2  skrll  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
     31  1.1.4.2  skrll  * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
     32  1.1.4.2  skrll  * SUCH DAMAGE.
     33  1.1.4.2  skrll  */
     34  1.1.4.2  skrll 
     35  1.1.4.2  skrll #include <machine/asm.h>
     36  1.1.4.2  skrll #include <arm/armreg.h>
     37  1.1.4.2  skrll #include <arm/s3c2xx0/s3c2800reg.h>
     38  1.1.4.2  skrll 
     39  1.1.4.2  skrll ENTRY(smdk2800_ram_init)
     40  1.1.4.2  skrll 	/* Initialize memory controller */
     41  1.1.4.2  skrll 	adr	r0, Lmemctl_initial_data
     42  1.1.4.2  skrll 	ldr	r1, [r0], #4
     43  1.1.4.2  skrll 	adr	r2, Lmemctl_initial_data_end
     44  1.1.4.2  skrll 1:
     45  1.1.4.2  skrll 	ldr	r3, [r0], #4
     46  1.1.4.2  skrll 	str	r3, [r1], #4
     47  1.1.4.2  skrll 	cmp	r0, r2
     48  1.1.4.2  skrll 	blo	1b
     49  1.1.4.2  skrll 
     50  1.1.4.2  skrll 	mov	pc,lr
     51  1.1.4.2  skrll 
     52  1.1.4.2  skrll #define REFRESH_INIT		(REFRESH_REFEN | \
     53  1.1.4.2  skrll 				(0x0<<20) | \
     54  1.1.4.2  skrll 				(0x3<<16) | \
     55  1.1.4.2  skrll 				(0x0<<12) | \
     56  1.1.4.2  skrll 				(0x1e9))
     57  1.1.4.2  skrll #define DMTMCON_INIT		((0x2<<16) | \
     58  1.1.4.2  skrll 				(0x3<<10) | \
     59  1.1.4.2  skrll 				(0x1<<8) | \
     60  1.1.4.2  skrll 				(0x1<<6) | \
     61  1.1.4.2  skrll 				(0x1<<4) | \
     62  1.1.4.2  skrll 				(0x1<<2) | \
     63  1.1.4.2  skrll 				(0x1))
     64  1.1.4.2  skrll 
     65  1.1.4.2  skrll #define	SMBCON_VAL(ws,st,tacs,tcoc,toch,tacc,tcah,sdw) \
     66  1.1.4.2  skrll 	((ws) | (st) |                                 \
     67  1.1.4.2  skrll 	 ((tacs)<<SMBCON_TACS_SHIFT) | ((tcoc)<<SMBCON_TCOS_SHIFT) |  \
     68  1.1.4.2  skrll 	 ((toch)<<SMBCON_TOCH_SHIFT) | ((tacc)<<SMBCON_TACC_SHIFT) |  \
     69  1.1.4.2  skrll 	 ((tcah)<<SMBCON_TCAH_SHIFT) | (sdw))
     70  1.1.4.2  skrll 
     71  1.1.4.2  skrll Lmemctl_initial_data:
     72  1.1.4.2  skrll 	.word	S3C2800_MEMCTL_BASE + MEMCTL_SMBCON0	    /* address */
     73  1.1.4.2  skrll 	.word	SMBCON_VAL(0,0,0,0,0,0x0a,0,SMBCON_SDW_32BIT) /* SMBCON0 */
     74  1.1.4.2  skrll 	.word	SMBCON_VAL(0,0,0,0,0,0x0a,0,SMBCON_SDW_16BIT) /* SMBCON1 */
     75  1.1.4.2  skrll 	.word	SMBCON_VAL(0,0,0,0,0,0x0a,0,SMBCON_SDW_32BIT) /* SMBCON2 */
     76  1.1.4.2  skrll 	.word	SMBCON_VAL(0,0,0,0,0,0x0a,0,SMBCON_SDW_32BIT) /* SMBCON3 */
     77  1.1.4.2  skrll 	.word	REFRESH_INIT
     78  1.1.4.2  skrll 	.word	DMTMCON_INIT
     79  1.1.4.2  skrll 	.word	0x3<<MRSR_CL_SHIFT			    /* MRSR */
     80  1.1.4.2  skrll Lmemctl_initial_data_end:
     81