emi_prep.c revision 1.2.2.2
1 1.2.2.2 yamt /* $Id: emi_prep.c,v 1.2.2.2 2013/01/16 05:32:56 yamt Exp $ */ 2 1.2.2.2 yamt 3 1.2.2.2 yamt /* 4 1.2.2.2 yamt * Copyright (c) 2012 The NetBSD Foundation, Inc. 5 1.2.2.2 yamt * All rights reserved. 6 1.2.2.2 yamt * 7 1.2.2.2 yamt * This code is derived from software contributed to The NetBSD Foundation 8 1.2.2.2 yamt * by Petri Laakso. 9 1.2.2.2 yamt * 10 1.2.2.2 yamt * Redistribution and use in source and binary forms, with or without 11 1.2.2.2 yamt * modification, are permitted provided that the following conditions 12 1.2.2.2 yamt * are met: 13 1.2.2.2 yamt * 1. Redistributions of source code must retain the above copyright 14 1.2.2.2 yamt * notice, this list of conditions and the following disclaimer. 15 1.2.2.2 yamt * 2. Redistributions in binary form must reproduce the above copyright 16 1.2.2.2 yamt * notice, this list of conditions and the following disclaimer in the 17 1.2.2.2 yamt * documentation and/or other materials provided with the distribution. 18 1.2.2.2 yamt * 19 1.2.2.2 yamt * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 1.2.2.2 yamt * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 1.2.2.2 yamt * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 1.2.2.2 yamt * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 1.2.2.2 yamt * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 1.2.2.2 yamt * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 1.2.2.2 yamt * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 1.2.2.2 yamt * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 1.2.2.2 yamt * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 1.2.2.2 yamt * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 1.2.2.2 yamt * POSSIBILITY OF SUCH DAMAGE. 30 1.2.2.2 yamt */ 31 1.2.2.2 yamt 32 1.2.2.2 yamt #include <sys/param.h> 33 1.2.2.2 yamt #include <sys/cdefs.h> 34 1.2.2.2 yamt #include <sys/types.h> 35 1.2.2.2 yamt 36 1.2.2.2 yamt #include <arm/imx/imx23_emireg.h> 37 1.2.2.2 yamt 38 1.2.2.2 yamt #include <lib/libsa/stand.h> 39 1.2.2.2 yamt 40 1.2.2.2 yamt #include "common.h" 41 1.2.2.2 yamt 42 1.2.2.2 yamt void init_dram_registers(void); 43 1.2.2.2 yamt void start_dram(void); 44 1.2.2.2 yamt uint32_t get_dram_int_status(void); 45 1.2.2.2 yamt 46 1.2.2.2 yamt /* 47 1.2.2.2 yamt * Initialize external DRAM memory. 48 1.2.2.2 yamt */ 49 1.2.2.2 yamt int 50 1.2.2.2 yamt emi_prep(void) 51 1.2.2.2 yamt { 52 1.2.2.2 yamt 53 1.2.2.2 yamt init_dram_registers(); 54 1.2.2.2 yamt start_dram(); 55 1.2.2.2 yamt 56 1.2.2.2 yamt return 0; 57 1.2.2.2 yamt } 58 1.2.2.2 yamt 59 1.2.2.2 yamt /* 60 1.2.2.2 yamt * DRAM register values for 32Mx16 hy5du121622dtp-d43 DDR module. 61 1.2.2.2 yamt * 62 1.2.2.2 yamt * Register values were copied from Freescale's imx-bootlets-src-10.05.02 63 1.2.2.2 yamt * source code, init_ddr_mt46v32m16_133Mhz() function. Only change to those 64 1.2.2.2 yamt * settings were to HW_DRAM_CTL19_DQS_OUT_SHIFT which was set to 16 as a result 65 1.2.2.2 yamt * from trial and error. 66 1.2.2.2 yamt */ 67 1.2.2.2 yamt void 68 1.2.2.2 yamt init_dram_registers(void) 69 1.2.2.2 yamt { 70 1.2.2.2 yamt uint32_t reg; 71 1.2.2.2 yamt 72 1.2.2.2 yamt REG_WRITE(HW_DRAM_BASE + HW_DRAM_CTL00, 0x01010001); 73 1.2.2.2 yamt REG_WRITE(HW_DRAM_BASE + HW_DRAM_CTL01, 0x00010100); 74 1.2.2.2 yamt REG_WRITE(HW_DRAM_BASE + HW_DRAM_CTL02, 0x01000101); 75 1.2.2.2 yamt REG_WRITE(HW_DRAM_BASE + HW_DRAM_CTL03, 0x00000001); 76 1.2.2.2 yamt REG_WRITE(HW_DRAM_BASE + HW_DRAM_CTL04, 0x00000101); 77 1.2.2.2 yamt REG_WRITE(HW_DRAM_BASE + HW_DRAM_CTL05, 0x00000000); 78 1.2.2.2 yamt REG_WRITE(HW_DRAM_BASE + HW_DRAM_CTL06, 0x00010000); 79 1.2.2.2 yamt REG_WRITE(HW_DRAM_BASE + HW_DRAM_CTL07, 0x01000001); 80 1.2.2.2 yamt // HW_DRAM_CTL08 initialized last. 81 1.2.2.2 yamt REG_WRITE(HW_DRAM_BASE + HW_DRAM_CTL09, 0x00000001); 82 1.2.2.2 yamt REG_WRITE(HW_DRAM_BASE + HW_DRAM_CTL10, 0x07000200); 83 1.2.2.2 yamt REG_WRITE(HW_DRAM_BASE + HW_DRAM_CTL11, 0x00070202); 84 1.2.2.2 yamt REG_WRITE(HW_DRAM_BASE + HW_DRAM_CTL12, 0x02020000); 85 1.2.2.2 yamt REG_WRITE(HW_DRAM_BASE + HW_DRAM_CTL13, 0x04040a01); 86 1.2.2.2 yamt REG_WRITE(HW_DRAM_BASE + HW_DRAM_CTL14, 0x00000201); 87 1.2.2.2 yamt REG_WRITE(HW_DRAM_BASE + HW_DRAM_CTL15, 0x02040000); 88 1.2.2.2 yamt REG_WRITE(HW_DRAM_BASE + HW_DRAM_CTL16, 0x02000000); 89 1.2.2.2 yamt REG_WRITE(HW_DRAM_BASE + HW_DRAM_CTL17, 0x19000f08); 90 1.2.2.2 yamt REG_WRITE(HW_DRAM_BASE + HW_DRAM_CTL18, 0x0d0d0000); 91 1.2.2.2 yamt // REG_WRITE(HW_DRAM_BASE + HW_DRAM_CTL19, 0x02021313); 92 1.2.2.2 yamt reg = __SHIFTIN(2, HW_DRAM_CTL19_DQS_OUT_SHIFT_BYPASS) | 93 1.2.2.2 yamt __SHIFTIN(16, HW_DRAM_CTL19_DQS_OUT_SHIFT) | 94 1.2.2.2 yamt __SHIFTIN(19, HW_DRAM_CTL19_DLL_DQS_DELAY_BYPASS_1) | 95 1.2.2.2 yamt __SHIFTIN(19, HW_DRAM_CTL19_DLL_DQS_DELAY_BYPASS_0); 96 1.2.2.2 yamt REG_WRITE(HW_DRAM_BASE + HW_DRAM_CTL19, reg); 97 1.2.2.2 yamt REG_WRITE(HW_DRAM_BASE + HW_DRAM_CTL20, 0x02061521); 98 1.2.2.2 yamt REG_WRITE(HW_DRAM_BASE + HW_DRAM_CTL21, 0x0000000a); 99 1.2.2.2 yamt REG_WRITE(HW_DRAM_BASE + HW_DRAM_CTL22, 0x00080008); 100 1.2.2.2 yamt REG_WRITE(HW_DRAM_BASE + HW_DRAM_CTL23, 0x00200020); 101 1.2.2.2 yamt REG_WRITE(HW_DRAM_BASE + HW_DRAM_CTL24, 0x00200020); 102 1.2.2.2 yamt REG_WRITE(HW_DRAM_BASE + HW_DRAM_CTL25, 0x00200020); 103 1.2.2.2 yamt REG_WRITE(HW_DRAM_BASE + HW_DRAM_CTL26, 0x000003f7); 104 1.2.2.2 yamt // HW_DRAM_CTL27 105 1.2.2.2 yamt // HW_DRAM_CTL28 106 1.2.2.2 yamt REG_WRITE(HW_DRAM_BASE + HW_DRAM_CTL29, 0x00000020); 107 1.2.2.2 yamt REG_WRITE(HW_DRAM_BASE + HW_DRAM_CTL30, 0x00000020); 108 1.2.2.2 yamt REG_WRITE(HW_DRAM_BASE + HW_DRAM_CTL31, 0x00c80000); 109 1.2.2.2 yamt REG_WRITE(HW_DRAM_BASE + HW_DRAM_CTL32, 0x000a23cd); 110 1.2.2.2 yamt REG_WRITE(HW_DRAM_BASE + HW_DRAM_CTL33, 0x000000c8); 111 1.2.2.2 yamt REG_WRITE(HW_DRAM_BASE + HW_DRAM_CTL34, 0x00006665); 112 1.2.2.2 yamt // HW_DRAM_CTL35 is read only register 113 1.2.2.2 yamt REG_WRITE(HW_DRAM_BASE + HW_DRAM_CTL36, 0x00000101); 114 1.2.2.2 yamt REG_WRITE(HW_DRAM_BASE + HW_DRAM_CTL37, 0x00040001); 115 1.2.2.2 yamt REG_WRITE(HW_DRAM_BASE + HW_DRAM_CTL38, 0x00000000); 116 1.2.2.2 yamt REG_WRITE(HW_DRAM_BASE + HW_DRAM_CTL39, 0x00000000); 117 1.2.2.2 yamt REG_WRITE(HW_DRAM_BASE + HW_DRAM_CTL40, 0x00010000); 118 1.2.2.2 yamt REG_WRITE(HW_DRAM_BASE + HW_DRAM_CTL08, 0x01000000); 119 1.2.2.2 yamt 120 1.2.2.2 yamt return; 121 1.2.2.2 yamt } 122 1.2.2.2 yamt 123 1.2.2.2 yamt /* 124 1.2.2.2 yamt * Start DRAM module. After return DRAM is ready to use. 125 1.2.2.2 yamt */ 126 1.2.2.2 yamt void 127 1.2.2.2 yamt start_dram(void) 128 1.2.2.2 yamt { 129 1.2.2.2 yamt uint32_t reg; 130 1.2.2.2 yamt 131 1.2.2.2 yamt reg = REG_READ(HW_DRAM_BASE + HW_DRAM_CTL08); 132 1.2.2.2 yamt reg |= HW_DRAM_CTL08_START; 133 1.2.2.2 yamt REG_WRITE(HW_DRAM_BASE + HW_DRAM_CTL08, reg); 134 1.2.2.2 yamt 135 1.2.2.2 yamt /* Wait until DRAM initialization is complete. */ 136 1.2.2.2 yamt while(!(get_dram_int_status() & (1<<2))); 137 1.2.2.2 yamt 138 1.2.2.2 yamt return; 139 1.2.2.2 yamt } 140 1.2.2.2 yamt 141 1.2.2.2 yamt /* 142 1.2.2.2 yamt * Return DRAM controller interrupt status register. 143 1.2.2.2 yamt */ 144 1.2.2.2 yamt uint32_t 145 1.2.2.2 yamt get_dram_int_status(void) 146 1.2.2.2 yamt { 147 1.2.2.2 yamt uint32_t reg; 148 1.2.2.2 yamt 149 1.2.2.2 yamt reg = REG_READ(HW_DRAM_BASE + HW_DRAM_CTL18); 150 1.2.2.2 yamt return __SHIFTOUT(reg, HW_DRAM_CTL18_INT_STATUS); 151 1.2.2.2 yamt } 152
Indexes created Tue Oct 21 19:09:51 GMT 2025