emi_prep.c revision 1.1
1 /* $Id: emi_prep.c,v 1.1 2012/11/20 19:08:46 jkunz Exp $ */ 2 3 /* 4 * Copyright (c) 2012 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Petri Laakso. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/param.h> 33 #include <sys/cdefs.h> 34 #include <sys/types.h> 35 36 #include <arm/imx/imx23_emireg.h> 37 38 #include <lib/libsa/stand.h> 39 40 #include "common.h" 41 42 void init_dram_registers(void); 43 void start_dram(void); 44 uint32_t get_dram_int_status(void); 45 46 /* 47 * Initialize external DRAM memory. 48 */ 49 int 50 emi_prep(void) 51 { 52 53 init_dram_registers(); 54 start_dram(); 55 56 return 0; 57 } 58 59 /* 60 * DRAM register values for 32Mx16 hy5du121622dtp-d43 DDR module. 61 * 62 * Register values were copied from Freescale's imx-bootlets-src-10.05.02 63 * source code, init_ddr_mt46v32m16_133Mhz() function. Only change to those 64 * settings were to HW_DRAM_CTL19_DQS_OUT_SHIFT which was set to 16 as a result 65 * from trial and error. 66 */ 67 void 68 init_dram_registers(void) 69 { 70 uint32_t reg; 71 72 REG_WRITE(HW_DRAM_BASE + HW_DRAM_CTL00, 0x01010001); 73 REG_WRITE(HW_DRAM_BASE + HW_DRAM_CTL01, 0x00010100); 74 REG_WRITE(HW_DRAM_BASE + HW_DRAM_CTL02, 0x01000101); 75 REG_WRITE(HW_DRAM_BASE + HW_DRAM_CTL03, 0x00000001); 76 REG_WRITE(HW_DRAM_BASE + HW_DRAM_CTL04, 0x00000101); 77 REG_WRITE(HW_DRAM_BASE + HW_DRAM_CTL05, 0x00000000); 78 REG_WRITE(HW_DRAM_BASE + HW_DRAM_CTL06, 0x00010000); 79 REG_WRITE(HW_DRAM_BASE + HW_DRAM_CTL07, 0x01000001); 80 // HW_DRAM_CTL08 initialized last. 81 REG_WRITE(HW_DRAM_BASE + HW_DRAM_CTL09, 0x00000001); 82 REG_WRITE(HW_DRAM_BASE + HW_DRAM_CTL10, 0x07000200); 83 REG_WRITE(HW_DRAM_BASE + HW_DRAM_CTL11, 0x00070202); 84 REG_WRITE(HW_DRAM_BASE + HW_DRAM_CTL12, 0x02020000); 85 REG_WRITE(HW_DRAM_BASE + HW_DRAM_CTL13, 0x04040a01); 86 REG_WRITE(HW_DRAM_BASE + HW_DRAM_CTL14, 0x00000201); 87 REG_WRITE(HW_DRAM_BASE + HW_DRAM_CTL15, 0x02040000); 88 REG_WRITE(HW_DRAM_BASE + HW_DRAM_CTL16, 0x02000000); 89 REG_WRITE(HW_DRAM_BASE + HW_DRAM_CTL17, 0x19000f08); 90 REG_WRITE(HW_DRAM_BASE + HW_DRAM_CTL18, 0x0d0d0000); 91 // REG_WRITE(HW_DRAM_BASE + HW_DRAM_CTL19, 0x02021313); 92 reg = __SHIFTIN(2, HW_DRAM_CTL19_DQS_OUT_SHIFT_BYPASS) | 93 __SHIFTIN(16, HW_DRAM_CTL19_DQS_OUT_SHIFT) | 94 __SHIFTIN(19, HW_DRAM_CTL19_DLL_DQS_DELAY_BYPASS_1) | 95 __SHIFTIN(19, HW_DRAM_CTL19_DLL_DQS_DELAY_BYPASS_0); 96 REG_WRITE(HW_DRAM_BASE + HW_DRAM_CTL19, reg); 97 REG_WRITE(HW_DRAM_BASE + HW_DRAM_CTL20, 0x02061521); 98 REG_WRITE(HW_DRAM_BASE + HW_DRAM_CTL21, 0x0000000a); 99 REG_WRITE(HW_DRAM_BASE + HW_DRAM_CTL22, 0x00080008); 100 REG_WRITE(HW_DRAM_BASE + HW_DRAM_CTL23, 0x00200020); 101 REG_WRITE(HW_DRAM_BASE + HW_DRAM_CTL24, 0x00200020); 102 REG_WRITE(HW_DRAM_BASE + HW_DRAM_CTL25, 0x00200020); 103 REG_WRITE(HW_DRAM_BASE + HW_DRAM_CTL26, 0x000003f7); 104 // HW_DRAM_CTL27 105 // HW_DRAM_CTL28 106 REG_WRITE(HW_DRAM_BASE + HW_DRAM_CTL29, 0x00000020); 107 REG_WRITE(HW_DRAM_BASE + HW_DRAM_CTL30, 0x00000020); 108 REG_WRITE(HW_DRAM_BASE + HW_DRAM_CTL31, 0x00c80000); 109 REG_WRITE(HW_DRAM_BASE + HW_DRAM_CTL32, 0x000a23cd); 110 REG_WRITE(HW_DRAM_BASE + HW_DRAM_CTL33, 0x000000c8); 111 REG_WRITE(HW_DRAM_BASE + HW_DRAM_CTL34, 0x00006665); 112 // HW_DRAM_CTL35 is read only register 113 REG_WRITE(HW_DRAM_BASE + HW_DRAM_CTL36, 0x00000101); 114 REG_WRITE(HW_DRAM_BASE + HW_DRAM_CTL37, 0x00040001); 115 REG_WRITE(HW_DRAM_BASE + HW_DRAM_CTL38, 0x00000000); 116 REG_WRITE(HW_DRAM_BASE + HW_DRAM_CTL39, 0x00000000); 117 REG_WRITE(HW_DRAM_BASE + HW_DRAM_CTL40, 0x00010000); 118 REG_WRITE(HW_DRAM_BASE + HW_DRAM_CTL08, 0x01000000); 119 120 return; 121 } 122 123 /* 124 * Start DRAM module. After return DRAM is ready to use. 125 */ 126 void 127 start_dram(void) 128 { 129 uint32_t reg; 130 131 reg = REG_READ(HW_DRAM_BASE + HW_DRAM_CTL08); 132 reg |= HW_DRAM_CTL08_START; 133 REG_WRITE(HW_DRAM_BASE + HW_DRAM_CTL08, reg); 134 135 /* Wait until DRAM initialization is complete. */ 136 while(!(get_dram_int_status() & (1<<2))); 137 138 return; 139 } 140 141 /* 142 * Return DRAM controller interrupt status register. 143 */ 144 uint32_t 145 get_dram_int_status(void) 146 { 147 uint32_t reg; 148 149 reg = REG_READ(HW_DRAM_BASE + HW_DRAM_CTL18); 150 return __SHIFTOUT(reg, HW_DRAM_CTL18_INT_STATUS); 151 } 152
Indexes created Fri Sep 26 08:10:20 GMT 2025