pinctrl_prep.c revision 1.2.2.2
1 1.2.2.2 yamt /* $Id: pinctrl_prep.c,v 1.2.2.2 2013/01/16 05:32:56 yamt Exp $ */ 2 1.2.2.2 yamt 3 1.2.2.2 yamt /* 4 1.2.2.2 yamt * Copyright (c) 2012 The NetBSD Foundation, Inc. 5 1.2.2.2 yamt * All rights reserved. 6 1.2.2.2 yamt * 7 1.2.2.2 yamt * This code is derived from software contributed to The NetBSD Foundation 8 1.2.2.2 yamt * by Petri Laakso. 9 1.2.2.2 yamt * 10 1.2.2.2 yamt * Redistribution and use in source and binary forms, with or without 11 1.2.2.2 yamt * modification, are permitted provided that the following conditions 12 1.2.2.2 yamt * are met: 13 1.2.2.2 yamt * 1. Redistributions of source code must retain the above copyright 14 1.2.2.2 yamt * notice, this list of conditions and the following disclaimer. 15 1.2.2.2 yamt * 2. Redistributions in binary form must reproduce the above copyright 16 1.2.2.2 yamt * notice, this list of conditions and the following disclaimer in the 17 1.2.2.2 yamt * documentation and/or other materials provided with the distribution. 18 1.2.2.2 yamt * 19 1.2.2.2 yamt * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 1.2.2.2 yamt * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 1.2.2.2 yamt * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 1.2.2.2 yamt * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 1.2.2.2 yamt * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 1.2.2.2 yamt * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 1.2.2.2 yamt * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 1.2.2.2 yamt * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 1.2.2.2 yamt * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 1.2.2.2 yamt * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 1.2.2.2 yamt * POSSIBILITY OF SUCH DAMAGE. 30 1.2.2.2 yamt */ 31 1.2.2.2 yamt 32 1.2.2.2 yamt #include <sys/param.h> 33 1.2.2.2 yamt #include <sys/cdefs.h> 34 1.2.2.2 yamt #include <sys/types.h> 35 1.2.2.2 yamt 36 1.2.2.2 yamt #include <arm/imx/imx23_pinctrlreg.h> 37 1.2.2.2 yamt 38 1.2.2.2 yamt #include <lib/libsa/stand.h> 39 1.2.2.2 yamt 40 1.2.2.2 yamt #include "common.h" 41 1.2.2.2 yamt 42 1.2.2.2 yamt void configure_emi_mux(void); 43 1.2.2.2 yamt void configure_emi_drive(int); 44 1.2.2.2 yamt void disable_emi_padkeepers(void); 45 1.2.2.2 yamt void configure_ssp_mux(); 46 1.2.2.2 yamt void configure_ssp_drive(int); 47 1.2.2.2 yamt void configure_ssp_pullups(void); 48 1.2.2.2 yamt 49 1.2.2.2 yamt /* EMI pins output drive strengths */ 50 1.2.2.2 yamt #define DRIVE_04_MA 0x0 /* 4 mA */ 51 1.2.2.2 yamt #define DRIVE_08_MA 0x1 /* 8 mA */ 52 1.2.2.2 yamt #define DRIVE_12_MA 0x2 /* 12 mA */ 53 1.2.2.2 yamt #define DRIVE_16_MA 0x3 /* 16 mA */ 54 1.2.2.2 yamt 55 1.2.2.2 yamt /* 56 1.2.2.2 yamt * Configure external EMI pins. 57 1.2.2.2 yamt */ 58 1.2.2.2 yamt int 59 1.2.2.2 yamt pinctrl_prep(void) 60 1.2.2.2 yamt { 61 1.2.2.2 yamt 62 1.2.2.2 yamt REG_WRITE(HW_PINCTRL_BASE + HW_PINCTRL_CTRL_CLR, 63 1.2.2.2 yamt (HW_PINCTRL_CTRL_SFTRST | HW_PINCTRL_CTRL_CLKGATE)); 64 1.2.2.2 yamt 65 1.2.2.2 yamt /* EMI. */ 66 1.2.2.2 yamt configure_emi_mux(); 67 1.2.2.2 yamt configure_emi_drive(DRIVE_12_MA); 68 1.2.2.2 yamt disable_emi_padkeepers(); 69 1.2.2.2 yamt 70 1.2.2.2 yamt /* SSP. */ 71 1.2.2.2 yamt configure_ssp_mux(); 72 1.2.2.2 yamt configure_ssp_drive(DRIVE_16_MA); 73 1.2.2.2 yamt configure_ssp_pullups(); 74 1.2.2.2 yamt 75 1.2.2.2 yamt return 0; 76 1.2.2.2 yamt } 77 1.2.2.2 yamt 78 1.2.2.2 yamt /* 79 1.2.2.2 yamt * Configure external EMI pins to be used for DRAM. 80 1.2.2.2 yamt */ 81 1.2.2.2 yamt void 82 1.2.2.2 yamt configure_emi_mux(void) 83 1.2.2.2 yamt { 84 1.2.2.2 yamt 85 1.2.2.2 yamt REG_WRITE(HW_PINCTRL_BASE + HW_PINCTRL_MUXSEL4_CLR, ( 86 1.2.2.2 yamt HW_PINCTRL_MUXSEL4_BANK2_PIN15 | /* Pin 108, EMI_A06 */ 87 1.2.2.2 yamt HW_PINCTRL_MUXSEL4_BANK2_PIN14 | /* Pin 107, EMI_A05 */ 88 1.2.2.2 yamt HW_PINCTRL_MUXSEL4_BANK2_PIN13 | /* Pin 109, EMI_A04 */ 89 1.2.2.2 yamt HW_PINCTRL_MUXSEL4_BANK2_PIN12 | /* Pin 110, EMI_A03 */ 90 1.2.2.2 yamt HW_PINCTRL_MUXSEL4_BANK2_PIN11 | /* Pin 111, EMI_A02 */ 91 1.2.2.2 yamt HW_PINCTRL_MUXSEL4_BANK2_PIN10 | /* Pin 112, EMI_A01 */ 92 1.2.2.2 yamt HW_PINCTRL_MUXSEL4_BANK2_PIN09) /* Pin 113, EMI_A00 */ 93 1.2.2.2 yamt ); 94 1.2.2.2 yamt 95 1.2.2.2 yamt REG_WRITE(HW_PINCTRL_BASE + HW_PINCTRL_MUXSEL5_CLR, ( 96 1.2.2.2 yamt HW_PINCTRL_MUXSEL5_BANK2_PIN31 | /* Pin 114, EMI_WEN */ 97 1.2.2.2 yamt HW_PINCTRL_MUXSEL5_BANK2_PIN30 | /* Pin 98, EMI_RASN */ 98 1.2.2.2 yamt HW_PINCTRL_MUXSEL5_BANK2_PIN29 | /* Pin 115, EMI_CKE */ 99 1.2.2.2 yamt #if 0 100 1.2.2.2 yamt /* 169-Pin BGA Package */ 101 1.2.2.2 yamt HW_PINCTRL_MUXSEL5_BANK2_PIN26 | /* Pin 99, EMI_CE1N */ 102 1.2.2.2 yamt #endif 103 1.2.2.2 yamt HW_PINCTRL_MUXSEL5_BANK2_PIN25 | /* Pin 100, EMI_CE0N */ 104 1.2.2.2 yamt HW_PINCTRL_MUXSEL5_BANK2_PIN24 | /* Pin 97, EMI_CASN */ 105 1.2.2.2 yamt HW_PINCTRL_MUXSEL5_BANK2_PIN23 | /* Pin 117, EMI_BA1 */ 106 1.2.2.2 yamt HW_PINCTRL_MUXSEL5_BANK2_PIN22 | /* Pin 116, EMI_BA0 */ 107 1.2.2.2 yamt HW_PINCTRL_MUXSEL5_BANK2_PIN21 | /* Pin 101, EMI_A12 */ 108 1.2.2.2 yamt HW_PINCTRL_MUXSEL5_BANK2_PIN20 | /* Pin 102, EMI_A11 */ 109 1.2.2.2 yamt HW_PINCTRL_MUXSEL5_BANK2_PIN19 | /* Pin 104, EMI_A10 */ 110 1.2.2.2 yamt HW_PINCTRL_MUXSEL5_BANK2_PIN18 | /* Pin 103, EMI_A09 */ 111 1.2.2.2 yamt HW_PINCTRL_MUXSEL5_BANK2_PIN17 | /* Pin 106, EMI_A08 */ 112 1.2.2.2 yamt HW_PINCTRL_MUXSEL5_BANK2_PIN16) /* Pin 105, EMI_A07 */ 113 1.2.2.2 yamt ); 114 1.2.2.2 yamt 115 1.2.2.2 yamt REG_WRITE(HW_PINCTRL_BASE + HW_PINCTRL_MUXSEL6_CLR, ( 116 1.2.2.2 yamt HW_PINCTRL_MUXSEL6_BANK3_PIN15 | /* Pin 95, EMI_D15 */ 117 1.2.2.2 yamt HW_PINCTRL_MUXSEL6_BANK3_PIN14 | /* Pin 96, EMI_D14 */ 118 1.2.2.2 yamt HW_PINCTRL_MUXSEL6_BANK3_PIN13 | /* Pin 94, EMI_D13 */ 119 1.2.2.2 yamt HW_PINCTRL_MUXSEL6_BANK3_PIN12 | /* Pin 93, EMI_D12 */ 120 1.2.2.2 yamt HW_PINCTRL_MUXSEL6_BANK3_PIN11 | /* Pin 91, EMI_D11 */ 121 1.2.2.2 yamt HW_PINCTRL_MUXSEL6_BANK3_PIN10 | /* Pin 89, EMI_D10 */ 122 1.2.2.2 yamt HW_PINCTRL_MUXSEL6_BANK3_PIN09 | /* Pin 87, EMI_D09 */ 123 1.2.2.2 yamt HW_PINCTRL_MUXSEL6_BANK3_PIN08 | /* Pin 86, EMI_D08 */ 124 1.2.2.2 yamt HW_PINCTRL_MUXSEL6_BANK3_PIN07 | /* Pin 85, EMI_D07 */ 125 1.2.2.2 yamt HW_PINCTRL_MUXSEL6_BANK3_PIN06 | /* Pin 84, EMI_D06 */ 126 1.2.2.2 yamt HW_PINCTRL_MUXSEL6_BANK3_PIN05 | /* Pin 83, EMI_D05 */ 127 1.2.2.2 yamt HW_PINCTRL_MUXSEL6_BANK3_PIN04 | /* Pin 82, EMI_D04 */ 128 1.2.2.2 yamt HW_PINCTRL_MUXSEL6_BANK3_PIN03 | /* Pin 79, EMI_D03 */ 129 1.2.2.2 yamt HW_PINCTRL_MUXSEL6_BANK3_PIN02 | /* Pin 77, EMI_D02 */ 130 1.2.2.2 yamt HW_PINCTRL_MUXSEL6_BANK3_PIN01 | /* Pin 76, EMI_D01 */ 131 1.2.2.2 yamt HW_PINCTRL_MUXSEL6_BANK3_PIN00) /* Pin 75, EMI_D00 */ 132 1.2.2.2 yamt ); 133 1.2.2.2 yamt 134 1.2.2.2 yamt REG_WRITE(HW_PINCTRL_BASE + HW_PINCTRL_MUXSEL7_CLR, ( 135 1.2.2.2 yamt HW_PINCTRL_MUXSEL7_BANK3_PIN21 | /* Pin 72, EMI_CLKN */ 136 1.2.2.2 yamt HW_PINCTRL_MUXSEL7_BANK3_PIN20 | /* Pin 70, EMI_CLK */ 137 1.2.2.2 yamt HW_PINCTRL_MUXSEL7_BANK3_PIN19 | /* Pin 74, EMI_DQS1 */ 138 1.2.2.2 yamt HW_PINCTRL_MUXSEL7_BANK3_PIN18 | /* Pin 73, EMI_DQS0 */ 139 1.2.2.2 yamt HW_PINCTRL_MUXSEL7_BANK3_PIN17 | /* Pin 92, EMI_DQM1 */ 140 1.2.2.2 yamt HW_PINCTRL_MUXSEL7_BANK3_PIN16) /* Pin 81, EMI_DQM0 */ 141 1.2.2.2 yamt ); 142 1.2.2.2 yamt 143 1.2.2.2 yamt return; 144 1.2.2.2 yamt } 145 1.2.2.2 yamt 146 1.2.2.2 yamt /* 147 1.2.2.2 yamt * Configure EMI pins voltages to 1.8/2.5V operation and drive strength 148 1.2.2.2 yamt * to "ma". 149 1.2.2.2 yamt */ 150 1.2.2.2 yamt void 151 1.2.2.2 yamt configure_emi_drive(int ma) 152 1.2.2.2 yamt { 153 1.2.2.2 yamt uint32_t drive; 154 1.2.2.2 yamt 155 1.2.2.2 yamt /* DRIVE 9 */ 156 1.2.2.2 yamt drive = REG_READ(HW_PINCTRL_BASE + HW_PINCTRL_DRIVE9); 157 1.2.2.2 yamt drive &= ~( 158 1.2.2.2 yamt HW_PINCTRL_DRIVE9_BANK2_PIN15_V | /* Pin 108, EMI_A06 */ 159 1.2.2.2 yamt HW_PINCTRL_DRIVE9_BANK2_PIN15_MA | 160 1.2.2.2 yamt HW_PINCTRL_DRIVE9_BANK2_PIN14_V | /* Pin 107, EMI_A05 */ 161 1.2.2.2 yamt HW_PINCTRL_DRIVE9_BANK2_PIN14_MA | 162 1.2.2.2 yamt HW_PINCTRL_DRIVE9_BANK2_PIN13_V | /* Pin 109, EMI_A04 */ 163 1.2.2.2 yamt HW_PINCTRL_DRIVE9_BANK2_PIN13_MA | 164 1.2.2.2 yamt HW_PINCTRL_DRIVE9_BANK2_PIN12_V | /* Pin 110, EMI_A03 */ 165 1.2.2.2 yamt HW_PINCTRL_DRIVE9_BANK2_PIN12_MA | 166 1.2.2.2 yamt HW_PINCTRL_DRIVE9_BANK2_PIN11_V | /* Pin 111, EMI_A02 */ 167 1.2.2.2 yamt HW_PINCTRL_DRIVE9_BANK2_PIN11_MA | 168 1.2.2.2 yamt HW_PINCTRL_DRIVE9_BANK2_PIN10_V | /* Pin 112, EMI_A01 */ 169 1.2.2.2 yamt HW_PINCTRL_DRIVE9_BANK2_PIN10_MA | 170 1.2.2.2 yamt HW_PINCTRL_DRIVE9_BANK2_PIN09_V | /* Pin 113, EMI_A00 */ 171 1.2.2.2 yamt HW_PINCTRL_DRIVE9_BANK2_PIN09_MA | 172 1.2.2.2 yamt HW_PINCTRL_DRIVE9_RSRVD6 | /* Always write zeroes */ 173 1.2.2.2 yamt HW_PINCTRL_DRIVE9_RSRVD5 | 174 1.2.2.2 yamt HW_PINCTRL_DRIVE9_RSRVD4 | 175 1.2.2.2 yamt HW_PINCTRL_DRIVE9_RSRVD3 | 176 1.2.2.2 yamt HW_PINCTRL_DRIVE9_RSRVD2 | 177 1.2.2.2 yamt HW_PINCTRL_DRIVE9_RSRVD1 | 178 1.2.2.2 yamt HW_PINCTRL_DRIVE9_RSRVD0 179 1.2.2.2 yamt ); 180 1.2.2.2 yamt drive |= ( 181 1.2.2.2 yamt __SHIFTIN(ma, HW_PINCTRL_DRIVE9_BANK2_PIN15_MA) | /* EMI_A06 */ 182 1.2.2.2 yamt __SHIFTIN(ma, HW_PINCTRL_DRIVE9_BANK2_PIN14_MA) | /* EMI_A05 */ 183 1.2.2.2 yamt __SHIFTIN(ma, HW_PINCTRL_DRIVE9_BANK2_PIN13_MA) | /* EMI_A04 */ 184 1.2.2.2 yamt __SHIFTIN(ma, HW_PINCTRL_DRIVE9_BANK2_PIN12_MA) | /* EMI_A03 */ 185 1.2.2.2 yamt __SHIFTIN(ma, HW_PINCTRL_DRIVE9_BANK2_PIN11_MA) | /* EMI_A02 */ 186 1.2.2.2 yamt __SHIFTIN(ma, HW_PINCTRL_DRIVE9_BANK2_PIN10_MA) | /* EMI_A01 */ 187 1.2.2.2 yamt __SHIFTIN(ma, HW_PINCTRL_DRIVE9_BANK2_PIN09_MA) /* EMI_A00 */ 188 1.2.2.2 yamt ); 189 1.2.2.2 yamt REG_WRITE(HW_PINCTRL_BASE + HW_PINCTRL_DRIVE9, drive); 190 1.2.2.2 yamt 191 1.2.2.2 yamt /* DRIVE 10 */ 192 1.2.2.2 yamt drive = REG_READ(HW_PINCTRL_BASE + HW_PINCTRL_DRIVE10); 193 1.2.2.2 yamt drive &= ~( 194 1.2.2.2 yamt HW_PINCTRL_DRIVE10_BANK2_PIN23_V | /* Pin 117, EMI_BA1 */ 195 1.2.2.2 yamt HW_PINCTRL_DRIVE10_BANK2_PIN23_MA | 196 1.2.2.2 yamt HW_PINCTRL_DRIVE10_BANK2_PIN22_V | /* Pin 116, EMI_BA0 */ 197 1.2.2.2 yamt HW_PINCTRL_DRIVE10_BANK2_PIN22_MA | 198 1.2.2.2 yamt HW_PINCTRL_DRIVE10_BANK2_PIN21_V | /* Pin 101, EMI_A12 */ 199 1.2.2.2 yamt HW_PINCTRL_DRIVE10_BANK2_PIN21_MA | 200 1.2.2.2 yamt HW_PINCTRL_DRIVE10_BANK2_PIN20_V | /* Pin 102, EMI_A11 */ 201 1.2.2.2 yamt HW_PINCTRL_DRIVE10_BANK2_PIN20_MA | 202 1.2.2.2 yamt HW_PINCTRL_DRIVE10_BANK2_PIN19_V | /* Pin 104, EMI_A10 */ 203 1.2.2.2 yamt HW_PINCTRL_DRIVE10_BANK2_PIN19_MA | 204 1.2.2.2 yamt HW_PINCTRL_DRIVE10_BANK2_PIN18_V | /* Pin 103, EMI_A09 */ 205 1.2.2.2 yamt HW_PINCTRL_DRIVE10_BANK2_PIN18_MA | 206 1.2.2.2 yamt HW_PINCTRL_DRIVE10_BANK2_PIN17_V | /* Pin 106, EMI_A08 */ 207 1.2.2.2 yamt HW_PINCTRL_DRIVE10_BANK2_PIN17_MA | 208 1.2.2.2 yamt HW_PINCTRL_DRIVE10_BANK2_PIN16_V | /* Pin 105, EMI_A07 */ 209 1.2.2.2 yamt HW_PINCTRL_DRIVE10_BANK2_PIN16_MA | 210 1.2.2.2 yamt HW_PINCTRL_DRIVE10_RSRVD6 | /* Always write zeroes */ 211 1.2.2.2 yamt HW_PINCTRL_DRIVE10_RSRVD5 | 212 1.2.2.2 yamt HW_PINCTRL_DRIVE10_RSRVD4 | 213 1.2.2.2 yamt HW_PINCTRL_DRIVE10_RSRVD3 | 214 1.2.2.2 yamt HW_PINCTRL_DRIVE10_RSRVD2 | 215 1.2.2.2 yamt HW_PINCTRL_DRIVE10_RSRVD1 | 216 1.2.2.2 yamt HW_PINCTRL_DRIVE10_RSRVD0 217 1.2.2.2 yamt ); 218 1.2.2.2 yamt drive |= ( 219 1.2.2.2 yamt __SHIFTIN(ma, HW_PINCTRL_DRIVE10_BANK2_PIN23_MA) | /* EMI_BA1 */ 220 1.2.2.2 yamt __SHIFTIN(ma, HW_PINCTRL_DRIVE10_BANK2_PIN22_MA) | /* EMI_BA0 */ 221 1.2.2.2 yamt __SHIFTIN(ma, HW_PINCTRL_DRIVE10_BANK2_PIN21_MA) | /* EMI_A12 */ 222 1.2.2.2 yamt __SHIFTIN(ma, HW_PINCTRL_DRIVE10_BANK2_PIN20_MA) | /* EMI_A11 */ 223 1.2.2.2 yamt __SHIFTIN(ma, HW_PINCTRL_DRIVE10_BANK2_PIN19_MA) | /* EMI_A10 */ 224 1.2.2.2 yamt __SHIFTIN(ma, HW_PINCTRL_DRIVE10_BANK2_PIN18_MA) | /* EMI_A09 */ 225 1.2.2.2 yamt __SHIFTIN(ma, HW_PINCTRL_DRIVE10_BANK2_PIN17_MA) | /* EMI_A08 */ 226 1.2.2.2 yamt __SHIFTIN(ma, HW_PINCTRL_DRIVE10_BANK2_PIN16_MA) /* EMI_A07 */ 227 1.2.2.2 yamt ); 228 1.2.2.2 yamt REG_WRITE(HW_PINCTRL_BASE + HW_PINCTRL_DRIVE10, drive); 229 1.2.2.2 yamt 230 1.2.2.2 yamt /* DRIVE 11 */ 231 1.2.2.2 yamt drive = REG_READ(HW_PINCTRL_BASE + HW_PINCTRL_DRIVE11); 232 1.2.2.2 yamt drive &= ~( 233 1.2.2.2 yamt HW_PINCTRL_DRIVE11_BANK2_PIN31_V | /* Pin 114, EMI_WEN */ 234 1.2.2.2 yamt HW_PINCTRL_DRIVE11_BANK2_PIN31_MA | 235 1.2.2.2 yamt HW_PINCTRL_DRIVE11_BANK2_PIN30_V | /* Pin 98, EMI_RASN */ 236 1.2.2.2 yamt HW_PINCTRL_DRIVE11_BANK2_PIN30_MA | 237 1.2.2.2 yamt HW_PINCTRL_DRIVE11_BANK2_PIN29_V | /* Pin 115, EMI_CKE */ 238 1.2.2.2 yamt HW_PINCTRL_DRIVE11_BANK2_PIN29_MA | 239 1.2.2.2 yamt #if 0 240 1.2.2.2 yamt /* 169-Pin BGA Package */ 241 1.2.2.2 yamt HW_PINCTRL_DRIVE11_BANK2_PIN26_V | /* Pin 99, EMI_CE1N */ 242 1.2.2.2 yamt HW_PINCTRL_DRIVE11_BANK2_PIN26_MA | 243 1.2.2.2 yamt #endif 244 1.2.2.2 yamt HW_PINCTRL_DRIVE11_BANK2_PIN25_V | /* Pin 100, EMI_CE0N */ 245 1.2.2.2 yamt HW_PINCTRL_DRIVE11_BANK2_PIN25_MA | 246 1.2.2.2 yamt HW_PINCTRL_DRIVE11_BANK2_PIN24_V | /* Pin 97, EMI_CASN */ 247 1.2.2.2 yamt HW_PINCTRL_DRIVE11_BANK2_PIN24_MA | 248 1.2.2.2 yamt HW_PINCTRL_DRIVE11_RSRVD6 | /* Always write zeroes */ 249 1.2.2.2 yamt HW_PINCTRL_DRIVE11_RSRVD5 | 250 1.2.2.2 yamt HW_PINCTRL_DRIVE11_RSRVD4 | 251 1.2.2.2 yamt HW_PINCTRL_DRIVE11_RSRVD3 | 252 1.2.2.2 yamt HW_PINCTRL_DRIVE11_RSRVD2 | 253 1.2.2.2 yamt HW_PINCTRL_DRIVE11_RSRVD1 | 254 1.2.2.2 yamt HW_PINCTRL_DRIVE11_RSRVD0 255 1.2.2.2 yamt ); 256 1.2.2.2 yamt drive |= ( 257 1.2.2.2 yamt __SHIFTIN(ma, HW_PINCTRL_DRIVE11_BANK2_PIN31_MA) | /* EMI_WEN */ 258 1.2.2.2 yamt __SHIFTIN(ma, HW_PINCTRL_DRIVE11_BANK2_PIN30_MA) | /* EMI_RASN */ 259 1.2.2.2 yamt __SHIFTIN(ma, HW_PINCTRL_DRIVE11_BANK2_PIN29_MA) | /* EMI_CKE */ 260 1.2.2.2 yamt #if 0 /* 169-Pin BGA Package */ 261 1.2.2.2 yamt __SHIFTIN(ma, HW_PINCTRL_DRIVE11_BANK2_PIN26_MA) | /* EMI_CE1N */ 262 1.2.2.2 yamt #endif 263 1.2.2.2 yamt __SHIFTIN(ma, HW_PINCTRL_DRIVE11_BANK2_PIN25_MA) | /* EMI_CE0N */ 264 1.2.2.2 yamt __SHIFTIN(ma, HW_PINCTRL_DRIVE11_BANK2_PIN24_MA) /* EMI_CASN */ 265 1.2.2.2 yamt ); 266 1.2.2.2 yamt REG_WRITE(HW_PINCTRL_BASE + HW_PINCTRL_DRIVE11, drive); 267 1.2.2.2 yamt 268 1.2.2.2 yamt /* DRIVE 12 */ 269 1.2.2.2 yamt drive = REG_READ(HW_PINCTRL_BASE + HW_PINCTRL_DRIVE12); 270 1.2.2.2 yamt drive &= ~( 271 1.2.2.2 yamt HW_PINCTRL_DRIVE12_BANK3_PIN07_V | /* Pin 85, EMI_D07 */ 272 1.2.2.2 yamt HW_PINCTRL_DRIVE12_BANK3_PIN07_MA | 273 1.2.2.2 yamt HW_PINCTRL_DRIVE12_BANK3_PIN06_V | /* Pin 84, EMI_D06 */ 274 1.2.2.2 yamt HW_PINCTRL_DRIVE12_BANK3_PIN06_MA | 275 1.2.2.2 yamt HW_PINCTRL_DRIVE12_BANK3_PIN05_V | /* Pin 83, EMI_D05 */ 276 1.2.2.2 yamt HW_PINCTRL_DRIVE12_BANK3_PIN05_MA | 277 1.2.2.2 yamt HW_PINCTRL_DRIVE12_BANK3_PIN04_V | /* Pin 82, EMI_D04 */ 278 1.2.2.2 yamt HW_PINCTRL_DRIVE12_BANK3_PIN04_MA | 279 1.2.2.2 yamt HW_PINCTRL_DRIVE12_BANK3_PIN03_V | /* Pin 79, EMI_D03 */ 280 1.2.2.2 yamt HW_PINCTRL_DRIVE12_BANK3_PIN03_MA | 281 1.2.2.2 yamt HW_PINCTRL_DRIVE12_BANK3_PIN02_V | /* Pin 77, EMI_D02 */ 282 1.2.2.2 yamt HW_PINCTRL_DRIVE12_BANK3_PIN02_MA | 283 1.2.2.2 yamt HW_PINCTRL_DRIVE12_BANK3_PIN01_V | /* Pin 76, EMI_D01 */ 284 1.2.2.2 yamt HW_PINCTRL_DRIVE12_BANK3_PIN01_MA | 285 1.2.2.2 yamt HW_PINCTRL_DRIVE12_BANK3_PIN00_V | /* Pin 75, EMI_D00 */ 286 1.2.2.2 yamt HW_PINCTRL_DRIVE12_BANK3_PIN00_MA | 287 1.2.2.2 yamt HW_PINCTRL_DRIVE12_RSRVD6 | /* Always write zeroes */ 288 1.2.2.2 yamt HW_PINCTRL_DRIVE12_RSRVD5 | 289 1.2.2.2 yamt HW_PINCTRL_DRIVE12_RSRVD4 | 290 1.2.2.2 yamt HW_PINCTRL_DRIVE12_RSRVD3 | 291 1.2.2.2 yamt HW_PINCTRL_DRIVE12_RSRVD2 | 292 1.2.2.2 yamt HW_PINCTRL_DRIVE12_RSRVD1 | 293 1.2.2.2 yamt HW_PINCTRL_DRIVE12_RSRVD0 294 1.2.2.2 yamt ); 295 1.2.2.2 yamt drive |= ( 296 1.2.2.2 yamt __SHIFTIN(ma, HW_PINCTRL_DRIVE12_BANK3_PIN07_MA) | /* EMI_D07 */ 297 1.2.2.2 yamt __SHIFTIN(ma, HW_PINCTRL_DRIVE12_BANK3_PIN06_MA) | /* EMI_D06 */ 298 1.2.2.2 yamt __SHIFTIN(ma, HW_PINCTRL_DRIVE12_BANK3_PIN05_MA) | /* EMI_D05 */ 299 1.2.2.2 yamt __SHIFTIN(ma, HW_PINCTRL_DRIVE12_BANK3_PIN04_MA) | /* EMI_D04 */ 300 1.2.2.2 yamt __SHIFTIN(ma, HW_PINCTRL_DRIVE12_BANK3_PIN03_MA) | /* EMI_D03 */ 301 1.2.2.2 yamt __SHIFTIN(ma, HW_PINCTRL_DRIVE12_BANK3_PIN02_MA) | /* EMI_D02 */ 302 1.2.2.2 yamt __SHIFTIN(ma, HW_PINCTRL_DRIVE12_BANK3_PIN01_MA) | /* EMI_D01 */ 303 1.2.2.2 yamt __SHIFTIN(ma, HW_PINCTRL_DRIVE12_BANK3_PIN00_MA) /* EMI_D00 */ 304 1.2.2.2 yamt ); 305 1.2.2.2 yamt REG_WRITE(HW_PINCTRL_BASE + HW_PINCTRL_DRIVE12, drive); 306 1.2.2.2 yamt 307 1.2.2.2 yamt /* DRIVE 13 */ 308 1.2.2.2 yamt drive = REG_READ(HW_PINCTRL_BASE + HW_PINCTRL_DRIVE13); 309 1.2.2.2 yamt drive &= ~( 310 1.2.2.2 yamt HW_PINCTRL_DRIVE13_BANK3_PIN15_V | /* Pin 95, EMI_D15 */ 311 1.2.2.2 yamt HW_PINCTRL_DRIVE13_BANK3_PIN15_MA | 312 1.2.2.2 yamt HW_PINCTRL_DRIVE13_BANK3_PIN14_V | /* Pin 96, EMI_D14 */ 313 1.2.2.2 yamt HW_PINCTRL_DRIVE13_BANK3_PIN14_MA | 314 1.2.2.2 yamt HW_PINCTRL_DRIVE13_BANK3_PIN13_V | /* Pin 94, EMI_D13 */ 315 1.2.2.2 yamt HW_PINCTRL_DRIVE13_BANK3_PIN13_MA | 316 1.2.2.2 yamt HW_PINCTRL_DRIVE13_BANK3_PIN12_V | /* Pin 93, EMI_D12 */ 317 1.2.2.2 yamt HW_PINCTRL_DRIVE13_BANK3_PIN12_MA | 318 1.2.2.2 yamt HW_PINCTRL_DRIVE13_BANK3_PIN11_V | /* Pin 91, EMI_D11 */ 319 1.2.2.2 yamt HW_PINCTRL_DRIVE13_BANK3_PIN11_MA | 320 1.2.2.2 yamt HW_PINCTRL_DRIVE13_BANK3_PIN10_V | /* Pin 89, EMI_D10 */ 321 1.2.2.2 yamt HW_PINCTRL_DRIVE13_BANK3_PIN10_MA | 322 1.2.2.2 yamt HW_PINCTRL_DRIVE13_BANK3_PIN09_V | /* Pin 87, EMI_D09 */ 323 1.2.2.2 yamt HW_PINCTRL_DRIVE13_BANK3_PIN09_MA | 324 1.2.2.2 yamt HW_PINCTRL_DRIVE13_BANK3_PIN08_V | /* Pin 86, EMI_D08 */ 325 1.2.2.2 yamt HW_PINCTRL_DRIVE13_BANK3_PIN08_MA | 326 1.2.2.2 yamt HW_PINCTRL_DRIVE13_RSRVD6 | /* Always write zeroes */ 327 1.2.2.2 yamt HW_PINCTRL_DRIVE13_RSRVD5 | 328 1.2.2.2 yamt HW_PINCTRL_DRIVE13_RSRVD4 | 329 1.2.2.2 yamt HW_PINCTRL_DRIVE13_RSRVD3 | 330 1.2.2.2 yamt HW_PINCTRL_DRIVE13_RSRVD2 | 331 1.2.2.2 yamt HW_PINCTRL_DRIVE13_RSRVD1 | 332 1.2.2.2 yamt HW_PINCTRL_DRIVE13_RSRVD0 333 1.2.2.2 yamt ); 334 1.2.2.2 yamt drive |= ( 335 1.2.2.2 yamt __SHIFTIN(ma, HW_PINCTRL_DRIVE13_BANK3_PIN15_MA) | /* EMI_D15 */ 336 1.2.2.2 yamt __SHIFTIN(ma, HW_PINCTRL_DRIVE13_BANK3_PIN14_MA) | /* EMI_D14 */ 337 1.2.2.2 yamt __SHIFTIN(ma, HW_PINCTRL_DRIVE13_BANK3_PIN13_MA) | /* EMI_D13 */ 338 1.2.2.2 yamt __SHIFTIN(ma, HW_PINCTRL_DRIVE13_BANK3_PIN12_MA) | /* EMI_D12 */ 339 1.2.2.2 yamt __SHIFTIN(ma, HW_PINCTRL_DRIVE13_BANK3_PIN11_MA) | /* EMI_D11 */ 340 1.2.2.2 yamt __SHIFTIN(ma, HW_PINCTRL_DRIVE13_BANK3_PIN10_MA) | /* EMI_D10 */ 341 1.2.2.2 yamt __SHIFTIN(ma, HW_PINCTRL_DRIVE13_BANK3_PIN09_MA) | /* EMI_D09 */ 342 1.2.2.2 yamt __SHIFTIN(ma, HW_PINCTRL_DRIVE13_BANK3_PIN08_MA) /* EMI_D08 */ 343 1.2.2.2 yamt ); 344 1.2.2.2 yamt REG_WRITE(HW_PINCTRL_BASE + HW_PINCTRL_DRIVE13, drive); 345 1.2.2.2 yamt 346 1.2.2.2 yamt /* DRIVE 14 */ 347 1.2.2.2 yamt drive = REG_READ(HW_PINCTRL_BASE + HW_PINCTRL_DRIVE14); 348 1.2.2.2 yamt drive &= ~( 349 1.2.2.2 yamt HW_PINCTRL_DRIVE14_BANK3_PIN21_V | /* Pin 72, EMI_CLKN */ 350 1.2.2.2 yamt HW_PINCTRL_DRIVE14_BANK3_PIN21_MA | 351 1.2.2.2 yamt HW_PINCTRL_DRIVE14_BANK3_PIN20_V | /* Pin 70, EMI_CLK */ 352 1.2.2.2 yamt HW_PINCTRL_DRIVE14_BANK3_PIN20_MA | 353 1.2.2.2 yamt HW_PINCTRL_DRIVE14_BANK3_PIN19_V | /* Pin 74, EMI_DQS1 */ 354 1.2.2.2 yamt HW_PINCTRL_DRIVE14_BANK3_PIN19_MA | 355 1.2.2.2 yamt HW_PINCTRL_DRIVE14_BANK3_PIN18_V | /* Pin 73, EMI_DQS0 */ 356 1.2.2.2 yamt HW_PINCTRL_DRIVE14_BANK3_PIN18_MA | 357 1.2.2.2 yamt HW_PINCTRL_DRIVE14_BANK3_PIN17_V | /* Pin 92, EMI_DQM1 */ 358 1.2.2.2 yamt HW_PINCTRL_DRIVE14_BANK3_PIN17_MA | 359 1.2.2.2 yamt HW_PINCTRL_DRIVE14_BANK3_PIN16_V | /* Pin 81, EMI_DQM0 */ 360 1.2.2.2 yamt HW_PINCTRL_DRIVE14_BANK3_PIN16_MA | 361 1.2.2.2 yamt HW_PINCTRL_DRIVE14_RSRVD6 | /* Always write zeroes */ 362 1.2.2.2 yamt HW_PINCTRL_DRIVE14_RSRVD5 | 363 1.2.2.2 yamt HW_PINCTRL_DRIVE14_RSRVD4 | 364 1.2.2.2 yamt HW_PINCTRL_DRIVE14_RSRVD3 | 365 1.2.2.2 yamt HW_PINCTRL_DRIVE14_RSRVD2 | 366 1.2.2.2 yamt HW_PINCTRL_DRIVE14_RSRVD1 | 367 1.2.2.2 yamt HW_PINCTRL_DRIVE14_RSRVD0 368 1.2.2.2 yamt ); 369 1.2.2.2 yamt drive |= ( 370 1.2.2.2 yamt __SHIFTIN(ma, HW_PINCTRL_DRIVE14_BANK3_PIN21_MA) | /* EMI_CLKN */ 371 1.2.2.2 yamt __SHIFTIN(ma, HW_PINCTRL_DRIVE14_BANK3_PIN20_MA) | /* EMI_CLK */ 372 1.2.2.2 yamt __SHIFTIN(ma, HW_PINCTRL_DRIVE14_BANK3_PIN19_MA) | /* EMI_DQS1 */ 373 1.2.2.2 yamt __SHIFTIN(ma, HW_PINCTRL_DRIVE14_BANK3_PIN18_MA) | /* EMI_DQS0 */ 374 1.2.2.2 yamt __SHIFTIN(ma, HW_PINCTRL_DRIVE14_BANK3_PIN17_MA) | /* EMI_DQM1 */ 375 1.2.2.2 yamt __SHIFTIN(ma, HW_PINCTRL_DRIVE14_BANK3_PIN16_MA) /* EMI_DQM0 */ 376 1.2.2.2 yamt ); 377 1.2.2.2 yamt REG_WRITE(HW_PINCTRL_BASE + HW_PINCTRL_DRIVE14, drive); 378 1.2.2.2 yamt 379 1.2.2.2 yamt return; 380 1.2.2.2 yamt } 381 1.2.2.2 yamt 382 1.2.2.2 yamt /* 383 1.2.2.2 yamt * Disable internal gate keepers on EMI pins. 384 1.2.2.2 yamt */ 385 1.2.2.2 yamt void 386 1.2.2.2 yamt disable_emi_padkeepers(void) 387 1.2.2.2 yamt { 388 1.2.2.2 yamt 389 1.2.2.2 yamt REG_WRITE(HW_PINCTRL_BASE + HW_PINCTRL_PULL3_SET, ( 390 1.2.2.2 yamt HW_PINCTRL_PULL3_BANK3_PIN17 | /* EMI_DQM1 */ 391 1.2.2.2 yamt HW_PINCTRL_PULL3_BANK3_PIN16 | /* EMI_DQM0 */ 392 1.2.2.2 yamt HW_PINCTRL_PULL3_BANK3_PIN15 | /* EMI_D15 */ 393 1.2.2.2 yamt HW_PINCTRL_PULL3_BANK3_PIN14 | /* EMI_D14 */ 394 1.2.2.2 yamt HW_PINCTRL_PULL3_BANK3_PIN13 | /* EMI_D13 */ 395 1.2.2.2 yamt HW_PINCTRL_PULL3_BANK3_PIN12 | /* EMI_D12 */ 396 1.2.2.2 yamt HW_PINCTRL_PULL3_BANK3_PIN11 | /* EMI_D11 */ 397 1.2.2.2 yamt HW_PINCTRL_PULL3_BANK3_PIN10 | /* EMI_D10 */ 398 1.2.2.2 yamt HW_PINCTRL_PULL3_BANK3_PIN09 | /* EMI_D09 */ 399 1.2.2.2 yamt HW_PINCTRL_PULL3_BANK3_PIN08 | /* EMI_D08 */ 400 1.2.2.2 yamt HW_PINCTRL_PULL3_BANK3_PIN07 | /* EMI_D07 */ 401 1.2.2.2 yamt HW_PINCTRL_PULL3_BANK3_PIN06 | /* EMI_D06 */ 402 1.2.2.2 yamt HW_PINCTRL_PULL3_BANK3_PIN05 | /* EMI_D05 */ 403 1.2.2.2 yamt HW_PINCTRL_PULL3_BANK3_PIN04 | /* EMI_D04 */ 404 1.2.2.2 yamt HW_PINCTRL_PULL3_BANK3_PIN03 | /* EMI_D03 */ 405 1.2.2.2 yamt HW_PINCTRL_PULL3_BANK3_PIN02 | /* EMI_D02 */ 406 1.2.2.2 yamt HW_PINCTRL_PULL3_BANK3_PIN01 | /* EMI_D01 */ 407 1.2.2.2 yamt HW_PINCTRL_PULL3_BANK3_PIN00) /* EMI_D00 */ 408 1.2.2.2 yamt ); 409 1.2.2.2 yamt 410 1.2.2.2 yamt return; 411 1.2.2.2 yamt } 412 1.2.2.2 yamt 413 1.2.2.2 yamt /* 414 1.2.2.2 yamt * Configure external SSP pins to be used for SD/MMC. 415 1.2.2.2 yamt */ 416 1.2.2.2 yamt void 417 1.2.2.2 yamt configure_ssp_mux(void) 418 1.2.2.2 yamt { 419 1.2.2.2 yamt REG_WRITE(HW_PINCTRL_BASE + HW_PINCTRL_MUXSEL4_CLR, ( 420 1.2.2.2 yamt HW_PINCTRL_MUXSEL4_BANK2_PIN00 | /* Pin 121, SSP1_CMD */ 421 1.2.2.2 yamt HW_PINCTRL_MUXSEL4_BANK2_PIN02 | /* Pin 122, SSP1_DATA0 */ 422 1.2.2.2 yamt HW_PINCTRL_MUXSEL4_BANK2_PIN03 | /* Pin 123, SSP1_DATA1 */ 423 1.2.2.2 yamt HW_PINCTRL_MUXSEL4_BANK2_PIN04 | /* Pin 124, SSP1_DATA2 */ 424 1.2.2.2 yamt HW_PINCTRL_MUXSEL4_BANK2_PIN05 | /* Pin 125, SSP1_DATA3 */ 425 1.2.2.2 yamt HW_PINCTRL_MUXSEL4_BANK2_PIN06) /* Pin 127, SSP1_SCK */ 426 1.2.2.2 yamt ); 427 1.2.2.2 yamt 428 1.2.2.2 yamt return; 429 1.2.2.2 yamt } 430 1.2.2.2 yamt 431 1.2.2.2 yamt /* 432 1.2.2.2 yamt * Configure SSP pins drive strength to "ma". 433 1.2.2.2 yamt * Out of reset, all non-EMI pins are configured as 3.3 V. 434 1.2.2.2 yamt */ 435 1.2.2.2 yamt void 436 1.2.2.2 yamt configure_ssp_drive(int ma) 437 1.2.2.2 yamt { 438 1.2.2.2 yamt uint32_t reg = REG_READ(HW_PINCTRL_BASE + HW_PINCTRL_DRIVE8); 439 1.2.2.2 yamt reg &= ~( 440 1.2.2.2 yamt HW_PINCTRL_DRIVE8_BANK2_PIN06_MA | /* Pin 127, SSP1_SCK */ 441 1.2.2.2 yamt HW_PINCTRL_DRIVE8_BANK2_PIN05_MA | /* Pin 125, SSP1_DATA3 */ 442 1.2.2.2 yamt HW_PINCTRL_DRIVE8_BANK2_PIN04_MA | /* Pin 124, SSP1_DATA2 */ 443 1.2.2.2 yamt HW_PINCTRL_DRIVE8_BANK2_PIN03_MA | /* Pin 123, SSP1_DATA1 */ 444 1.2.2.2 yamt HW_PINCTRL_DRIVE8_BANK2_PIN02_MA | /* Pin 122, SSP1_DATA0 */ 445 1.2.2.2 yamt HW_PINCTRL_DRIVE8_BANK2_PIN00_MA /* Pin 121, SSP1_CMD */ 446 1.2.2.2 yamt ); 447 1.2.2.2 yamt 448 1.2.2.2 yamt reg |= __SHIFTIN(ma, HW_PINCTRL_DRIVE8_BANK2_PIN06_MA) | 449 1.2.2.2 yamt __SHIFTIN(ma, HW_PINCTRL_DRIVE8_BANK2_PIN05_MA) | 450 1.2.2.2 yamt __SHIFTIN(ma, HW_PINCTRL_DRIVE8_BANK2_PIN04_MA) | 451 1.2.2.2 yamt __SHIFTIN(ma, HW_PINCTRL_DRIVE8_BANK2_PIN03_MA) | 452 1.2.2.2 yamt __SHIFTIN(ma, HW_PINCTRL_DRIVE8_BANK2_PIN02_MA) | 453 1.2.2.2 yamt __SHIFTIN(ma, HW_PINCTRL_DRIVE8_BANK2_PIN00_MA 454 1.2.2.2 yamt ); 455 1.2.2.2 yamt 456 1.2.2.2 yamt REG_WRITE(HW_PINCTRL_BASE + HW_PINCTRL_DRIVE8, reg); 457 1.2.2.2 yamt 458 1.2.2.2 yamt return; 459 1.2.2.2 yamt } 460 1.2.2.2 yamt 461 1.2.2.2 yamt /* 462 1.2.2.2 yamt * Configure SSP pull ups. 463 1.2.2.2 yamt */ 464 1.2.2.2 yamt void 465 1.2.2.2 yamt configure_ssp_pullups(void) 466 1.2.2.2 yamt { 467 1.2.2.2 yamt /* Disable pull ups for SSP and let HW take care of them. */ 468 1.2.2.2 yamt // REG_WRITE(HW_PINCTRL_BASE + HW_PINCTRL_PULL2_CLR, ( 469 1.2.2.2 yamt // HW_PINCTRL_PULL2_BANK2_PIN05 |/* Pin 125, SSP1_DATA3 */ 470 1.2.2.2 yamt // HW_PINCTRL_PULL2_BANK2_PIN04 | /* Pin 124, SSP1_DATA2 */ 471 1.2.2.2 yamt // HW_PINCTRL_PULL2_BANK2_PIN03 | /* Pin 123, SSP1_DATA1 */ 472 1.2.2.2 yamt // HW_PINCTRL_PULL2_BANK2_PIN02 | /* Pin 122, SSP1_DATA0 */ 473 1.2.2.2 yamt // HW_PINCTRL_PULL2_BANK2_PIN00 /* Pin 121, SSP1_CMD */ 474 1.2.2.2 yamt // )); 475 1.2.2.2 yamt 476 1.2.2.2 yamt REG_WRITE(HW_PINCTRL_BASE + HW_PINCTRL_PULL2_SET, ( 477 1.2.2.2 yamt HW_PINCTRL_PULL2_BANK2_PIN05 |/* Pin 125, SSP1_DATA3 */ 478 1.2.2.2 yamt HW_PINCTRL_PULL2_BANK2_PIN04 | /* Pin 124, SSP1_DATA2 */ 479 1.2.2.2 yamt HW_PINCTRL_PULL2_BANK2_PIN03 | /* Pin 123, SSP1_DATA1 */ 480 1.2.2.2 yamt HW_PINCTRL_PULL2_BANK2_PIN02 | /* Pin 122, SSP1_DATA0 */ 481 1.2.2.2 yamt HW_PINCTRL_PULL2_BANK2_PIN00 /* Pin 121, SSP1_CMD */ 482 1.2.2.2 yamt )); 483 1.2.2.2 yamt 484 1.2.2.2 yamt return; 485 1.2.2.2 yamt } 486
Indexes created Fri Oct 17 09:09:57 GMT 2025