pinctrl_prep.c revision 1.3.4.2
1 1.3.4.2 tls /* $Id: pinctrl_prep.c,v 1.3.4.2 2013/02/25 00:28:38 tls Exp $ */ 2 1.3.4.2 tls 3 1.3.4.2 tls /* 4 1.3.4.2 tls * Copyright (c) 2012 The NetBSD Foundation, Inc. 5 1.3.4.2 tls * All rights reserved. 6 1.3.4.2 tls * 7 1.3.4.2 tls * This code is derived from software contributed to The NetBSD Foundation 8 1.3.4.2 tls * by Petri Laakso. 9 1.3.4.2 tls * 10 1.3.4.2 tls * Redistribution and use in source and binary forms, with or without 11 1.3.4.2 tls * modification, are permitted provided that the following conditions 12 1.3.4.2 tls * are met: 13 1.3.4.2 tls * 1. Redistributions of source code must retain the above copyright 14 1.3.4.2 tls * notice, this list of conditions and the following disclaimer. 15 1.3.4.2 tls * 2. Redistributions in binary form must reproduce the above copyright 16 1.3.4.2 tls * notice, this list of conditions and the following disclaimer in the 17 1.3.4.2 tls * documentation and/or other materials provided with the distribution. 18 1.3.4.2 tls * 19 1.3.4.2 tls * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 1.3.4.2 tls * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 1.3.4.2 tls * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 1.3.4.2 tls * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 1.3.4.2 tls * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 1.3.4.2 tls * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 1.3.4.2 tls * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 1.3.4.2 tls * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 1.3.4.2 tls * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 1.3.4.2 tls * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 1.3.4.2 tls * POSSIBILITY OF SUCH DAMAGE. 30 1.3.4.2 tls */ 31 1.3.4.2 tls 32 1.3.4.2 tls #include <sys/param.h> 33 1.3.4.2 tls #include <sys/cdefs.h> 34 1.3.4.2 tls #include <sys/types.h> 35 1.3.4.2 tls 36 1.3.4.2 tls #include <arm/imx/imx23_pinctrlreg.h> 37 1.3.4.2 tls 38 1.3.4.2 tls #include <lib/libsa/stand.h> 39 1.3.4.2 tls 40 1.3.4.2 tls #include "common.h" 41 1.3.4.2 tls 42 1.3.4.2 tls static void configure_emi_mux(void); 43 1.3.4.2 tls static void configure_emi_drive(int); 44 1.3.4.2 tls static void disable_emi_padkeepers(void); 45 1.3.4.2 tls static void configure_ssp_mux(void); 46 1.3.4.2 tls static void configure_ssp_drive(int); 47 1.3.4.2 tls static void configure_ssp_pullups(void); 48 1.3.4.2 tls static void configure_dbuart_mux(void); 49 1.3.4.2 tls 50 1.3.4.2 tls /* EMI pins output drive strengths */ 51 1.3.4.2 tls #define DRIVE_04_MA 0x0 /* 4 mA */ 52 1.3.4.2 tls #define DRIVE_08_MA 0x1 /* 8 mA */ 53 1.3.4.2 tls #define DRIVE_12_MA 0x2 /* 12 mA */ 54 1.3.4.2 tls #define DRIVE_16_MA 0x3 /* 16 mA */ 55 1.3.4.2 tls 56 1.3.4.2 tls /* 57 1.3.4.2 tls * Configure external EMI pins. 58 1.3.4.2 tls */ 59 1.3.4.2 tls int 60 1.3.4.2 tls pinctrl_prep(void) 61 1.3.4.2 tls { 62 1.3.4.2 tls 63 1.3.4.2 tls REG_WR(HW_PINCTRL_BASE + HW_PINCTRL_CTRL_CLR, 64 1.3.4.2 tls (HW_PINCTRL_CTRL_SFTRST | HW_PINCTRL_CTRL_CLKGATE)); 65 1.3.4.2 tls 66 1.3.4.2 tls /* EMI. */ 67 1.3.4.2 tls configure_emi_mux(); 68 1.3.4.2 tls configure_emi_drive(DRIVE_12_MA); 69 1.3.4.2 tls disable_emi_padkeepers(); 70 1.3.4.2 tls 71 1.3.4.2 tls /* SSP. */ 72 1.3.4.2 tls configure_ssp_mux(); 73 1.3.4.2 tls configure_ssp_drive(DRIVE_16_MA); 74 1.3.4.2 tls configure_ssp_pullups(); 75 1.3.4.2 tls 76 1.3.4.2 tls /* Debug UART. */ 77 1.3.4.2 tls configure_dbuart_mux(); 78 1.3.4.2 tls 79 1.3.4.2 tls return 0; 80 1.3.4.2 tls } 81 1.3.4.2 tls 82 1.3.4.2 tls /* 83 1.3.4.2 tls * Configure external EMI pins to be used for DRAM. 84 1.3.4.2 tls */ 85 1.3.4.2 tls static void 86 1.3.4.2 tls configure_emi_mux(void) 87 1.3.4.2 tls { 88 1.3.4.2 tls 89 1.3.4.2 tls REG_WR(HW_PINCTRL_BASE + HW_PINCTRL_MUXSEL4_CLR, ( 90 1.3.4.2 tls HW_PINCTRL_MUXSEL4_BANK2_PIN15 | /* Pin 108, EMI_A06 */ 91 1.3.4.2 tls HW_PINCTRL_MUXSEL4_BANK2_PIN14 | /* Pin 107, EMI_A05 */ 92 1.3.4.2 tls HW_PINCTRL_MUXSEL4_BANK2_PIN13 | /* Pin 109, EMI_A04 */ 93 1.3.4.2 tls HW_PINCTRL_MUXSEL4_BANK2_PIN12 | /* Pin 110, EMI_A03 */ 94 1.3.4.2 tls HW_PINCTRL_MUXSEL4_BANK2_PIN11 | /* Pin 111, EMI_A02 */ 95 1.3.4.2 tls HW_PINCTRL_MUXSEL4_BANK2_PIN10 | /* Pin 112, EMI_A01 */ 96 1.3.4.2 tls HW_PINCTRL_MUXSEL4_BANK2_PIN09) /* Pin 113, EMI_A00 */ 97 1.3.4.2 tls ); 98 1.3.4.2 tls 99 1.3.4.2 tls REG_WR(HW_PINCTRL_BASE + HW_PINCTRL_MUXSEL5_CLR, ( 100 1.3.4.2 tls HW_PINCTRL_MUXSEL5_BANK2_PIN31 | /* Pin 114, EMI_WEN */ 101 1.3.4.2 tls HW_PINCTRL_MUXSEL5_BANK2_PIN30 | /* Pin 98, EMI_RASN */ 102 1.3.4.2 tls HW_PINCTRL_MUXSEL5_BANK2_PIN29 | /* Pin 115, EMI_CKE */ 103 1.3.4.2 tls #if 0 104 1.3.4.2 tls /* 169-Pin BGA Package */ 105 1.3.4.2 tls HW_PINCTRL_MUXSEL5_BANK2_PIN26 | /* Pin 99, EMI_CE1N */ 106 1.3.4.2 tls #endif 107 1.3.4.2 tls HW_PINCTRL_MUXSEL5_BANK2_PIN25 | /* Pin 100, EMI_CE0N */ 108 1.3.4.2 tls HW_PINCTRL_MUXSEL5_BANK2_PIN24 | /* Pin 97, EMI_CASN */ 109 1.3.4.2 tls HW_PINCTRL_MUXSEL5_BANK2_PIN23 | /* Pin 117, EMI_BA1 */ 110 1.3.4.2 tls HW_PINCTRL_MUXSEL5_BANK2_PIN22 | /* Pin 116, EMI_BA0 */ 111 1.3.4.2 tls HW_PINCTRL_MUXSEL5_BANK2_PIN21 | /* Pin 101, EMI_A12 */ 112 1.3.4.2 tls HW_PINCTRL_MUXSEL5_BANK2_PIN20 | /* Pin 102, EMI_A11 */ 113 1.3.4.2 tls HW_PINCTRL_MUXSEL5_BANK2_PIN19 | /* Pin 104, EMI_A10 */ 114 1.3.4.2 tls HW_PINCTRL_MUXSEL5_BANK2_PIN18 | /* Pin 103, EMI_A09 */ 115 1.3.4.2 tls HW_PINCTRL_MUXSEL5_BANK2_PIN17 | /* Pin 106, EMI_A08 */ 116 1.3.4.2 tls HW_PINCTRL_MUXSEL5_BANK2_PIN16) /* Pin 105, EMI_A07 */ 117 1.3.4.2 tls ); 118 1.3.4.2 tls 119 1.3.4.2 tls REG_WR(HW_PINCTRL_BASE + HW_PINCTRL_MUXSEL6_CLR, ( 120 1.3.4.2 tls HW_PINCTRL_MUXSEL6_BANK3_PIN15 | /* Pin 95, EMI_D15 */ 121 1.3.4.2 tls HW_PINCTRL_MUXSEL6_BANK3_PIN14 | /* Pin 96, EMI_D14 */ 122 1.3.4.2 tls HW_PINCTRL_MUXSEL6_BANK3_PIN13 | /* Pin 94, EMI_D13 */ 123 1.3.4.2 tls HW_PINCTRL_MUXSEL6_BANK3_PIN12 | /* Pin 93, EMI_D12 */ 124 1.3.4.2 tls HW_PINCTRL_MUXSEL6_BANK3_PIN11 | /* Pin 91, EMI_D11 */ 125 1.3.4.2 tls HW_PINCTRL_MUXSEL6_BANK3_PIN10 | /* Pin 89, EMI_D10 */ 126 1.3.4.2 tls HW_PINCTRL_MUXSEL6_BANK3_PIN09 | /* Pin 87, EMI_D09 */ 127 1.3.4.2 tls HW_PINCTRL_MUXSEL6_BANK3_PIN08 | /* Pin 86, EMI_D08 */ 128 1.3.4.2 tls HW_PINCTRL_MUXSEL6_BANK3_PIN07 | /* Pin 85, EMI_D07 */ 129 1.3.4.2 tls HW_PINCTRL_MUXSEL6_BANK3_PIN06 | /* Pin 84, EMI_D06 */ 130 1.3.4.2 tls HW_PINCTRL_MUXSEL6_BANK3_PIN05 | /* Pin 83, EMI_D05 */ 131 1.3.4.2 tls HW_PINCTRL_MUXSEL6_BANK3_PIN04 | /* Pin 82, EMI_D04 */ 132 1.3.4.2 tls HW_PINCTRL_MUXSEL6_BANK3_PIN03 | /* Pin 79, EMI_D03 */ 133 1.3.4.2 tls HW_PINCTRL_MUXSEL6_BANK3_PIN02 | /* Pin 77, EMI_D02 */ 134 1.3.4.2 tls HW_PINCTRL_MUXSEL6_BANK3_PIN01 | /* Pin 76, EMI_D01 */ 135 1.3.4.2 tls HW_PINCTRL_MUXSEL6_BANK3_PIN00) /* Pin 75, EMI_D00 */ 136 1.3.4.2 tls ); 137 1.3.4.2 tls 138 1.3.4.2 tls REG_WR(HW_PINCTRL_BASE + HW_PINCTRL_MUXSEL7_CLR, ( 139 1.3.4.2 tls HW_PINCTRL_MUXSEL7_BANK3_PIN21 | /* Pin 72, EMI_CLKN */ 140 1.3.4.2 tls HW_PINCTRL_MUXSEL7_BANK3_PIN20 | /* Pin 70, EMI_CLK */ 141 1.3.4.2 tls HW_PINCTRL_MUXSEL7_BANK3_PIN19 | /* Pin 74, EMI_DQS1 */ 142 1.3.4.2 tls HW_PINCTRL_MUXSEL7_BANK3_PIN18 | /* Pin 73, EMI_DQS0 */ 143 1.3.4.2 tls HW_PINCTRL_MUXSEL7_BANK3_PIN17 | /* Pin 92, EMI_DQM1 */ 144 1.3.4.2 tls HW_PINCTRL_MUXSEL7_BANK3_PIN16) /* Pin 81, EMI_DQM0 */ 145 1.3.4.2 tls ); 146 1.3.4.2 tls 147 1.3.4.2 tls return; 148 1.3.4.2 tls } 149 1.3.4.2 tls 150 1.3.4.2 tls /* 151 1.3.4.2 tls * Configure EMI pins voltages to 1.8/2.5V operation and drive strength 152 1.3.4.2 tls * to "ma". 153 1.3.4.2 tls */ 154 1.3.4.2 tls static void 155 1.3.4.2 tls configure_emi_drive(int ma) 156 1.3.4.2 tls { 157 1.3.4.2 tls uint32_t drive; 158 1.3.4.2 tls 159 1.3.4.2 tls /* DRIVE 9 */ 160 1.3.4.2 tls drive = REG_RD(HW_PINCTRL_BASE + HW_PINCTRL_DRIVE9); 161 1.3.4.2 tls drive &= ~( 162 1.3.4.2 tls HW_PINCTRL_DRIVE9_BANK2_PIN15_V | /* Pin 108, EMI_A06 */ 163 1.3.4.2 tls HW_PINCTRL_DRIVE9_BANK2_PIN15_MA | 164 1.3.4.2 tls HW_PINCTRL_DRIVE9_BANK2_PIN14_V | /* Pin 107, EMI_A05 */ 165 1.3.4.2 tls HW_PINCTRL_DRIVE9_BANK2_PIN14_MA | 166 1.3.4.2 tls HW_PINCTRL_DRIVE9_BANK2_PIN13_V | /* Pin 109, EMI_A04 */ 167 1.3.4.2 tls HW_PINCTRL_DRIVE9_BANK2_PIN13_MA | 168 1.3.4.2 tls HW_PINCTRL_DRIVE9_BANK2_PIN12_V | /* Pin 110, EMI_A03 */ 169 1.3.4.2 tls HW_PINCTRL_DRIVE9_BANK2_PIN12_MA | 170 1.3.4.2 tls HW_PINCTRL_DRIVE9_BANK2_PIN11_V | /* Pin 111, EMI_A02 */ 171 1.3.4.2 tls HW_PINCTRL_DRIVE9_BANK2_PIN11_MA | 172 1.3.4.2 tls HW_PINCTRL_DRIVE9_BANK2_PIN10_V | /* Pin 112, EMI_A01 */ 173 1.3.4.2 tls HW_PINCTRL_DRIVE9_BANK2_PIN10_MA | 174 1.3.4.2 tls HW_PINCTRL_DRIVE9_BANK2_PIN09_V | /* Pin 113, EMI_A00 */ 175 1.3.4.2 tls HW_PINCTRL_DRIVE9_BANK2_PIN09_MA | 176 1.3.4.2 tls HW_PINCTRL_DRIVE9_RSRVD6 | /* Always write zeroes */ 177 1.3.4.2 tls HW_PINCTRL_DRIVE9_RSRVD5 | 178 1.3.4.2 tls HW_PINCTRL_DRIVE9_RSRVD4 | 179 1.3.4.2 tls HW_PINCTRL_DRIVE9_RSRVD3 | 180 1.3.4.2 tls HW_PINCTRL_DRIVE9_RSRVD2 | 181 1.3.4.2 tls HW_PINCTRL_DRIVE9_RSRVD1 | 182 1.3.4.2 tls HW_PINCTRL_DRIVE9_RSRVD0 183 1.3.4.2 tls ); 184 1.3.4.2 tls drive |= ( 185 1.3.4.2 tls __SHIFTIN(ma, HW_PINCTRL_DRIVE9_BANK2_PIN15_MA) | /* EMI_A06 */ 186 1.3.4.2 tls __SHIFTIN(ma, HW_PINCTRL_DRIVE9_BANK2_PIN14_MA) | /* EMI_A05 */ 187 1.3.4.2 tls __SHIFTIN(ma, HW_PINCTRL_DRIVE9_BANK2_PIN13_MA) | /* EMI_A04 */ 188 1.3.4.2 tls __SHIFTIN(ma, HW_PINCTRL_DRIVE9_BANK2_PIN12_MA) | /* EMI_A03 */ 189 1.3.4.2 tls __SHIFTIN(ma, HW_PINCTRL_DRIVE9_BANK2_PIN11_MA) | /* EMI_A02 */ 190 1.3.4.2 tls __SHIFTIN(ma, HW_PINCTRL_DRIVE9_BANK2_PIN10_MA) | /* EMI_A01 */ 191 1.3.4.2 tls __SHIFTIN(ma, HW_PINCTRL_DRIVE9_BANK2_PIN09_MA) /* EMI_A00 */ 192 1.3.4.2 tls ); 193 1.3.4.2 tls REG_WR(HW_PINCTRL_BASE + HW_PINCTRL_DRIVE9, drive); 194 1.3.4.2 tls 195 1.3.4.2 tls /* DRIVE 10 */ 196 1.3.4.2 tls drive = REG_RD(HW_PINCTRL_BASE + HW_PINCTRL_DRIVE10); 197 1.3.4.2 tls drive &= ~( 198 1.3.4.2 tls HW_PINCTRL_DRIVE10_BANK2_PIN23_V | /* Pin 117, EMI_BA1 */ 199 1.3.4.2 tls HW_PINCTRL_DRIVE10_BANK2_PIN23_MA | 200 1.3.4.2 tls HW_PINCTRL_DRIVE10_BANK2_PIN22_V | /* Pin 116, EMI_BA0 */ 201 1.3.4.2 tls HW_PINCTRL_DRIVE10_BANK2_PIN22_MA | 202 1.3.4.2 tls HW_PINCTRL_DRIVE10_BANK2_PIN21_V | /* Pin 101, EMI_A12 */ 203 1.3.4.2 tls HW_PINCTRL_DRIVE10_BANK2_PIN21_MA | 204 1.3.4.2 tls HW_PINCTRL_DRIVE10_BANK2_PIN20_V | /* Pin 102, EMI_A11 */ 205 1.3.4.2 tls HW_PINCTRL_DRIVE10_BANK2_PIN20_MA | 206 1.3.4.2 tls HW_PINCTRL_DRIVE10_BANK2_PIN19_V | /* Pin 104, EMI_A10 */ 207 1.3.4.2 tls HW_PINCTRL_DRIVE10_BANK2_PIN19_MA | 208 1.3.4.2 tls HW_PINCTRL_DRIVE10_BANK2_PIN18_V | /* Pin 103, EMI_A09 */ 209 1.3.4.2 tls HW_PINCTRL_DRIVE10_BANK2_PIN18_MA | 210 1.3.4.2 tls HW_PINCTRL_DRIVE10_BANK2_PIN17_V | /* Pin 106, EMI_A08 */ 211 1.3.4.2 tls HW_PINCTRL_DRIVE10_BANK2_PIN17_MA | 212 1.3.4.2 tls HW_PINCTRL_DRIVE10_BANK2_PIN16_V | /* Pin 105, EMI_A07 */ 213 1.3.4.2 tls HW_PINCTRL_DRIVE10_BANK2_PIN16_MA | 214 1.3.4.2 tls HW_PINCTRL_DRIVE10_RSRVD6 | /* Always write zeroes */ 215 1.3.4.2 tls HW_PINCTRL_DRIVE10_RSRVD5 | 216 1.3.4.2 tls HW_PINCTRL_DRIVE10_RSRVD4 | 217 1.3.4.2 tls HW_PINCTRL_DRIVE10_RSRVD3 | 218 1.3.4.2 tls HW_PINCTRL_DRIVE10_RSRVD2 | 219 1.3.4.2 tls HW_PINCTRL_DRIVE10_RSRVD1 | 220 1.3.4.2 tls HW_PINCTRL_DRIVE10_RSRVD0 221 1.3.4.2 tls ); 222 1.3.4.2 tls drive |= ( 223 1.3.4.2 tls __SHIFTIN(ma, HW_PINCTRL_DRIVE10_BANK2_PIN23_MA) | /* EMI_BA1 */ 224 1.3.4.2 tls __SHIFTIN(ma, HW_PINCTRL_DRIVE10_BANK2_PIN22_MA) | /* EMI_BA0 */ 225 1.3.4.2 tls __SHIFTIN(ma, HW_PINCTRL_DRIVE10_BANK2_PIN21_MA) | /* EMI_A12 */ 226 1.3.4.2 tls __SHIFTIN(ma, HW_PINCTRL_DRIVE10_BANK2_PIN20_MA) | /* EMI_A11 */ 227 1.3.4.2 tls __SHIFTIN(ma, HW_PINCTRL_DRIVE10_BANK2_PIN19_MA) | /* EMI_A10 */ 228 1.3.4.2 tls __SHIFTIN(ma, HW_PINCTRL_DRIVE10_BANK2_PIN18_MA) | /* EMI_A09 */ 229 1.3.4.2 tls __SHIFTIN(ma, HW_PINCTRL_DRIVE10_BANK2_PIN17_MA) | /* EMI_A08 */ 230 1.3.4.2 tls __SHIFTIN(ma, HW_PINCTRL_DRIVE10_BANK2_PIN16_MA) /* EMI_A07 */ 231 1.3.4.2 tls ); 232 1.3.4.2 tls REG_WR(HW_PINCTRL_BASE + HW_PINCTRL_DRIVE10, drive); 233 1.3.4.2 tls 234 1.3.4.2 tls /* DRIVE 11 */ 235 1.3.4.2 tls drive = REG_RD(HW_PINCTRL_BASE + HW_PINCTRL_DRIVE11); 236 1.3.4.2 tls drive &= ~( 237 1.3.4.2 tls HW_PINCTRL_DRIVE11_BANK2_PIN31_V | /* Pin 114, EMI_WEN */ 238 1.3.4.2 tls HW_PINCTRL_DRIVE11_BANK2_PIN31_MA | 239 1.3.4.2 tls HW_PINCTRL_DRIVE11_BANK2_PIN30_V | /* Pin 98, EMI_RASN */ 240 1.3.4.2 tls HW_PINCTRL_DRIVE11_BANK2_PIN30_MA | 241 1.3.4.2 tls HW_PINCTRL_DRIVE11_BANK2_PIN29_V | /* Pin 115, EMI_CKE */ 242 1.3.4.2 tls HW_PINCTRL_DRIVE11_BANK2_PIN29_MA | 243 1.3.4.2 tls #if 0 244 1.3.4.2 tls /* 169-Pin BGA Package */ 245 1.3.4.2 tls HW_PINCTRL_DRIVE11_BANK2_PIN26_V | /* Pin 99, EMI_CE1N */ 246 1.3.4.2 tls HW_PINCTRL_DRIVE11_BANK2_PIN26_MA | 247 1.3.4.2 tls #endif 248 1.3.4.2 tls HW_PINCTRL_DRIVE11_BANK2_PIN25_V | /* Pin 100, EMI_CE0N */ 249 1.3.4.2 tls HW_PINCTRL_DRIVE11_BANK2_PIN25_MA | 250 1.3.4.2 tls HW_PINCTRL_DRIVE11_BANK2_PIN24_V | /* Pin 97, EMI_CASN */ 251 1.3.4.2 tls HW_PINCTRL_DRIVE11_BANK2_PIN24_MA | 252 1.3.4.2 tls HW_PINCTRL_DRIVE11_RSRVD6 | /* Always write zeroes */ 253 1.3.4.2 tls HW_PINCTRL_DRIVE11_RSRVD5 | 254 1.3.4.2 tls HW_PINCTRL_DRIVE11_RSRVD4 | 255 1.3.4.2 tls HW_PINCTRL_DRIVE11_RSRVD3 | 256 1.3.4.2 tls HW_PINCTRL_DRIVE11_RSRVD2 | 257 1.3.4.2 tls HW_PINCTRL_DRIVE11_RSRVD1 | 258 1.3.4.2 tls HW_PINCTRL_DRIVE11_RSRVD0 259 1.3.4.2 tls ); 260 1.3.4.2 tls drive |= ( 261 1.3.4.2 tls __SHIFTIN(ma, HW_PINCTRL_DRIVE11_BANK2_PIN31_MA) | /* EMI_WEN */ 262 1.3.4.2 tls __SHIFTIN(ma, HW_PINCTRL_DRIVE11_BANK2_PIN30_MA) | /* EMI_RASN */ 263 1.3.4.2 tls __SHIFTIN(ma, HW_PINCTRL_DRIVE11_BANK2_PIN29_MA) | /* EMI_CKE */ 264 1.3.4.2 tls #if 0 265 1.3.4.2 tls /* 169-Pin BGA Package */ 266 1.3.4.2 tls __SHIFTIN(ma, HW_PINCTRL_DRIVE11_BANK2_PIN26_MA) | /* EMI_CE1N */ 267 1.3.4.2 tls #endif 268 1.3.4.2 tls __SHIFTIN(ma, HW_PINCTRL_DRIVE11_BANK2_PIN25_MA) | /* EMI_CE0N */ 269 1.3.4.2 tls __SHIFTIN(ma, HW_PINCTRL_DRIVE11_BANK2_PIN24_MA) /* EMI_CASN */ 270 1.3.4.2 tls ); 271 1.3.4.2 tls REG_WR(HW_PINCTRL_BASE + HW_PINCTRL_DRIVE11, drive); 272 1.3.4.2 tls 273 1.3.4.2 tls /* DRIVE 12 */ 274 1.3.4.2 tls drive = REG_RD(HW_PINCTRL_BASE + HW_PINCTRL_DRIVE12); 275 1.3.4.2 tls drive &= ~( 276 1.3.4.2 tls HW_PINCTRL_DRIVE12_BANK3_PIN07_V | /* Pin 85, EMI_D07 */ 277 1.3.4.2 tls HW_PINCTRL_DRIVE12_BANK3_PIN07_MA | 278 1.3.4.2 tls HW_PINCTRL_DRIVE12_BANK3_PIN06_V | /* Pin 84, EMI_D06 */ 279 1.3.4.2 tls HW_PINCTRL_DRIVE12_BANK3_PIN06_MA | 280 1.3.4.2 tls HW_PINCTRL_DRIVE12_BANK3_PIN05_V | /* Pin 83, EMI_D05 */ 281 1.3.4.2 tls HW_PINCTRL_DRIVE12_BANK3_PIN05_MA | 282 1.3.4.2 tls HW_PINCTRL_DRIVE12_BANK3_PIN04_V | /* Pin 82, EMI_D04 */ 283 1.3.4.2 tls HW_PINCTRL_DRIVE12_BANK3_PIN04_MA | 284 1.3.4.2 tls HW_PINCTRL_DRIVE12_BANK3_PIN03_V | /* Pin 79, EMI_D03 */ 285 1.3.4.2 tls HW_PINCTRL_DRIVE12_BANK3_PIN03_MA | 286 1.3.4.2 tls HW_PINCTRL_DRIVE12_BANK3_PIN02_V | /* Pin 77, EMI_D02 */ 287 1.3.4.2 tls HW_PINCTRL_DRIVE12_BANK3_PIN02_MA | 288 1.3.4.2 tls HW_PINCTRL_DRIVE12_BANK3_PIN01_V | /* Pin 76, EMI_D01 */ 289 1.3.4.2 tls HW_PINCTRL_DRIVE12_BANK3_PIN01_MA | 290 1.3.4.2 tls HW_PINCTRL_DRIVE12_BANK3_PIN00_V | /* Pin 75, EMI_D00 */ 291 1.3.4.2 tls HW_PINCTRL_DRIVE12_BANK3_PIN00_MA | 292 1.3.4.2 tls HW_PINCTRL_DRIVE12_RSRVD6 | /* Always write zeroes */ 293 1.3.4.2 tls HW_PINCTRL_DRIVE12_RSRVD5 | 294 1.3.4.2 tls HW_PINCTRL_DRIVE12_RSRVD4 | 295 1.3.4.2 tls HW_PINCTRL_DRIVE12_RSRVD3 | 296 1.3.4.2 tls HW_PINCTRL_DRIVE12_RSRVD2 | 297 1.3.4.2 tls HW_PINCTRL_DRIVE12_RSRVD1 | 298 1.3.4.2 tls HW_PINCTRL_DRIVE12_RSRVD0 299 1.3.4.2 tls ); 300 1.3.4.2 tls drive |= ( 301 1.3.4.2 tls __SHIFTIN(ma, HW_PINCTRL_DRIVE12_BANK3_PIN07_MA) | /* EMI_D07 */ 302 1.3.4.2 tls __SHIFTIN(ma, HW_PINCTRL_DRIVE12_BANK3_PIN06_MA) | /* EMI_D06 */ 303 1.3.4.2 tls __SHIFTIN(ma, HW_PINCTRL_DRIVE12_BANK3_PIN05_MA) | /* EMI_D05 */ 304 1.3.4.2 tls __SHIFTIN(ma, HW_PINCTRL_DRIVE12_BANK3_PIN04_MA) | /* EMI_D04 */ 305 1.3.4.2 tls __SHIFTIN(ma, HW_PINCTRL_DRIVE12_BANK3_PIN03_MA) | /* EMI_D03 */ 306 1.3.4.2 tls __SHIFTIN(ma, HW_PINCTRL_DRIVE12_BANK3_PIN02_MA) | /* EMI_D02 */ 307 1.3.4.2 tls __SHIFTIN(ma, HW_PINCTRL_DRIVE12_BANK3_PIN01_MA) | /* EMI_D01 */ 308 1.3.4.2 tls __SHIFTIN(ma, HW_PINCTRL_DRIVE12_BANK3_PIN00_MA) /* EMI_D00 */ 309 1.3.4.2 tls ); 310 1.3.4.2 tls REG_WR(HW_PINCTRL_BASE + HW_PINCTRL_DRIVE12, drive); 311 1.3.4.2 tls 312 1.3.4.2 tls /* DRIVE 13 */ 313 1.3.4.2 tls drive = REG_RD(HW_PINCTRL_BASE + HW_PINCTRL_DRIVE13); 314 1.3.4.2 tls drive &= ~( 315 1.3.4.2 tls HW_PINCTRL_DRIVE13_BANK3_PIN15_V | /* Pin 95, EMI_D15 */ 316 1.3.4.2 tls HW_PINCTRL_DRIVE13_BANK3_PIN15_MA | 317 1.3.4.2 tls HW_PINCTRL_DRIVE13_BANK3_PIN14_V | /* Pin 96, EMI_D14 */ 318 1.3.4.2 tls HW_PINCTRL_DRIVE13_BANK3_PIN14_MA | 319 1.3.4.2 tls HW_PINCTRL_DRIVE13_BANK3_PIN13_V | /* Pin 94, EMI_D13 */ 320 1.3.4.2 tls HW_PINCTRL_DRIVE13_BANK3_PIN13_MA | 321 1.3.4.2 tls HW_PINCTRL_DRIVE13_BANK3_PIN12_V | /* Pin 93, EMI_D12 */ 322 1.3.4.2 tls HW_PINCTRL_DRIVE13_BANK3_PIN12_MA | 323 1.3.4.2 tls HW_PINCTRL_DRIVE13_BANK3_PIN11_V | /* Pin 91, EMI_D11 */ 324 1.3.4.2 tls HW_PINCTRL_DRIVE13_BANK3_PIN11_MA | 325 1.3.4.2 tls HW_PINCTRL_DRIVE13_BANK3_PIN10_V | /* Pin 89, EMI_D10 */ 326 1.3.4.2 tls HW_PINCTRL_DRIVE13_BANK3_PIN10_MA | 327 1.3.4.2 tls HW_PINCTRL_DRIVE13_BANK3_PIN09_V | /* Pin 87, EMI_D09 */ 328 1.3.4.2 tls HW_PINCTRL_DRIVE13_BANK3_PIN09_MA | 329 1.3.4.2 tls HW_PINCTRL_DRIVE13_BANK3_PIN08_V | /* Pin 86, EMI_D08 */ 330 1.3.4.2 tls HW_PINCTRL_DRIVE13_BANK3_PIN08_MA | 331 1.3.4.2 tls HW_PINCTRL_DRIVE13_RSRVD6 | /* Always write zeroes */ 332 1.3.4.2 tls HW_PINCTRL_DRIVE13_RSRVD5 | 333 1.3.4.2 tls HW_PINCTRL_DRIVE13_RSRVD4 | 334 1.3.4.2 tls HW_PINCTRL_DRIVE13_RSRVD3 | 335 1.3.4.2 tls HW_PINCTRL_DRIVE13_RSRVD2 | 336 1.3.4.2 tls HW_PINCTRL_DRIVE13_RSRVD1 | 337 1.3.4.2 tls HW_PINCTRL_DRIVE13_RSRVD0 338 1.3.4.2 tls ); 339 1.3.4.2 tls drive |= ( 340 1.3.4.2 tls __SHIFTIN(ma, HW_PINCTRL_DRIVE13_BANK3_PIN15_MA) | /* EMI_D15 */ 341 1.3.4.2 tls __SHIFTIN(ma, HW_PINCTRL_DRIVE13_BANK3_PIN14_MA) | /* EMI_D14 */ 342 1.3.4.2 tls __SHIFTIN(ma, HW_PINCTRL_DRIVE13_BANK3_PIN13_MA) | /* EMI_D13 */ 343 1.3.4.2 tls __SHIFTIN(ma, HW_PINCTRL_DRIVE13_BANK3_PIN12_MA) | /* EMI_D12 */ 344 1.3.4.2 tls __SHIFTIN(ma, HW_PINCTRL_DRIVE13_BANK3_PIN11_MA) | /* EMI_D11 */ 345 1.3.4.2 tls __SHIFTIN(ma, HW_PINCTRL_DRIVE13_BANK3_PIN10_MA) | /* EMI_D10 */ 346 1.3.4.2 tls __SHIFTIN(ma, HW_PINCTRL_DRIVE13_BANK3_PIN09_MA) | /* EMI_D09 */ 347 1.3.4.2 tls __SHIFTIN(ma, HW_PINCTRL_DRIVE13_BANK3_PIN08_MA) /* EMI_D08 */ 348 1.3.4.2 tls ); 349 1.3.4.2 tls REG_WR(HW_PINCTRL_BASE + HW_PINCTRL_DRIVE13, drive); 350 1.3.4.2 tls 351 1.3.4.2 tls /* DRIVE 14 */ 352 1.3.4.2 tls drive = REG_RD(HW_PINCTRL_BASE + HW_PINCTRL_DRIVE14); 353 1.3.4.2 tls drive &= ~( 354 1.3.4.2 tls HW_PINCTRL_DRIVE14_BANK3_PIN21_V | /* Pin 72, EMI_CLKN */ 355 1.3.4.2 tls HW_PINCTRL_DRIVE14_BANK3_PIN21_MA | 356 1.3.4.2 tls HW_PINCTRL_DRIVE14_BANK3_PIN20_V | /* Pin 70, EMI_CLK */ 357 1.3.4.2 tls HW_PINCTRL_DRIVE14_BANK3_PIN20_MA | 358 1.3.4.2 tls HW_PINCTRL_DRIVE14_BANK3_PIN19_V | /* Pin 74, EMI_DQS1 */ 359 1.3.4.2 tls HW_PINCTRL_DRIVE14_BANK3_PIN19_MA | 360 1.3.4.2 tls HW_PINCTRL_DRIVE14_BANK3_PIN18_V | /* Pin 73, EMI_DQS0 */ 361 1.3.4.2 tls HW_PINCTRL_DRIVE14_BANK3_PIN18_MA | 362 1.3.4.2 tls HW_PINCTRL_DRIVE14_BANK3_PIN17_V | /* Pin 92, EMI_DQM1 */ 363 1.3.4.2 tls HW_PINCTRL_DRIVE14_BANK3_PIN17_MA | 364 1.3.4.2 tls HW_PINCTRL_DRIVE14_BANK3_PIN16_V | /* Pin 81, EMI_DQM0 */ 365 1.3.4.2 tls HW_PINCTRL_DRIVE14_BANK3_PIN16_MA | 366 1.3.4.2 tls HW_PINCTRL_DRIVE14_RSRVD6 | /* Always write zeroes */ 367 1.3.4.2 tls HW_PINCTRL_DRIVE14_RSRVD5 | 368 1.3.4.2 tls HW_PINCTRL_DRIVE14_RSRVD4 | 369 1.3.4.2 tls HW_PINCTRL_DRIVE14_RSRVD3 | 370 1.3.4.2 tls HW_PINCTRL_DRIVE14_RSRVD2 | 371 1.3.4.2 tls HW_PINCTRL_DRIVE14_RSRVD1 | 372 1.3.4.2 tls HW_PINCTRL_DRIVE14_RSRVD0 373 1.3.4.2 tls ); 374 1.3.4.2 tls drive |= ( 375 1.3.4.2 tls __SHIFTIN(ma, HW_PINCTRL_DRIVE14_BANK3_PIN21_MA) | /* EMI_CLKN */ 376 1.3.4.2 tls __SHIFTIN(ma, HW_PINCTRL_DRIVE14_BANK3_PIN20_MA) | /* EMI_CLK */ 377 1.3.4.2 tls __SHIFTIN(ma, HW_PINCTRL_DRIVE14_BANK3_PIN19_MA) | /* EMI_DQS1 */ 378 1.3.4.2 tls __SHIFTIN(ma, HW_PINCTRL_DRIVE14_BANK3_PIN18_MA) | /* EMI_DQS0 */ 379 1.3.4.2 tls __SHIFTIN(ma, HW_PINCTRL_DRIVE14_BANK3_PIN17_MA) | /* EMI_DQM1 */ 380 1.3.4.2 tls __SHIFTIN(ma, HW_PINCTRL_DRIVE14_BANK3_PIN16_MA) /* EMI_DQM0 */ 381 1.3.4.2 tls ); 382 1.3.4.2 tls REG_WR(HW_PINCTRL_BASE + HW_PINCTRL_DRIVE14, drive); 383 1.3.4.2 tls 384 1.3.4.2 tls return; 385 1.3.4.2 tls } 386 1.3.4.2 tls 387 1.3.4.2 tls /* 388 1.3.4.2 tls * Disable internal gate keepers on EMI pins. 389 1.3.4.2 tls */ 390 1.3.4.2 tls static void 391 1.3.4.2 tls disable_emi_padkeepers(void) 392 1.3.4.2 tls { 393 1.3.4.2 tls 394 1.3.4.2 tls REG_WR(HW_PINCTRL_BASE + HW_PINCTRL_PULL3_SET, ( 395 1.3.4.2 tls HW_PINCTRL_PULL3_BANK3_PIN17 | /* EMI_DQM1 */ 396 1.3.4.2 tls HW_PINCTRL_PULL3_BANK3_PIN16 | /* EMI_DQM0 */ 397 1.3.4.2 tls HW_PINCTRL_PULL3_BANK3_PIN15 | /* EMI_D15 */ 398 1.3.4.2 tls HW_PINCTRL_PULL3_BANK3_PIN14 | /* EMI_D14 */ 399 1.3.4.2 tls HW_PINCTRL_PULL3_BANK3_PIN13 | /* EMI_D13 */ 400 1.3.4.2 tls HW_PINCTRL_PULL3_BANK3_PIN12 | /* EMI_D12 */ 401 1.3.4.2 tls HW_PINCTRL_PULL3_BANK3_PIN11 | /* EMI_D11 */ 402 1.3.4.2 tls HW_PINCTRL_PULL3_BANK3_PIN10 | /* EMI_D10 */ 403 1.3.4.2 tls HW_PINCTRL_PULL3_BANK3_PIN09 | /* EMI_D09 */ 404 1.3.4.2 tls HW_PINCTRL_PULL3_BANK3_PIN08 | /* EMI_D08 */ 405 1.3.4.2 tls HW_PINCTRL_PULL3_BANK3_PIN07 | /* EMI_D07 */ 406 1.3.4.2 tls HW_PINCTRL_PULL3_BANK3_PIN06 | /* EMI_D06 */ 407 1.3.4.2 tls HW_PINCTRL_PULL3_BANK3_PIN05 | /* EMI_D05 */ 408 1.3.4.2 tls HW_PINCTRL_PULL3_BANK3_PIN04 | /* EMI_D04 */ 409 1.3.4.2 tls HW_PINCTRL_PULL3_BANK3_PIN03 | /* EMI_D03 */ 410 1.3.4.2 tls HW_PINCTRL_PULL3_BANK3_PIN02 | /* EMI_D02 */ 411 1.3.4.2 tls HW_PINCTRL_PULL3_BANK3_PIN01 | /* EMI_D01 */ 412 1.3.4.2 tls HW_PINCTRL_PULL3_BANK3_PIN00) /* EMI_D00 */ 413 1.3.4.2 tls ); 414 1.3.4.2 tls 415 1.3.4.2 tls return; 416 1.3.4.2 tls } 417 1.3.4.2 tls 418 1.3.4.2 tls /* 419 1.3.4.2 tls * Configure external SSP pins to be used for SD/MMC. 420 1.3.4.2 tls */ 421 1.3.4.2 tls static void 422 1.3.4.2 tls configure_ssp_mux(void) 423 1.3.4.2 tls { 424 1.3.4.2 tls REG_WR(HW_PINCTRL_BASE + HW_PINCTRL_MUXSEL4_CLR, ( 425 1.3.4.2 tls HW_PINCTRL_MUXSEL4_BANK2_PIN00 | /* Pin 121, SSP1_CMD */ 426 1.3.4.2 tls HW_PINCTRL_MUXSEL4_BANK2_PIN02 | /* Pin 122, SSP1_DATA0 */ 427 1.3.4.2 tls HW_PINCTRL_MUXSEL4_BANK2_PIN03 | /* Pin 123, SSP1_DATA1 */ 428 1.3.4.2 tls HW_PINCTRL_MUXSEL4_BANK2_PIN04 | /* Pin 124, SSP1_DATA2 */ 429 1.3.4.2 tls HW_PINCTRL_MUXSEL4_BANK2_PIN05 | /* Pin 125, SSP1_DATA3 */ 430 1.3.4.2 tls HW_PINCTRL_MUXSEL4_BANK2_PIN06) /* Pin 127, SSP1_SCK */ 431 1.3.4.2 tls ); 432 1.3.4.2 tls 433 1.3.4.2 tls return; 434 1.3.4.2 tls } 435 1.3.4.2 tls 436 1.3.4.2 tls /* 437 1.3.4.2 tls * Configure SSP pins drive strength to "ma". 438 1.3.4.2 tls * Out of reset, all non-EMI pins are configured as 3.3 V. 439 1.3.4.2 tls */ 440 1.3.4.2 tls static void 441 1.3.4.2 tls configure_ssp_drive(int ma) 442 1.3.4.2 tls { 443 1.3.4.2 tls uint32_t reg = REG_RD(HW_PINCTRL_BASE + HW_PINCTRL_DRIVE8); 444 1.3.4.2 tls reg &= ~( 445 1.3.4.2 tls HW_PINCTRL_DRIVE8_BANK2_PIN06_MA | /* Pin 127, SSP1_SCK */ 446 1.3.4.2 tls HW_PINCTRL_DRIVE8_BANK2_PIN05_MA | /* Pin 125, SSP1_DATA3 */ 447 1.3.4.2 tls HW_PINCTRL_DRIVE8_BANK2_PIN04_MA | /* Pin 124, SSP1_DATA2 */ 448 1.3.4.2 tls HW_PINCTRL_DRIVE8_BANK2_PIN03_MA | /* Pin 123, SSP1_DATA1 */ 449 1.3.4.2 tls HW_PINCTRL_DRIVE8_BANK2_PIN02_MA | /* Pin 122, SSP1_DATA0 */ 450 1.3.4.2 tls HW_PINCTRL_DRIVE8_BANK2_PIN00_MA /* Pin 121, SSP1_CMD */ 451 1.3.4.2 tls ); 452 1.3.4.2 tls 453 1.3.4.2 tls reg |= __SHIFTIN(ma, HW_PINCTRL_DRIVE8_BANK2_PIN06_MA) | 454 1.3.4.2 tls __SHIFTIN(ma, HW_PINCTRL_DRIVE8_BANK2_PIN05_MA) | 455 1.3.4.2 tls __SHIFTIN(ma, HW_PINCTRL_DRIVE8_BANK2_PIN04_MA) | 456 1.3.4.2 tls __SHIFTIN(ma, HW_PINCTRL_DRIVE8_BANK2_PIN03_MA) | 457 1.3.4.2 tls __SHIFTIN(ma, HW_PINCTRL_DRIVE8_BANK2_PIN02_MA) | 458 1.3.4.2 tls __SHIFTIN(ma, HW_PINCTRL_DRIVE8_BANK2_PIN00_MA 459 1.3.4.2 tls ); 460 1.3.4.2 tls 461 1.3.4.2 tls REG_WR(HW_PINCTRL_BASE + HW_PINCTRL_DRIVE8, reg); 462 1.3.4.2 tls 463 1.3.4.2 tls return; 464 1.3.4.2 tls } 465 1.3.4.2 tls 466 1.3.4.2 tls /* 467 1.3.4.2 tls * Configure SSP pull ups. 468 1.3.4.2 tls */ 469 1.3.4.2 tls static void 470 1.3.4.2 tls configure_ssp_pullups(void) 471 1.3.4.2 tls { 472 1.3.4.2 tls /* Disable pull ups for SSP and let HW take care of them. */ 473 1.3.4.2 tls // REG_WR(HW_PINCTRL_BASE + HW_PINCTRL_PULL2_CLR, ( 474 1.3.4.2 tls // HW_PINCTRL_PULL2_BANK2_PIN05 | /* Pin 125, SSP1_DATA3 */ 475 1.3.4.2 tls // HW_PINCTRL_PULL2_BANK2_PIN04 | /* Pin 124, SSP1_DATA2 */ 476 1.3.4.2 tls // HW_PINCTRL_PULL2_BANK2_PIN03 | /* Pin 123, SSP1_DATA1 */ 477 1.3.4.2 tls // HW_PINCTRL_PULL2_BANK2_PIN02 | /* Pin 122, SSP1_DATA0 */ 478 1.3.4.2 tls // HW_PINCTRL_PULL2_BANK2_PIN00 /* Pin 121, SSP1_CMD */ 479 1.3.4.2 tls // )); 480 1.3.4.2 tls 481 1.3.4.2 tls REG_WR(HW_PINCTRL_BASE + HW_PINCTRL_PULL2_SET, ( 482 1.3.4.2 tls HW_PINCTRL_PULL2_BANK2_PIN05 | /* Pin 125, SSP1_DATA3 */ 483 1.3.4.2 tls HW_PINCTRL_PULL2_BANK2_PIN04 | /* Pin 124, SSP1_DATA2 */ 484 1.3.4.2 tls HW_PINCTRL_PULL2_BANK2_PIN03 | /* Pin 123, SSP1_DATA1 */ 485 1.3.4.2 tls HW_PINCTRL_PULL2_BANK2_PIN02 | /* Pin 122, SSP1_DATA0 */ 486 1.3.4.2 tls HW_PINCTRL_PULL2_BANK2_PIN00 /* Pin 121, SSP1_CMD */ 487 1.3.4.2 tls )); 488 1.3.4.2 tls 489 1.3.4.2 tls return; 490 1.3.4.2 tls } 491 1.3.4.2 tls 492 1.3.4.2 tls /* 493 1.3.4.2 tls * Configure Debug UART MUX. 494 1.3.4.2 tls */ 495 1.3.4.2 tls static 496 1.3.4.2 tls void configure_dbuart_mux(void) 497 1.3.4.2 tls { 498 1.3.4.2 tls REG_WR(HW_PINCTRL_BASE + HW_PINCTRL_MUXSEL3_CLR, 499 1.3.4.2 tls __SHIFTIN(0x3, HW_PINCTRL_MUXSEL3_BANK1_PIN27) | 500 1.3.4.2 tls __SHIFTIN(0x3, HW_PINCTRL_MUXSEL3_BANK1_PIN26)); 501 1.3.4.2 tls REG_WR(HW_PINCTRL_BASE + HW_PINCTRL_MUXSEL3_SET, 502 1.3.4.2 tls __SHIFTIN(0x2, HW_PINCTRL_MUXSEL3_BANK1_PIN27) | 503 1.3.4.2 tls __SHIFTIN(0x2, HW_PINCTRL_MUXSEL3_BANK1_PIN26)); 504 1.3.4.2 tls 505 1.3.4.2 tls return; 506 1.3.4.2 tls } 507
Indexes created Mon Oct 20 15:10:11 GMT 2025