pinctrl_prep.c revision 1.2
1 /* $Id: pinctrl_prep.c,v 1.2 2012/12/16 19:08:44 jkunz Exp $ */ 2 3 /* 4 * Copyright (c) 2012 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Petri Laakso. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/param.h> 33 #include <sys/cdefs.h> 34 #include <sys/types.h> 35 36 #include <arm/imx/imx23_pinctrlreg.h> 37 38 #include <lib/libsa/stand.h> 39 40 #include "common.h" 41 42 static void configure_emi_mux(void); 43 static void configure_emi_drive(int); 44 static void disable_emi_padkeepers(void); 45 static void configure_ssp_mux(); 46 static void configure_ssp_drive(int); 47 static void configure_ssp_pullups(void); 48 49 /* EMI pins output drive strengths */ 50 #define DRIVE_04_MA 0x0 /* 4 mA */ 51 #define DRIVE_08_MA 0x1 /* 8 mA */ 52 #define DRIVE_12_MA 0x2 /* 12 mA */ 53 #define DRIVE_16_MA 0x3 /* 16 mA */ 54 55 /* 56 * Configure external EMI pins. 57 */ 58 int 59 pinctrl_prep(void) 60 { 61 62 REG_WR(HW_PINCTRL_BASE + HW_PINCTRL_CTRL_CLR, 63 (HW_PINCTRL_CTRL_SFTRST | HW_PINCTRL_CTRL_CLKGATE)); 64 65 /* EMI. */ 66 configure_emi_mux(); 67 configure_emi_drive(DRIVE_12_MA); 68 disable_emi_padkeepers(); 69 70 /* SSP. */ 71 configure_ssp_mux(); 72 configure_ssp_drive(DRIVE_16_MA); 73 configure_ssp_pullups(); 74 75 return 0; 76 } 77 78 /* 79 * Configure external EMI pins to be used for DRAM. 80 */ 81 static void 82 configure_emi_mux(void) 83 { 84 85 REG_WR(HW_PINCTRL_BASE + HW_PINCTRL_MUXSEL4_CLR, ( 86 HW_PINCTRL_MUXSEL4_BANK2_PIN15 | /* Pin 108, EMI_A06 */ 87 HW_PINCTRL_MUXSEL4_BANK2_PIN14 | /* Pin 107, EMI_A05 */ 88 HW_PINCTRL_MUXSEL4_BANK2_PIN13 | /* Pin 109, EMI_A04 */ 89 HW_PINCTRL_MUXSEL4_BANK2_PIN12 | /* Pin 110, EMI_A03 */ 90 HW_PINCTRL_MUXSEL4_BANK2_PIN11 | /* Pin 111, EMI_A02 */ 91 HW_PINCTRL_MUXSEL4_BANK2_PIN10 | /* Pin 112, EMI_A01 */ 92 HW_PINCTRL_MUXSEL4_BANK2_PIN09) /* Pin 113, EMI_A00 */ 93 ); 94 95 REG_WR(HW_PINCTRL_BASE + HW_PINCTRL_MUXSEL5_CLR, ( 96 HW_PINCTRL_MUXSEL5_BANK2_PIN31 | /* Pin 114, EMI_WEN */ 97 HW_PINCTRL_MUXSEL5_BANK2_PIN30 | /* Pin 98, EMI_RASN */ 98 HW_PINCTRL_MUXSEL5_BANK2_PIN29 | /* Pin 115, EMI_CKE */ 99 #if 0 100 /* 169-Pin BGA Package */ 101 HW_PINCTRL_MUXSEL5_BANK2_PIN26 | /* Pin 99, EMI_CE1N */ 102 #endif 103 HW_PINCTRL_MUXSEL5_BANK2_PIN25 | /* Pin 100, EMI_CE0N */ 104 HW_PINCTRL_MUXSEL5_BANK2_PIN24 | /* Pin 97, EMI_CASN */ 105 HW_PINCTRL_MUXSEL5_BANK2_PIN23 | /* Pin 117, EMI_BA1 */ 106 HW_PINCTRL_MUXSEL5_BANK2_PIN22 | /* Pin 116, EMI_BA0 */ 107 HW_PINCTRL_MUXSEL5_BANK2_PIN21 | /* Pin 101, EMI_A12 */ 108 HW_PINCTRL_MUXSEL5_BANK2_PIN20 | /* Pin 102, EMI_A11 */ 109 HW_PINCTRL_MUXSEL5_BANK2_PIN19 | /* Pin 104, EMI_A10 */ 110 HW_PINCTRL_MUXSEL5_BANK2_PIN18 | /* Pin 103, EMI_A09 */ 111 HW_PINCTRL_MUXSEL5_BANK2_PIN17 | /* Pin 106, EMI_A08 */ 112 HW_PINCTRL_MUXSEL5_BANK2_PIN16) /* Pin 105, EMI_A07 */ 113 ); 114 115 REG_WR(HW_PINCTRL_BASE + HW_PINCTRL_MUXSEL6_CLR, ( 116 HW_PINCTRL_MUXSEL6_BANK3_PIN15 | /* Pin 95, EMI_D15 */ 117 HW_PINCTRL_MUXSEL6_BANK3_PIN14 | /* Pin 96, EMI_D14 */ 118 HW_PINCTRL_MUXSEL6_BANK3_PIN13 | /* Pin 94, EMI_D13 */ 119 HW_PINCTRL_MUXSEL6_BANK3_PIN12 | /* Pin 93, EMI_D12 */ 120 HW_PINCTRL_MUXSEL6_BANK3_PIN11 | /* Pin 91, EMI_D11 */ 121 HW_PINCTRL_MUXSEL6_BANK3_PIN10 | /* Pin 89, EMI_D10 */ 122 HW_PINCTRL_MUXSEL6_BANK3_PIN09 | /* Pin 87, EMI_D09 */ 123 HW_PINCTRL_MUXSEL6_BANK3_PIN08 | /* Pin 86, EMI_D08 */ 124 HW_PINCTRL_MUXSEL6_BANK3_PIN07 | /* Pin 85, EMI_D07 */ 125 HW_PINCTRL_MUXSEL6_BANK3_PIN06 | /* Pin 84, EMI_D06 */ 126 HW_PINCTRL_MUXSEL6_BANK3_PIN05 | /* Pin 83, EMI_D05 */ 127 HW_PINCTRL_MUXSEL6_BANK3_PIN04 | /* Pin 82, EMI_D04 */ 128 HW_PINCTRL_MUXSEL6_BANK3_PIN03 | /* Pin 79, EMI_D03 */ 129 HW_PINCTRL_MUXSEL6_BANK3_PIN02 | /* Pin 77, EMI_D02 */ 130 HW_PINCTRL_MUXSEL6_BANK3_PIN01 | /* Pin 76, EMI_D01 */ 131 HW_PINCTRL_MUXSEL6_BANK3_PIN00) /* Pin 75, EMI_D00 */ 132 ); 133 134 REG_WR(HW_PINCTRL_BASE + HW_PINCTRL_MUXSEL7_CLR, ( 135 HW_PINCTRL_MUXSEL7_BANK3_PIN21 | /* Pin 72, EMI_CLKN */ 136 HW_PINCTRL_MUXSEL7_BANK3_PIN20 | /* Pin 70, EMI_CLK */ 137 HW_PINCTRL_MUXSEL7_BANK3_PIN19 | /* Pin 74, EMI_DQS1 */ 138 HW_PINCTRL_MUXSEL7_BANK3_PIN18 | /* Pin 73, EMI_DQS0 */ 139 HW_PINCTRL_MUXSEL7_BANK3_PIN17 | /* Pin 92, EMI_DQM1 */ 140 HW_PINCTRL_MUXSEL7_BANK3_PIN16) /* Pin 81, EMI_DQM0 */ 141 ); 142 143 return; 144 } 145 146 /* 147 * Configure EMI pins voltages to 1.8/2.5V operation and drive strength 148 * to "ma". 149 */ 150 static void 151 configure_emi_drive(int ma) 152 { 153 uint32_t drive; 154 155 /* DRIVE 9 */ 156 drive = REG_RD(HW_PINCTRL_BASE + HW_PINCTRL_DRIVE9); 157 drive &= ~( 158 HW_PINCTRL_DRIVE9_BANK2_PIN15_V | /* Pin 108, EMI_A06 */ 159 HW_PINCTRL_DRIVE9_BANK2_PIN15_MA | 160 HW_PINCTRL_DRIVE9_BANK2_PIN14_V | /* Pin 107, EMI_A05 */ 161 HW_PINCTRL_DRIVE9_BANK2_PIN14_MA | 162 HW_PINCTRL_DRIVE9_BANK2_PIN13_V | /* Pin 109, EMI_A04 */ 163 HW_PINCTRL_DRIVE9_BANK2_PIN13_MA | 164 HW_PINCTRL_DRIVE9_BANK2_PIN12_V | /* Pin 110, EMI_A03 */ 165 HW_PINCTRL_DRIVE9_BANK2_PIN12_MA | 166 HW_PINCTRL_DRIVE9_BANK2_PIN11_V | /* Pin 111, EMI_A02 */ 167 HW_PINCTRL_DRIVE9_BANK2_PIN11_MA | 168 HW_PINCTRL_DRIVE9_BANK2_PIN10_V | /* Pin 112, EMI_A01 */ 169 HW_PINCTRL_DRIVE9_BANK2_PIN10_MA | 170 HW_PINCTRL_DRIVE9_BANK2_PIN09_V | /* Pin 113, EMI_A00 */ 171 HW_PINCTRL_DRIVE9_BANK2_PIN09_MA | 172 HW_PINCTRL_DRIVE9_RSRVD6 | /* Always write zeroes */ 173 HW_PINCTRL_DRIVE9_RSRVD5 | 174 HW_PINCTRL_DRIVE9_RSRVD4 | 175 HW_PINCTRL_DRIVE9_RSRVD3 | 176 HW_PINCTRL_DRIVE9_RSRVD2 | 177 HW_PINCTRL_DRIVE9_RSRVD1 | 178 HW_PINCTRL_DRIVE9_RSRVD0 179 ); 180 drive |= ( 181 __SHIFTIN(ma, HW_PINCTRL_DRIVE9_BANK2_PIN15_MA) | /* EMI_A06 */ 182 __SHIFTIN(ma, HW_PINCTRL_DRIVE9_BANK2_PIN14_MA) | /* EMI_A05 */ 183 __SHIFTIN(ma, HW_PINCTRL_DRIVE9_BANK2_PIN13_MA) | /* EMI_A04 */ 184 __SHIFTIN(ma, HW_PINCTRL_DRIVE9_BANK2_PIN12_MA) | /* EMI_A03 */ 185 __SHIFTIN(ma, HW_PINCTRL_DRIVE9_BANK2_PIN11_MA) | /* EMI_A02 */ 186 __SHIFTIN(ma, HW_PINCTRL_DRIVE9_BANK2_PIN10_MA) | /* EMI_A01 */ 187 __SHIFTIN(ma, HW_PINCTRL_DRIVE9_BANK2_PIN09_MA) /* EMI_A00 */ 188 ); 189 REG_WR(HW_PINCTRL_BASE + HW_PINCTRL_DRIVE9, drive); 190 191 /* DRIVE 10 */ 192 drive = REG_RD(HW_PINCTRL_BASE + HW_PINCTRL_DRIVE10); 193 drive &= ~( 194 HW_PINCTRL_DRIVE10_BANK2_PIN23_V | /* Pin 117, EMI_BA1 */ 195 HW_PINCTRL_DRIVE10_BANK2_PIN23_MA | 196 HW_PINCTRL_DRIVE10_BANK2_PIN22_V | /* Pin 116, EMI_BA0 */ 197 HW_PINCTRL_DRIVE10_BANK2_PIN22_MA | 198 HW_PINCTRL_DRIVE10_BANK2_PIN21_V | /* Pin 101, EMI_A12 */ 199 HW_PINCTRL_DRIVE10_BANK2_PIN21_MA | 200 HW_PINCTRL_DRIVE10_BANK2_PIN20_V | /* Pin 102, EMI_A11 */ 201 HW_PINCTRL_DRIVE10_BANK2_PIN20_MA | 202 HW_PINCTRL_DRIVE10_BANK2_PIN19_V | /* Pin 104, EMI_A10 */ 203 HW_PINCTRL_DRIVE10_BANK2_PIN19_MA | 204 HW_PINCTRL_DRIVE10_BANK2_PIN18_V | /* Pin 103, EMI_A09 */ 205 HW_PINCTRL_DRIVE10_BANK2_PIN18_MA | 206 HW_PINCTRL_DRIVE10_BANK2_PIN17_V | /* Pin 106, EMI_A08 */ 207 HW_PINCTRL_DRIVE10_BANK2_PIN17_MA | 208 HW_PINCTRL_DRIVE10_BANK2_PIN16_V | /* Pin 105, EMI_A07 */ 209 HW_PINCTRL_DRIVE10_BANK2_PIN16_MA | 210 HW_PINCTRL_DRIVE10_RSRVD6 | /* Always write zeroes */ 211 HW_PINCTRL_DRIVE10_RSRVD5 | 212 HW_PINCTRL_DRIVE10_RSRVD4 | 213 HW_PINCTRL_DRIVE10_RSRVD3 | 214 HW_PINCTRL_DRIVE10_RSRVD2 | 215 HW_PINCTRL_DRIVE10_RSRVD1 | 216 HW_PINCTRL_DRIVE10_RSRVD0 217 ); 218 drive |= ( 219 __SHIFTIN(ma, HW_PINCTRL_DRIVE10_BANK2_PIN23_MA) | /* EMI_BA1 */ 220 __SHIFTIN(ma, HW_PINCTRL_DRIVE10_BANK2_PIN22_MA) | /* EMI_BA0 */ 221 __SHIFTIN(ma, HW_PINCTRL_DRIVE10_BANK2_PIN21_MA) | /* EMI_A12 */ 222 __SHIFTIN(ma, HW_PINCTRL_DRIVE10_BANK2_PIN20_MA) | /* EMI_A11 */ 223 __SHIFTIN(ma, HW_PINCTRL_DRIVE10_BANK2_PIN19_MA) | /* EMI_A10 */ 224 __SHIFTIN(ma, HW_PINCTRL_DRIVE10_BANK2_PIN18_MA) | /* EMI_A09 */ 225 __SHIFTIN(ma, HW_PINCTRL_DRIVE10_BANK2_PIN17_MA) | /* EMI_A08 */ 226 __SHIFTIN(ma, HW_PINCTRL_DRIVE10_BANK2_PIN16_MA) /* EMI_A07 */ 227 ); 228 REG_WR(HW_PINCTRL_BASE + HW_PINCTRL_DRIVE10, drive); 229 230 /* DRIVE 11 */ 231 drive = REG_RD(HW_PINCTRL_BASE + HW_PINCTRL_DRIVE11); 232 drive &= ~( 233 HW_PINCTRL_DRIVE11_BANK2_PIN31_V | /* Pin 114, EMI_WEN */ 234 HW_PINCTRL_DRIVE11_BANK2_PIN31_MA | 235 HW_PINCTRL_DRIVE11_BANK2_PIN30_V | /* Pin 98, EMI_RASN */ 236 HW_PINCTRL_DRIVE11_BANK2_PIN30_MA | 237 HW_PINCTRL_DRIVE11_BANK2_PIN29_V | /* Pin 115, EMI_CKE */ 238 HW_PINCTRL_DRIVE11_BANK2_PIN29_MA | 239 #if 0 240 /* 169-Pin BGA Package */ 241 HW_PINCTRL_DRIVE11_BANK2_PIN26_V | /* Pin 99, EMI_CE1N */ 242 HW_PINCTRL_DRIVE11_BANK2_PIN26_MA | 243 #endif 244 HW_PINCTRL_DRIVE11_BANK2_PIN25_V | /* Pin 100, EMI_CE0N */ 245 HW_PINCTRL_DRIVE11_BANK2_PIN25_MA | 246 HW_PINCTRL_DRIVE11_BANK2_PIN24_V | /* Pin 97, EMI_CASN */ 247 HW_PINCTRL_DRIVE11_BANK2_PIN24_MA | 248 HW_PINCTRL_DRIVE11_RSRVD6 | /* Always write zeroes */ 249 HW_PINCTRL_DRIVE11_RSRVD5 | 250 HW_PINCTRL_DRIVE11_RSRVD4 | 251 HW_PINCTRL_DRIVE11_RSRVD3 | 252 HW_PINCTRL_DRIVE11_RSRVD2 | 253 HW_PINCTRL_DRIVE11_RSRVD1 | 254 HW_PINCTRL_DRIVE11_RSRVD0 255 ); 256 drive |= ( 257 __SHIFTIN(ma, HW_PINCTRL_DRIVE11_BANK2_PIN31_MA) | /* EMI_WEN */ 258 __SHIFTIN(ma, HW_PINCTRL_DRIVE11_BANK2_PIN30_MA) | /* EMI_RASN */ 259 __SHIFTIN(ma, HW_PINCTRL_DRIVE11_BANK2_PIN29_MA) | /* EMI_CKE */ 260 #if 0 261 /* 169-Pin BGA Package */ 262 __SHIFTIN(ma, HW_PINCTRL_DRIVE11_BANK2_PIN26_MA) | /* EMI_CE1N */ 263 #endif 264 __SHIFTIN(ma, HW_PINCTRL_DRIVE11_BANK2_PIN25_MA) | /* EMI_CE0N */ 265 __SHIFTIN(ma, HW_PINCTRL_DRIVE11_BANK2_PIN24_MA) /* EMI_CASN */ 266 ); 267 REG_WR(HW_PINCTRL_BASE + HW_PINCTRL_DRIVE11, drive); 268 269 /* DRIVE 12 */ 270 drive = REG_RD(HW_PINCTRL_BASE + HW_PINCTRL_DRIVE12); 271 drive &= ~( 272 HW_PINCTRL_DRIVE12_BANK3_PIN07_V | /* Pin 85, EMI_D07 */ 273 HW_PINCTRL_DRIVE12_BANK3_PIN07_MA | 274 HW_PINCTRL_DRIVE12_BANK3_PIN06_V | /* Pin 84, EMI_D06 */ 275 HW_PINCTRL_DRIVE12_BANK3_PIN06_MA | 276 HW_PINCTRL_DRIVE12_BANK3_PIN05_V | /* Pin 83, EMI_D05 */ 277 HW_PINCTRL_DRIVE12_BANK3_PIN05_MA | 278 HW_PINCTRL_DRIVE12_BANK3_PIN04_V | /* Pin 82, EMI_D04 */ 279 HW_PINCTRL_DRIVE12_BANK3_PIN04_MA | 280 HW_PINCTRL_DRIVE12_BANK3_PIN03_V | /* Pin 79, EMI_D03 */ 281 HW_PINCTRL_DRIVE12_BANK3_PIN03_MA | 282 HW_PINCTRL_DRIVE12_BANK3_PIN02_V | /* Pin 77, EMI_D02 */ 283 HW_PINCTRL_DRIVE12_BANK3_PIN02_MA | 284 HW_PINCTRL_DRIVE12_BANK3_PIN01_V | /* Pin 76, EMI_D01 */ 285 HW_PINCTRL_DRIVE12_BANK3_PIN01_MA | 286 HW_PINCTRL_DRIVE12_BANK3_PIN00_V | /* Pin 75, EMI_D00 */ 287 HW_PINCTRL_DRIVE12_BANK3_PIN00_MA | 288 HW_PINCTRL_DRIVE12_RSRVD6 | /* Always write zeroes */ 289 HW_PINCTRL_DRIVE12_RSRVD5 | 290 HW_PINCTRL_DRIVE12_RSRVD4 | 291 HW_PINCTRL_DRIVE12_RSRVD3 | 292 HW_PINCTRL_DRIVE12_RSRVD2 | 293 HW_PINCTRL_DRIVE12_RSRVD1 | 294 HW_PINCTRL_DRIVE12_RSRVD0 295 ); 296 drive |= ( 297 __SHIFTIN(ma, HW_PINCTRL_DRIVE12_BANK3_PIN07_MA) | /* EMI_D07 */ 298 __SHIFTIN(ma, HW_PINCTRL_DRIVE12_BANK3_PIN06_MA) | /* EMI_D06 */ 299 __SHIFTIN(ma, HW_PINCTRL_DRIVE12_BANK3_PIN05_MA) | /* EMI_D05 */ 300 __SHIFTIN(ma, HW_PINCTRL_DRIVE12_BANK3_PIN04_MA) | /* EMI_D04 */ 301 __SHIFTIN(ma, HW_PINCTRL_DRIVE12_BANK3_PIN03_MA) | /* EMI_D03 */ 302 __SHIFTIN(ma, HW_PINCTRL_DRIVE12_BANK3_PIN02_MA) | /* EMI_D02 */ 303 __SHIFTIN(ma, HW_PINCTRL_DRIVE12_BANK3_PIN01_MA) | /* EMI_D01 */ 304 __SHIFTIN(ma, HW_PINCTRL_DRIVE12_BANK3_PIN00_MA) /* EMI_D00 */ 305 ); 306 REG_WR(HW_PINCTRL_BASE + HW_PINCTRL_DRIVE12, drive); 307 308 /* DRIVE 13 */ 309 drive = REG_RD(HW_PINCTRL_BASE + HW_PINCTRL_DRIVE13); 310 drive &= ~( 311 HW_PINCTRL_DRIVE13_BANK3_PIN15_V | /* Pin 95, EMI_D15 */ 312 HW_PINCTRL_DRIVE13_BANK3_PIN15_MA | 313 HW_PINCTRL_DRIVE13_BANK3_PIN14_V | /* Pin 96, EMI_D14 */ 314 HW_PINCTRL_DRIVE13_BANK3_PIN14_MA | 315 HW_PINCTRL_DRIVE13_BANK3_PIN13_V | /* Pin 94, EMI_D13 */ 316 HW_PINCTRL_DRIVE13_BANK3_PIN13_MA | 317 HW_PINCTRL_DRIVE13_BANK3_PIN12_V | /* Pin 93, EMI_D12 */ 318 HW_PINCTRL_DRIVE13_BANK3_PIN12_MA | 319 HW_PINCTRL_DRIVE13_BANK3_PIN11_V | /* Pin 91, EMI_D11 */ 320 HW_PINCTRL_DRIVE13_BANK3_PIN11_MA | 321 HW_PINCTRL_DRIVE13_BANK3_PIN10_V | /* Pin 89, EMI_D10 */ 322 HW_PINCTRL_DRIVE13_BANK3_PIN10_MA | 323 HW_PINCTRL_DRIVE13_BANK3_PIN09_V | /* Pin 87, EMI_D09 */ 324 HW_PINCTRL_DRIVE13_BANK3_PIN09_MA | 325 HW_PINCTRL_DRIVE13_BANK3_PIN08_V | /* Pin 86, EMI_D08 */ 326 HW_PINCTRL_DRIVE13_BANK3_PIN08_MA | 327 HW_PINCTRL_DRIVE13_RSRVD6 | /* Always write zeroes */ 328 HW_PINCTRL_DRIVE13_RSRVD5 | 329 HW_PINCTRL_DRIVE13_RSRVD4 | 330 HW_PINCTRL_DRIVE13_RSRVD3 | 331 HW_PINCTRL_DRIVE13_RSRVD2 | 332 HW_PINCTRL_DRIVE13_RSRVD1 | 333 HW_PINCTRL_DRIVE13_RSRVD0 334 ); 335 drive |= ( 336 __SHIFTIN(ma, HW_PINCTRL_DRIVE13_BANK3_PIN15_MA) | /* EMI_D15 */ 337 __SHIFTIN(ma, HW_PINCTRL_DRIVE13_BANK3_PIN14_MA) | /* EMI_D14 */ 338 __SHIFTIN(ma, HW_PINCTRL_DRIVE13_BANK3_PIN13_MA) | /* EMI_D13 */ 339 __SHIFTIN(ma, HW_PINCTRL_DRIVE13_BANK3_PIN12_MA) | /* EMI_D12 */ 340 __SHIFTIN(ma, HW_PINCTRL_DRIVE13_BANK3_PIN11_MA) | /* EMI_D11 */ 341 __SHIFTIN(ma, HW_PINCTRL_DRIVE13_BANK3_PIN10_MA) | /* EMI_D10 */ 342 __SHIFTIN(ma, HW_PINCTRL_DRIVE13_BANK3_PIN09_MA) | /* EMI_D09 */ 343 __SHIFTIN(ma, HW_PINCTRL_DRIVE13_BANK3_PIN08_MA) /* EMI_D08 */ 344 ); 345 REG_WR(HW_PINCTRL_BASE + HW_PINCTRL_DRIVE13, drive); 346 347 /* DRIVE 14 */ 348 drive = REG_RD(HW_PINCTRL_BASE + HW_PINCTRL_DRIVE14); 349 drive &= ~( 350 HW_PINCTRL_DRIVE14_BANK3_PIN21_V | /* Pin 72, EMI_CLKN */ 351 HW_PINCTRL_DRIVE14_BANK3_PIN21_MA | 352 HW_PINCTRL_DRIVE14_BANK3_PIN20_V | /* Pin 70, EMI_CLK */ 353 HW_PINCTRL_DRIVE14_BANK3_PIN20_MA | 354 HW_PINCTRL_DRIVE14_BANK3_PIN19_V | /* Pin 74, EMI_DQS1 */ 355 HW_PINCTRL_DRIVE14_BANK3_PIN19_MA | 356 HW_PINCTRL_DRIVE14_BANK3_PIN18_V | /* Pin 73, EMI_DQS0 */ 357 HW_PINCTRL_DRIVE14_BANK3_PIN18_MA | 358 HW_PINCTRL_DRIVE14_BANK3_PIN17_V | /* Pin 92, EMI_DQM1 */ 359 HW_PINCTRL_DRIVE14_BANK3_PIN17_MA | 360 HW_PINCTRL_DRIVE14_BANK3_PIN16_V | /* Pin 81, EMI_DQM0 */ 361 HW_PINCTRL_DRIVE14_BANK3_PIN16_MA | 362 HW_PINCTRL_DRIVE14_RSRVD6 | /* Always write zeroes */ 363 HW_PINCTRL_DRIVE14_RSRVD5 | 364 HW_PINCTRL_DRIVE14_RSRVD4 | 365 HW_PINCTRL_DRIVE14_RSRVD3 | 366 HW_PINCTRL_DRIVE14_RSRVD2 | 367 HW_PINCTRL_DRIVE14_RSRVD1 | 368 HW_PINCTRL_DRIVE14_RSRVD0 369 ); 370 drive |= ( 371 __SHIFTIN(ma, HW_PINCTRL_DRIVE14_BANK3_PIN21_MA) | /* EMI_CLKN */ 372 __SHIFTIN(ma, HW_PINCTRL_DRIVE14_BANK3_PIN20_MA) | /* EMI_CLK */ 373 __SHIFTIN(ma, HW_PINCTRL_DRIVE14_BANK3_PIN19_MA) | /* EMI_DQS1 */ 374 __SHIFTIN(ma, HW_PINCTRL_DRIVE14_BANK3_PIN18_MA) | /* EMI_DQS0 */ 375 __SHIFTIN(ma, HW_PINCTRL_DRIVE14_BANK3_PIN17_MA) | /* EMI_DQM1 */ 376 __SHIFTIN(ma, HW_PINCTRL_DRIVE14_BANK3_PIN16_MA) /* EMI_DQM0 */ 377 ); 378 REG_WR(HW_PINCTRL_BASE + HW_PINCTRL_DRIVE14, drive); 379 380 return; 381 } 382 383 /* 384 * Disable internal gate keepers on EMI pins. 385 */ 386 static void 387 disable_emi_padkeepers(void) 388 { 389 390 REG_WR(HW_PINCTRL_BASE + HW_PINCTRL_PULL3_SET, ( 391 HW_PINCTRL_PULL3_BANK3_PIN17 | /* EMI_DQM1 */ 392 HW_PINCTRL_PULL3_BANK3_PIN16 | /* EMI_DQM0 */ 393 HW_PINCTRL_PULL3_BANK3_PIN15 | /* EMI_D15 */ 394 HW_PINCTRL_PULL3_BANK3_PIN14 | /* EMI_D14 */ 395 HW_PINCTRL_PULL3_BANK3_PIN13 | /* EMI_D13 */ 396 HW_PINCTRL_PULL3_BANK3_PIN12 | /* EMI_D12 */ 397 HW_PINCTRL_PULL3_BANK3_PIN11 | /* EMI_D11 */ 398 HW_PINCTRL_PULL3_BANK3_PIN10 | /* EMI_D10 */ 399 HW_PINCTRL_PULL3_BANK3_PIN09 | /* EMI_D09 */ 400 HW_PINCTRL_PULL3_BANK3_PIN08 | /* EMI_D08 */ 401 HW_PINCTRL_PULL3_BANK3_PIN07 | /* EMI_D07 */ 402 HW_PINCTRL_PULL3_BANK3_PIN06 | /* EMI_D06 */ 403 HW_PINCTRL_PULL3_BANK3_PIN05 | /* EMI_D05 */ 404 HW_PINCTRL_PULL3_BANK3_PIN04 | /* EMI_D04 */ 405 HW_PINCTRL_PULL3_BANK3_PIN03 | /* EMI_D03 */ 406 HW_PINCTRL_PULL3_BANK3_PIN02 | /* EMI_D02 */ 407 HW_PINCTRL_PULL3_BANK3_PIN01 | /* EMI_D01 */ 408 HW_PINCTRL_PULL3_BANK3_PIN00) /* EMI_D00 */ 409 ); 410 411 return; 412 } 413 414 /* 415 * Configure external SSP pins to be used for SD/MMC. 416 */ 417 static void 418 configure_ssp_mux(void) 419 { 420 REG_WR(HW_PINCTRL_BASE + HW_PINCTRL_MUXSEL4_CLR, ( 421 HW_PINCTRL_MUXSEL4_BANK2_PIN00 | /* Pin 121, SSP1_CMD */ 422 HW_PINCTRL_MUXSEL4_BANK2_PIN02 | /* Pin 122, SSP1_DATA0 */ 423 HW_PINCTRL_MUXSEL4_BANK2_PIN03 | /* Pin 123, SSP1_DATA1 */ 424 HW_PINCTRL_MUXSEL4_BANK2_PIN04 | /* Pin 124, SSP1_DATA2 */ 425 HW_PINCTRL_MUXSEL4_BANK2_PIN05 | /* Pin 125, SSP1_DATA3 */ 426 HW_PINCTRL_MUXSEL4_BANK2_PIN06) /* Pin 127, SSP1_SCK */ 427 ); 428 429 return; 430 } 431 432 /* 433 * Configure SSP pins drive strength to "ma". 434 * Out of reset, all non-EMI pins are configured as 3.3 V. 435 */ 436 static void 437 configure_ssp_drive(int ma) 438 { 439 uint32_t reg = REG_RD(HW_PINCTRL_BASE + HW_PINCTRL_DRIVE8); 440 reg &= ~( 441 HW_PINCTRL_DRIVE8_BANK2_PIN06_MA | /* Pin 127, SSP1_SCK */ 442 HW_PINCTRL_DRIVE8_BANK2_PIN05_MA | /* Pin 125, SSP1_DATA3 */ 443 HW_PINCTRL_DRIVE8_BANK2_PIN04_MA | /* Pin 124, SSP1_DATA2 */ 444 HW_PINCTRL_DRIVE8_BANK2_PIN03_MA | /* Pin 123, SSP1_DATA1 */ 445 HW_PINCTRL_DRIVE8_BANK2_PIN02_MA | /* Pin 122, SSP1_DATA0 */ 446 HW_PINCTRL_DRIVE8_BANK2_PIN00_MA /* Pin 121, SSP1_CMD */ 447 ); 448 449 reg |= __SHIFTIN(ma, HW_PINCTRL_DRIVE8_BANK2_PIN06_MA) | 450 __SHIFTIN(ma, HW_PINCTRL_DRIVE8_BANK2_PIN05_MA) | 451 __SHIFTIN(ma, HW_PINCTRL_DRIVE8_BANK2_PIN04_MA) | 452 __SHIFTIN(ma, HW_PINCTRL_DRIVE8_BANK2_PIN03_MA) | 453 __SHIFTIN(ma, HW_PINCTRL_DRIVE8_BANK2_PIN02_MA) | 454 __SHIFTIN(ma, HW_PINCTRL_DRIVE8_BANK2_PIN00_MA 455 ); 456 457 REG_WR(HW_PINCTRL_BASE + HW_PINCTRL_DRIVE8, reg); 458 459 return; 460 } 461 462 /* 463 * Configure SSP pull ups. 464 */ 465 static void 466 configure_ssp_pullups(void) 467 { 468 /* Disable pull ups for SSP and let HW take care of them. */ 469 // REG_WR(HW_PINCTRL_BASE + HW_PINCTRL_PULL2_CLR, ( 470 // HW_PINCTRL_PULL2_BANK2_PIN05 | /* Pin 125, SSP1_DATA3 */ 471 // HW_PINCTRL_PULL2_BANK2_PIN04 | /* Pin 124, SSP1_DATA2 */ 472 // HW_PINCTRL_PULL2_BANK2_PIN03 | /* Pin 123, SSP1_DATA1 */ 473 // HW_PINCTRL_PULL2_BANK2_PIN02 | /* Pin 122, SSP1_DATA0 */ 474 // HW_PINCTRL_PULL2_BANK2_PIN00 /* Pin 121, SSP1_CMD */ 475 // )); 476 477 REG_WR(HW_PINCTRL_BASE + HW_PINCTRL_PULL2_SET, ( 478 HW_PINCTRL_PULL2_BANK2_PIN05 | /* Pin 125, SSP1_DATA3 */ 479 HW_PINCTRL_PULL2_BANK2_PIN04 | /* Pin 124, SSP1_DATA2 */ 480 HW_PINCTRL_PULL2_BANK2_PIN03 | /* Pin 123, SSP1_DATA1 */ 481 HW_PINCTRL_PULL2_BANK2_PIN02 | /* Pin 122, SSP1_DATA0 */ 482 HW_PINCTRL_PULL2_BANK2_PIN00 /* Pin 121, SSP1_CMD */ 483 )); 484 485 return; 486 } 487
Indexes created Fri Sep 26 20:09:58 GMT 2025