pinctrl_prep.c revision 1.3.4.2
1 /* $Id: pinctrl_prep.c,v 1.3.4.2 2013/02/25 00:28:38 tls Exp $ */ 2 3 /* 4 * Copyright (c) 2012 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Petri Laakso. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/param.h> 33 #include <sys/cdefs.h> 34 #include <sys/types.h> 35 36 #include <arm/imx/imx23_pinctrlreg.h> 37 38 #include <lib/libsa/stand.h> 39 40 #include "common.h" 41 42 static void configure_emi_mux(void); 43 static void configure_emi_drive(int); 44 static void disable_emi_padkeepers(void); 45 static void configure_ssp_mux(void); 46 static void configure_ssp_drive(int); 47 static void configure_ssp_pullups(void); 48 static void configure_dbuart_mux(void); 49 50 /* EMI pins output drive strengths */ 51 #define DRIVE_04_MA 0x0 /* 4 mA */ 52 #define DRIVE_08_MA 0x1 /* 8 mA */ 53 #define DRIVE_12_MA 0x2 /* 12 mA */ 54 #define DRIVE_16_MA 0x3 /* 16 mA */ 55 56 /* 57 * Configure external EMI pins. 58 */ 59 int 60 pinctrl_prep(void) 61 { 62 63 REG_WR(HW_PINCTRL_BASE + HW_PINCTRL_CTRL_CLR, 64 (HW_PINCTRL_CTRL_SFTRST | HW_PINCTRL_CTRL_CLKGATE)); 65 66 /* EMI. */ 67 configure_emi_mux(); 68 configure_emi_drive(DRIVE_12_MA); 69 disable_emi_padkeepers(); 70 71 /* SSP. */ 72 configure_ssp_mux(); 73 configure_ssp_drive(DRIVE_16_MA); 74 configure_ssp_pullups(); 75 76 /* Debug UART. */ 77 configure_dbuart_mux(); 78 79 return 0; 80 } 81 82 /* 83 * Configure external EMI pins to be used for DRAM. 84 */ 85 static void 86 configure_emi_mux(void) 87 { 88 89 REG_WR(HW_PINCTRL_BASE + HW_PINCTRL_MUXSEL4_CLR, ( 90 HW_PINCTRL_MUXSEL4_BANK2_PIN15 | /* Pin 108, EMI_A06 */ 91 HW_PINCTRL_MUXSEL4_BANK2_PIN14 | /* Pin 107, EMI_A05 */ 92 HW_PINCTRL_MUXSEL4_BANK2_PIN13 | /* Pin 109, EMI_A04 */ 93 HW_PINCTRL_MUXSEL4_BANK2_PIN12 | /* Pin 110, EMI_A03 */ 94 HW_PINCTRL_MUXSEL4_BANK2_PIN11 | /* Pin 111, EMI_A02 */ 95 HW_PINCTRL_MUXSEL4_BANK2_PIN10 | /* Pin 112, EMI_A01 */ 96 HW_PINCTRL_MUXSEL4_BANK2_PIN09) /* Pin 113, EMI_A00 */ 97 ); 98 99 REG_WR(HW_PINCTRL_BASE + HW_PINCTRL_MUXSEL5_CLR, ( 100 HW_PINCTRL_MUXSEL5_BANK2_PIN31 | /* Pin 114, EMI_WEN */ 101 HW_PINCTRL_MUXSEL5_BANK2_PIN30 | /* Pin 98, EMI_RASN */ 102 HW_PINCTRL_MUXSEL5_BANK2_PIN29 | /* Pin 115, EMI_CKE */ 103 #if 0 104 /* 169-Pin BGA Package */ 105 HW_PINCTRL_MUXSEL5_BANK2_PIN26 | /* Pin 99, EMI_CE1N */ 106 #endif 107 HW_PINCTRL_MUXSEL5_BANK2_PIN25 | /* Pin 100, EMI_CE0N */ 108 HW_PINCTRL_MUXSEL5_BANK2_PIN24 | /* Pin 97, EMI_CASN */ 109 HW_PINCTRL_MUXSEL5_BANK2_PIN23 | /* Pin 117, EMI_BA1 */ 110 HW_PINCTRL_MUXSEL5_BANK2_PIN22 | /* Pin 116, EMI_BA0 */ 111 HW_PINCTRL_MUXSEL5_BANK2_PIN21 | /* Pin 101, EMI_A12 */ 112 HW_PINCTRL_MUXSEL5_BANK2_PIN20 | /* Pin 102, EMI_A11 */ 113 HW_PINCTRL_MUXSEL5_BANK2_PIN19 | /* Pin 104, EMI_A10 */ 114 HW_PINCTRL_MUXSEL5_BANK2_PIN18 | /* Pin 103, EMI_A09 */ 115 HW_PINCTRL_MUXSEL5_BANK2_PIN17 | /* Pin 106, EMI_A08 */ 116 HW_PINCTRL_MUXSEL5_BANK2_PIN16) /* Pin 105, EMI_A07 */ 117 ); 118 119 REG_WR(HW_PINCTRL_BASE + HW_PINCTRL_MUXSEL6_CLR, ( 120 HW_PINCTRL_MUXSEL6_BANK3_PIN15 | /* Pin 95, EMI_D15 */ 121 HW_PINCTRL_MUXSEL6_BANK3_PIN14 | /* Pin 96, EMI_D14 */ 122 HW_PINCTRL_MUXSEL6_BANK3_PIN13 | /* Pin 94, EMI_D13 */ 123 HW_PINCTRL_MUXSEL6_BANK3_PIN12 | /* Pin 93, EMI_D12 */ 124 HW_PINCTRL_MUXSEL6_BANK3_PIN11 | /* Pin 91, EMI_D11 */ 125 HW_PINCTRL_MUXSEL6_BANK3_PIN10 | /* Pin 89, EMI_D10 */ 126 HW_PINCTRL_MUXSEL6_BANK3_PIN09 | /* Pin 87, EMI_D09 */ 127 HW_PINCTRL_MUXSEL6_BANK3_PIN08 | /* Pin 86, EMI_D08 */ 128 HW_PINCTRL_MUXSEL6_BANK3_PIN07 | /* Pin 85, EMI_D07 */ 129 HW_PINCTRL_MUXSEL6_BANK3_PIN06 | /* Pin 84, EMI_D06 */ 130 HW_PINCTRL_MUXSEL6_BANK3_PIN05 | /* Pin 83, EMI_D05 */ 131 HW_PINCTRL_MUXSEL6_BANK3_PIN04 | /* Pin 82, EMI_D04 */ 132 HW_PINCTRL_MUXSEL6_BANK3_PIN03 | /* Pin 79, EMI_D03 */ 133 HW_PINCTRL_MUXSEL6_BANK3_PIN02 | /* Pin 77, EMI_D02 */ 134 HW_PINCTRL_MUXSEL6_BANK3_PIN01 | /* Pin 76, EMI_D01 */ 135 HW_PINCTRL_MUXSEL6_BANK3_PIN00) /* Pin 75, EMI_D00 */ 136 ); 137 138 REG_WR(HW_PINCTRL_BASE + HW_PINCTRL_MUXSEL7_CLR, ( 139 HW_PINCTRL_MUXSEL7_BANK3_PIN21 | /* Pin 72, EMI_CLKN */ 140 HW_PINCTRL_MUXSEL7_BANK3_PIN20 | /* Pin 70, EMI_CLK */ 141 HW_PINCTRL_MUXSEL7_BANK3_PIN19 | /* Pin 74, EMI_DQS1 */ 142 HW_PINCTRL_MUXSEL7_BANK3_PIN18 | /* Pin 73, EMI_DQS0 */ 143 HW_PINCTRL_MUXSEL7_BANK3_PIN17 | /* Pin 92, EMI_DQM1 */ 144 HW_PINCTRL_MUXSEL7_BANK3_PIN16) /* Pin 81, EMI_DQM0 */ 145 ); 146 147 return; 148 } 149 150 /* 151 * Configure EMI pins voltages to 1.8/2.5V operation and drive strength 152 * to "ma". 153 */ 154 static void 155 configure_emi_drive(int ma) 156 { 157 uint32_t drive; 158 159 /* DRIVE 9 */ 160 drive = REG_RD(HW_PINCTRL_BASE + HW_PINCTRL_DRIVE9); 161 drive &= ~( 162 HW_PINCTRL_DRIVE9_BANK2_PIN15_V | /* Pin 108, EMI_A06 */ 163 HW_PINCTRL_DRIVE9_BANK2_PIN15_MA | 164 HW_PINCTRL_DRIVE9_BANK2_PIN14_V | /* Pin 107, EMI_A05 */ 165 HW_PINCTRL_DRIVE9_BANK2_PIN14_MA | 166 HW_PINCTRL_DRIVE9_BANK2_PIN13_V | /* Pin 109, EMI_A04 */ 167 HW_PINCTRL_DRIVE9_BANK2_PIN13_MA | 168 HW_PINCTRL_DRIVE9_BANK2_PIN12_V | /* Pin 110, EMI_A03 */ 169 HW_PINCTRL_DRIVE9_BANK2_PIN12_MA | 170 HW_PINCTRL_DRIVE9_BANK2_PIN11_V | /* Pin 111, EMI_A02 */ 171 HW_PINCTRL_DRIVE9_BANK2_PIN11_MA | 172 HW_PINCTRL_DRIVE9_BANK2_PIN10_V | /* Pin 112, EMI_A01 */ 173 HW_PINCTRL_DRIVE9_BANK2_PIN10_MA | 174 HW_PINCTRL_DRIVE9_BANK2_PIN09_V | /* Pin 113, EMI_A00 */ 175 HW_PINCTRL_DRIVE9_BANK2_PIN09_MA | 176 HW_PINCTRL_DRIVE9_RSRVD6 | /* Always write zeroes */ 177 HW_PINCTRL_DRIVE9_RSRVD5 | 178 HW_PINCTRL_DRIVE9_RSRVD4 | 179 HW_PINCTRL_DRIVE9_RSRVD3 | 180 HW_PINCTRL_DRIVE9_RSRVD2 | 181 HW_PINCTRL_DRIVE9_RSRVD1 | 182 HW_PINCTRL_DRIVE9_RSRVD0 183 ); 184 drive |= ( 185 __SHIFTIN(ma, HW_PINCTRL_DRIVE9_BANK2_PIN15_MA) | /* EMI_A06 */ 186 __SHIFTIN(ma, HW_PINCTRL_DRIVE9_BANK2_PIN14_MA) | /* EMI_A05 */ 187 __SHIFTIN(ma, HW_PINCTRL_DRIVE9_BANK2_PIN13_MA) | /* EMI_A04 */ 188 __SHIFTIN(ma, HW_PINCTRL_DRIVE9_BANK2_PIN12_MA) | /* EMI_A03 */ 189 __SHIFTIN(ma, HW_PINCTRL_DRIVE9_BANK2_PIN11_MA) | /* EMI_A02 */ 190 __SHIFTIN(ma, HW_PINCTRL_DRIVE9_BANK2_PIN10_MA) | /* EMI_A01 */ 191 __SHIFTIN(ma, HW_PINCTRL_DRIVE9_BANK2_PIN09_MA) /* EMI_A00 */ 192 ); 193 REG_WR(HW_PINCTRL_BASE + HW_PINCTRL_DRIVE9, drive); 194 195 /* DRIVE 10 */ 196 drive = REG_RD(HW_PINCTRL_BASE + HW_PINCTRL_DRIVE10); 197 drive &= ~( 198 HW_PINCTRL_DRIVE10_BANK2_PIN23_V | /* Pin 117, EMI_BA1 */ 199 HW_PINCTRL_DRIVE10_BANK2_PIN23_MA | 200 HW_PINCTRL_DRIVE10_BANK2_PIN22_V | /* Pin 116, EMI_BA0 */ 201 HW_PINCTRL_DRIVE10_BANK2_PIN22_MA | 202 HW_PINCTRL_DRIVE10_BANK2_PIN21_V | /* Pin 101, EMI_A12 */ 203 HW_PINCTRL_DRIVE10_BANK2_PIN21_MA | 204 HW_PINCTRL_DRIVE10_BANK2_PIN20_V | /* Pin 102, EMI_A11 */ 205 HW_PINCTRL_DRIVE10_BANK2_PIN20_MA | 206 HW_PINCTRL_DRIVE10_BANK2_PIN19_V | /* Pin 104, EMI_A10 */ 207 HW_PINCTRL_DRIVE10_BANK2_PIN19_MA | 208 HW_PINCTRL_DRIVE10_BANK2_PIN18_V | /* Pin 103, EMI_A09 */ 209 HW_PINCTRL_DRIVE10_BANK2_PIN18_MA | 210 HW_PINCTRL_DRIVE10_BANK2_PIN17_V | /* Pin 106, EMI_A08 */ 211 HW_PINCTRL_DRIVE10_BANK2_PIN17_MA | 212 HW_PINCTRL_DRIVE10_BANK2_PIN16_V | /* Pin 105, EMI_A07 */ 213 HW_PINCTRL_DRIVE10_BANK2_PIN16_MA | 214 HW_PINCTRL_DRIVE10_RSRVD6 | /* Always write zeroes */ 215 HW_PINCTRL_DRIVE10_RSRVD5 | 216 HW_PINCTRL_DRIVE10_RSRVD4 | 217 HW_PINCTRL_DRIVE10_RSRVD3 | 218 HW_PINCTRL_DRIVE10_RSRVD2 | 219 HW_PINCTRL_DRIVE10_RSRVD1 | 220 HW_PINCTRL_DRIVE10_RSRVD0 221 ); 222 drive |= ( 223 __SHIFTIN(ma, HW_PINCTRL_DRIVE10_BANK2_PIN23_MA) | /* EMI_BA1 */ 224 __SHIFTIN(ma, HW_PINCTRL_DRIVE10_BANK2_PIN22_MA) | /* EMI_BA0 */ 225 __SHIFTIN(ma, HW_PINCTRL_DRIVE10_BANK2_PIN21_MA) | /* EMI_A12 */ 226 __SHIFTIN(ma, HW_PINCTRL_DRIVE10_BANK2_PIN20_MA) | /* EMI_A11 */ 227 __SHIFTIN(ma, HW_PINCTRL_DRIVE10_BANK2_PIN19_MA) | /* EMI_A10 */ 228 __SHIFTIN(ma, HW_PINCTRL_DRIVE10_BANK2_PIN18_MA) | /* EMI_A09 */ 229 __SHIFTIN(ma, HW_PINCTRL_DRIVE10_BANK2_PIN17_MA) | /* EMI_A08 */ 230 __SHIFTIN(ma, HW_PINCTRL_DRIVE10_BANK2_PIN16_MA) /* EMI_A07 */ 231 ); 232 REG_WR(HW_PINCTRL_BASE + HW_PINCTRL_DRIVE10, drive); 233 234 /* DRIVE 11 */ 235 drive = REG_RD(HW_PINCTRL_BASE + HW_PINCTRL_DRIVE11); 236 drive &= ~( 237 HW_PINCTRL_DRIVE11_BANK2_PIN31_V | /* Pin 114, EMI_WEN */ 238 HW_PINCTRL_DRIVE11_BANK2_PIN31_MA | 239 HW_PINCTRL_DRIVE11_BANK2_PIN30_V | /* Pin 98, EMI_RASN */ 240 HW_PINCTRL_DRIVE11_BANK2_PIN30_MA | 241 HW_PINCTRL_DRIVE11_BANK2_PIN29_V | /* Pin 115, EMI_CKE */ 242 HW_PINCTRL_DRIVE11_BANK2_PIN29_MA | 243 #if 0 244 /* 169-Pin BGA Package */ 245 HW_PINCTRL_DRIVE11_BANK2_PIN26_V | /* Pin 99, EMI_CE1N */ 246 HW_PINCTRL_DRIVE11_BANK2_PIN26_MA | 247 #endif 248 HW_PINCTRL_DRIVE11_BANK2_PIN25_V | /* Pin 100, EMI_CE0N */ 249 HW_PINCTRL_DRIVE11_BANK2_PIN25_MA | 250 HW_PINCTRL_DRIVE11_BANK2_PIN24_V | /* Pin 97, EMI_CASN */ 251 HW_PINCTRL_DRIVE11_BANK2_PIN24_MA | 252 HW_PINCTRL_DRIVE11_RSRVD6 | /* Always write zeroes */ 253 HW_PINCTRL_DRIVE11_RSRVD5 | 254 HW_PINCTRL_DRIVE11_RSRVD4 | 255 HW_PINCTRL_DRIVE11_RSRVD3 | 256 HW_PINCTRL_DRIVE11_RSRVD2 | 257 HW_PINCTRL_DRIVE11_RSRVD1 | 258 HW_PINCTRL_DRIVE11_RSRVD0 259 ); 260 drive |= ( 261 __SHIFTIN(ma, HW_PINCTRL_DRIVE11_BANK2_PIN31_MA) | /* EMI_WEN */ 262 __SHIFTIN(ma, HW_PINCTRL_DRIVE11_BANK2_PIN30_MA) | /* EMI_RASN */ 263 __SHIFTIN(ma, HW_PINCTRL_DRIVE11_BANK2_PIN29_MA) | /* EMI_CKE */ 264 #if 0 265 /* 169-Pin BGA Package */ 266 __SHIFTIN(ma, HW_PINCTRL_DRIVE11_BANK2_PIN26_MA) | /* EMI_CE1N */ 267 #endif 268 __SHIFTIN(ma, HW_PINCTRL_DRIVE11_BANK2_PIN25_MA) | /* EMI_CE0N */ 269 __SHIFTIN(ma, HW_PINCTRL_DRIVE11_BANK2_PIN24_MA) /* EMI_CASN */ 270 ); 271 REG_WR(HW_PINCTRL_BASE + HW_PINCTRL_DRIVE11, drive); 272 273 /* DRIVE 12 */ 274 drive = REG_RD(HW_PINCTRL_BASE + HW_PINCTRL_DRIVE12); 275 drive &= ~( 276 HW_PINCTRL_DRIVE12_BANK3_PIN07_V | /* Pin 85, EMI_D07 */ 277 HW_PINCTRL_DRIVE12_BANK3_PIN07_MA | 278 HW_PINCTRL_DRIVE12_BANK3_PIN06_V | /* Pin 84, EMI_D06 */ 279 HW_PINCTRL_DRIVE12_BANK3_PIN06_MA | 280 HW_PINCTRL_DRIVE12_BANK3_PIN05_V | /* Pin 83, EMI_D05 */ 281 HW_PINCTRL_DRIVE12_BANK3_PIN05_MA | 282 HW_PINCTRL_DRIVE12_BANK3_PIN04_V | /* Pin 82, EMI_D04 */ 283 HW_PINCTRL_DRIVE12_BANK3_PIN04_MA | 284 HW_PINCTRL_DRIVE12_BANK3_PIN03_V | /* Pin 79, EMI_D03 */ 285 HW_PINCTRL_DRIVE12_BANK3_PIN03_MA | 286 HW_PINCTRL_DRIVE12_BANK3_PIN02_V | /* Pin 77, EMI_D02 */ 287 HW_PINCTRL_DRIVE12_BANK3_PIN02_MA | 288 HW_PINCTRL_DRIVE12_BANK3_PIN01_V | /* Pin 76, EMI_D01 */ 289 HW_PINCTRL_DRIVE12_BANK3_PIN01_MA | 290 HW_PINCTRL_DRIVE12_BANK3_PIN00_V | /* Pin 75, EMI_D00 */ 291 HW_PINCTRL_DRIVE12_BANK3_PIN00_MA | 292 HW_PINCTRL_DRIVE12_RSRVD6 | /* Always write zeroes */ 293 HW_PINCTRL_DRIVE12_RSRVD5 | 294 HW_PINCTRL_DRIVE12_RSRVD4 | 295 HW_PINCTRL_DRIVE12_RSRVD3 | 296 HW_PINCTRL_DRIVE12_RSRVD2 | 297 HW_PINCTRL_DRIVE12_RSRVD1 | 298 HW_PINCTRL_DRIVE12_RSRVD0 299 ); 300 drive |= ( 301 __SHIFTIN(ma, HW_PINCTRL_DRIVE12_BANK3_PIN07_MA) | /* EMI_D07 */ 302 __SHIFTIN(ma, HW_PINCTRL_DRIVE12_BANK3_PIN06_MA) | /* EMI_D06 */ 303 __SHIFTIN(ma, HW_PINCTRL_DRIVE12_BANK3_PIN05_MA) | /* EMI_D05 */ 304 __SHIFTIN(ma, HW_PINCTRL_DRIVE12_BANK3_PIN04_MA) | /* EMI_D04 */ 305 __SHIFTIN(ma, HW_PINCTRL_DRIVE12_BANK3_PIN03_MA) | /* EMI_D03 */ 306 __SHIFTIN(ma, HW_PINCTRL_DRIVE12_BANK3_PIN02_MA) | /* EMI_D02 */ 307 __SHIFTIN(ma, HW_PINCTRL_DRIVE12_BANK3_PIN01_MA) | /* EMI_D01 */ 308 __SHIFTIN(ma, HW_PINCTRL_DRIVE12_BANK3_PIN00_MA) /* EMI_D00 */ 309 ); 310 REG_WR(HW_PINCTRL_BASE + HW_PINCTRL_DRIVE12, drive); 311 312 /* DRIVE 13 */ 313 drive = REG_RD(HW_PINCTRL_BASE + HW_PINCTRL_DRIVE13); 314 drive &= ~( 315 HW_PINCTRL_DRIVE13_BANK3_PIN15_V | /* Pin 95, EMI_D15 */ 316 HW_PINCTRL_DRIVE13_BANK3_PIN15_MA | 317 HW_PINCTRL_DRIVE13_BANK3_PIN14_V | /* Pin 96, EMI_D14 */ 318 HW_PINCTRL_DRIVE13_BANK3_PIN14_MA | 319 HW_PINCTRL_DRIVE13_BANK3_PIN13_V | /* Pin 94, EMI_D13 */ 320 HW_PINCTRL_DRIVE13_BANK3_PIN13_MA | 321 HW_PINCTRL_DRIVE13_BANK3_PIN12_V | /* Pin 93, EMI_D12 */ 322 HW_PINCTRL_DRIVE13_BANK3_PIN12_MA | 323 HW_PINCTRL_DRIVE13_BANK3_PIN11_V | /* Pin 91, EMI_D11 */ 324 HW_PINCTRL_DRIVE13_BANK3_PIN11_MA | 325 HW_PINCTRL_DRIVE13_BANK3_PIN10_V | /* Pin 89, EMI_D10 */ 326 HW_PINCTRL_DRIVE13_BANK3_PIN10_MA | 327 HW_PINCTRL_DRIVE13_BANK3_PIN09_V | /* Pin 87, EMI_D09 */ 328 HW_PINCTRL_DRIVE13_BANK3_PIN09_MA | 329 HW_PINCTRL_DRIVE13_BANK3_PIN08_V | /* Pin 86, EMI_D08 */ 330 HW_PINCTRL_DRIVE13_BANK3_PIN08_MA | 331 HW_PINCTRL_DRIVE13_RSRVD6 | /* Always write zeroes */ 332 HW_PINCTRL_DRIVE13_RSRVD5 | 333 HW_PINCTRL_DRIVE13_RSRVD4 | 334 HW_PINCTRL_DRIVE13_RSRVD3 | 335 HW_PINCTRL_DRIVE13_RSRVD2 | 336 HW_PINCTRL_DRIVE13_RSRVD1 | 337 HW_PINCTRL_DRIVE13_RSRVD0 338 ); 339 drive |= ( 340 __SHIFTIN(ma, HW_PINCTRL_DRIVE13_BANK3_PIN15_MA) | /* EMI_D15 */ 341 __SHIFTIN(ma, HW_PINCTRL_DRIVE13_BANK3_PIN14_MA) | /* EMI_D14 */ 342 __SHIFTIN(ma, HW_PINCTRL_DRIVE13_BANK3_PIN13_MA) | /* EMI_D13 */ 343 __SHIFTIN(ma, HW_PINCTRL_DRIVE13_BANK3_PIN12_MA) | /* EMI_D12 */ 344 __SHIFTIN(ma, HW_PINCTRL_DRIVE13_BANK3_PIN11_MA) | /* EMI_D11 */ 345 __SHIFTIN(ma, HW_PINCTRL_DRIVE13_BANK3_PIN10_MA) | /* EMI_D10 */ 346 __SHIFTIN(ma, HW_PINCTRL_DRIVE13_BANK3_PIN09_MA) | /* EMI_D09 */ 347 __SHIFTIN(ma, HW_PINCTRL_DRIVE13_BANK3_PIN08_MA) /* EMI_D08 */ 348 ); 349 REG_WR(HW_PINCTRL_BASE + HW_PINCTRL_DRIVE13, drive); 350 351 /* DRIVE 14 */ 352 drive = REG_RD(HW_PINCTRL_BASE + HW_PINCTRL_DRIVE14); 353 drive &= ~( 354 HW_PINCTRL_DRIVE14_BANK3_PIN21_V | /* Pin 72, EMI_CLKN */ 355 HW_PINCTRL_DRIVE14_BANK3_PIN21_MA | 356 HW_PINCTRL_DRIVE14_BANK3_PIN20_V | /* Pin 70, EMI_CLK */ 357 HW_PINCTRL_DRIVE14_BANK3_PIN20_MA | 358 HW_PINCTRL_DRIVE14_BANK3_PIN19_V | /* Pin 74, EMI_DQS1 */ 359 HW_PINCTRL_DRIVE14_BANK3_PIN19_MA | 360 HW_PINCTRL_DRIVE14_BANK3_PIN18_V | /* Pin 73, EMI_DQS0 */ 361 HW_PINCTRL_DRIVE14_BANK3_PIN18_MA | 362 HW_PINCTRL_DRIVE14_BANK3_PIN17_V | /* Pin 92, EMI_DQM1 */ 363 HW_PINCTRL_DRIVE14_BANK3_PIN17_MA | 364 HW_PINCTRL_DRIVE14_BANK3_PIN16_V | /* Pin 81, EMI_DQM0 */ 365 HW_PINCTRL_DRIVE14_BANK3_PIN16_MA | 366 HW_PINCTRL_DRIVE14_RSRVD6 | /* Always write zeroes */ 367 HW_PINCTRL_DRIVE14_RSRVD5 | 368 HW_PINCTRL_DRIVE14_RSRVD4 | 369 HW_PINCTRL_DRIVE14_RSRVD3 | 370 HW_PINCTRL_DRIVE14_RSRVD2 | 371 HW_PINCTRL_DRIVE14_RSRVD1 | 372 HW_PINCTRL_DRIVE14_RSRVD0 373 ); 374 drive |= ( 375 __SHIFTIN(ma, HW_PINCTRL_DRIVE14_BANK3_PIN21_MA) | /* EMI_CLKN */ 376 __SHIFTIN(ma, HW_PINCTRL_DRIVE14_BANK3_PIN20_MA) | /* EMI_CLK */ 377 __SHIFTIN(ma, HW_PINCTRL_DRIVE14_BANK3_PIN19_MA) | /* EMI_DQS1 */ 378 __SHIFTIN(ma, HW_PINCTRL_DRIVE14_BANK3_PIN18_MA) | /* EMI_DQS0 */ 379 __SHIFTIN(ma, HW_PINCTRL_DRIVE14_BANK3_PIN17_MA) | /* EMI_DQM1 */ 380 __SHIFTIN(ma, HW_PINCTRL_DRIVE14_BANK3_PIN16_MA) /* EMI_DQM0 */ 381 ); 382 REG_WR(HW_PINCTRL_BASE + HW_PINCTRL_DRIVE14, drive); 383 384 return; 385 } 386 387 /* 388 * Disable internal gate keepers on EMI pins. 389 */ 390 static void 391 disable_emi_padkeepers(void) 392 { 393 394 REG_WR(HW_PINCTRL_BASE + HW_PINCTRL_PULL3_SET, ( 395 HW_PINCTRL_PULL3_BANK3_PIN17 | /* EMI_DQM1 */ 396 HW_PINCTRL_PULL3_BANK3_PIN16 | /* EMI_DQM0 */ 397 HW_PINCTRL_PULL3_BANK3_PIN15 | /* EMI_D15 */ 398 HW_PINCTRL_PULL3_BANK3_PIN14 | /* EMI_D14 */ 399 HW_PINCTRL_PULL3_BANK3_PIN13 | /* EMI_D13 */ 400 HW_PINCTRL_PULL3_BANK3_PIN12 | /* EMI_D12 */ 401 HW_PINCTRL_PULL3_BANK3_PIN11 | /* EMI_D11 */ 402 HW_PINCTRL_PULL3_BANK3_PIN10 | /* EMI_D10 */ 403 HW_PINCTRL_PULL3_BANK3_PIN09 | /* EMI_D09 */ 404 HW_PINCTRL_PULL3_BANK3_PIN08 | /* EMI_D08 */ 405 HW_PINCTRL_PULL3_BANK3_PIN07 | /* EMI_D07 */ 406 HW_PINCTRL_PULL3_BANK3_PIN06 | /* EMI_D06 */ 407 HW_PINCTRL_PULL3_BANK3_PIN05 | /* EMI_D05 */ 408 HW_PINCTRL_PULL3_BANK3_PIN04 | /* EMI_D04 */ 409 HW_PINCTRL_PULL3_BANK3_PIN03 | /* EMI_D03 */ 410 HW_PINCTRL_PULL3_BANK3_PIN02 | /* EMI_D02 */ 411 HW_PINCTRL_PULL3_BANK3_PIN01 | /* EMI_D01 */ 412 HW_PINCTRL_PULL3_BANK3_PIN00) /* EMI_D00 */ 413 ); 414 415 return; 416 } 417 418 /* 419 * Configure external SSP pins to be used for SD/MMC. 420 */ 421 static void 422 configure_ssp_mux(void) 423 { 424 REG_WR(HW_PINCTRL_BASE + HW_PINCTRL_MUXSEL4_CLR, ( 425 HW_PINCTRL_MUXSEL4_BANK2_PIN00 | /* Pin 121, SSP1_CMD */ 426 HW_PINCTRL_MUXSEL4_BANK2_PIN02 | /* Pin 122, SSP1_DATA0 */ 427 HW_PINCTRL_MUXSEL4_BANK2_PIN03 | /* Pin 123, SSP1_DATA1 */ 428 HW_PINCTRL_MUXSEL4_BANK2_PIN04 | /* Pin 124, SSP1_DATA2 */ 429 HW_PINCTRL_MUXSEL4_BANK2_PIN05 | /* Pin 125, SSP1_DATA3 */ 430 HW_PINCTRL_MUXSEL4_BANK2_PIN06) /* Pin 127, SSP1_SCK */ 431 ); 432 433 return; 434 } 435 436 /* 437 * Configure SSP pins drive strength to "ma". 438 * Out of reset, all non-EMI pins are configured as 3.3 V. 439 */ 440 static void 441 configure_ssp_drive(int ma) 442 { 443 uint32_t reg = REG_RD(HW_PINCTRL_BASE + HW_PINCTRL_DRIVE8); 444 reg &= ~( 445 HW_PINCTRL_DRIVE8_BANK2_PIN06_MA | /* Pin 127, SSP1_SCK */ 446 HW_PINCTRL_DRIVE8_BANK2_PIN05_MA | /* Pin 125, SSP1_DATA3 */ 447 HW_PINCTRL_DRIVE8_BANK2_PIN04_MA | /* Pin 124, SSP1_DATA2 */ 448 HW_PINCTRL_DRIVE8_BANK2_PIN03_MA | /* Pin 123, SSP1_DATA1 */ 449 HW_PINCTRL_DRIVE8_BANK2_PIN02_MA | /* Pin 122, SSP1_DATA0 */ 450 HW_PINCTRL_DRIVE8_BANK2_PIN00_MA /* Pin 121, SSP1_CMD */ 451 ); 452 453 reg |= __SHIFTIN(ma, HW_PINCTRL_DRIVE8_BANK2_PIN06_MA) | 454 __SHIFTIN(ma, HW_PINCTRL_DRIVE8_BANK2_PIN05_MA) | 455 __SHIFTIN(ma, HW_PINCTRL_DRIVE8_BANK2_PIN04_MA) | 456 __SHIFTIN(ma, HW_PINCTRL_DRIVE8_BANK2_PIN03_MA) | 457 __SHIFTIN(ma, HW_PINCTRL_DRIVE8_BANK2_PIN02_MA) | 458 __SHIFTIN(ma, HW_PINCTRL_DRIVE8_BANK2_PIN00_MA 459 ); 460 461 REG_WR(HW_PINCTRL_BASE + HW_PINCTRL_DRIVE8, reg); 462 463 return; 464 } 465 466 /* 467 * Configure SSP pull ups. 468 */ 469 static void 470 configure_ssp_pullups(void) 471 { 472 /* Disable pull ups for SSP and let HW take care of them. */ 473 // REG_WR(HW_PINCTRL_BASE + HW_PINCTRL_PULL2_CLR, ( 474 // HW_PINCTRL_PULL2_BANK2_PIN05 | /* Pin 125, SSP1_DATA3 */ 475 // HW_PINCTRL_PULL2_BANK2_PIN04 | /* Pin 124, SSP1_DATA2 */ 476 // HW_PINCTRL_PULL2_BANK2_PIN03 | /* Pin 123, SSP1_DATA1 */ 477 // HW_PINCTRL_PULL2_BANK2_PIN02 | /* Pin 122, SSP1_DATA0 */ 478 // HW_PINCTRL_PULL2_BANK2_PIN00 /* Pin 121, SSP1_CMD */ 479 // )); 480 481 REG_WR(HW_PINCTRL_BASE + HW_PINCTRL_PULL2_SET, ( 482 HW_PINCTRL_PULL2_BANK2_PIN05 | /* Pin 125, SSP1_DATA3 */ 483 HW_PINCTRL_PULL2_BANK2_PIN04 | /* Pin 124, SSP1_DATA2 */ 484 HW_PINCTRL_PULL2_BANK2_PIN03 | /* Pin 123, SSP1_DATA1 */ 485 HW_PINCTRL_PULL2_BANK2_PIN02 | /* Pin 122, SSP1_DATA0 */ 486 HW_PINCTRL_PULL2_BANK2_PIN00 /* Pin 121, SSP1_CMD */ 487 )); 488 489 return; 490 } 491 492 /* 493 * Configure Debug UART MUX. 494 */ 495 static 496 void configure_dbuart_mux(void) 497 { 498 REG_WR(HW_PINCTRL_BASE + HW_PINCTRL_MUXSEL3_CLR, 499 __SHIFTIN(0x3, HW_PINCTRL_MUXSEL3_BANK1_PIN27) | 500 __SHIFTIN(0x3, HW_PINCTRL_MUXSEL3_BANK1_PIN26)); 501 REG_WR(HW_PINCTRL_BASE + HW_PINCTRL_MUXSEL3_SET, 502 __SHIFTIN(0x2, HW_PINCTRL_MUXSEL3_BANK1_PIN27) | 503 __SHIFTIN(0x2, HW_PINCTRL_MUXSEL3_BANK1_PIN26)); 504 505 return; 506 } 507
Indexes created Wed Oct 15 16:09:53 GMT 2025