power_prep.c revision 1.3.2.2
1 1.3.2.2 yamt /* $Id: power_prep.c,v 1.3.2.2 2013/01/16 05:32:56 yamt Exp $ */ 2 1.3.2.2 yamt 3 1.3.2.2 yamt /* 4 1.3.2.2 yamt * Copyright (c) 2012 The NetBSD Foundation, Inc. 5 1.3.2.2 yamt * All rights reserved. 6 1.3.2.2 yamt * 7 1.3.2.2 yamt * This code is derived from software contributed to The NetBSD Foundation 8 1.3.2.2 yamt * by Petri Laakso. 9 1.3.2.2 yamt * 10 1.3.2.2 yamt * Redistribution and use in source and binary forms, with or without 11 1.3.2.2 yamt * modification, are permitted provided that the following conditions 12 1.3.2.2 yamt * are met: 13 1.3.2.2 yamt * 1. Redistributions of source code must retain the above copyright 14 1.3.2.2 yamt * notice, this list of conditions and the following disclaimer. 15 1.3.2.2 yamt * 2. Redistributions in binary form must reproduce the above copyright 16 1.3.2.2 yamt * notice, this list of conditions and the following disclaimer in the 17 1.3.2.2 yamt * documentation and/or other materials provided with the distribution. 18 1.3.2.2 yamt * 19 1.3.2.2 yamt * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 1.3.2.2 yamt * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 1.3.2.2 yamt * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 1.3.2.2 yamt * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 1.3.2.2 yamt * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 1.3.2.2 yamt * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 1.3.2.2 yamt * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 1.3.2.2 yamt * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 1.3.2.2 yamt * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 1.3.2.2 yamt * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 1.3.2.2 yamt * POSSIBILITY OF SUCH DAMAGE. 30 1.3.2.2 yamt */ 31 1.3.2.2 yamt 32 1.3.2.2 yamt #include <sys/param.h> 33 1.3.2.2 yamt #include <sys/cdefs.h> 34 1.3.2.2 yamt #include <sys/types.h> 35 1.3.2.2 yamt 36 1.3.2.2 yamt #include <arm/imx/imx23_powerreg.h> 37 1.3.2.2 yamt 38 1.3.2.2 yamt #include <lib/libsa/stand.h> 39 1.3.2.2 yamt 40 1.3.2.2 yamt #include "common.h" 41 1.3.2.2 yamt 42 1.3.2.2 yamt void charge_4p2_capacitance(void); 43 1.3.2.2 yamt void enable_4p2_linreg(void); 44 1.3.2.2 yamt void enable_dcdc(void); 45 1.3.2.2 yamt void enable_vbusvalid_comparator(void); 46 1.3.2.2 yamt void set_targets(void); 47 1.3.2.2 yamt void dcdc4p2_enable_dcdc(void); 48 1.3.2.2 yamt void p5vctrl_enable_dcdc(void); 49 1.3.2.2 yamt void enable_vddmem(void); 50 1.3.2.2 yamt 51 1.3.2.2 yamt /* 52 1.3.2.2 yamt * Power rail voltage targets, brownout levels and linear regulator 53 1.3.2.2 yamt * offsets from the target. 54 1.3.2.2 yamt * 55 1.3.2.2 yamt * Supply Target BO LinReg offset 56 1.3.2.2 yamt * ------------------------------------------ 57 1.3.2.2 yamt * VDDD 1.550 V 1.450 V -25 mV 58 1.3.2.2 yamt * VDDA 1.750 V 1.575 V -25 mV 59 1.3.2.2 yamt * VDDIO 3.100 V 2.925 V -25 mV 60 1.3.2.2 yamt * VDDMEM 2.500 V <na> <na> 61 1.3.2.2 yamt * 62 1.3.2.2 yamt * BO = Brownout level below target. 63 1.3.2.2 yamt */ 64 1.3.2.2 yamt #define VDDD_TARGET 0x1e 65 1.3.2.2 yamt #define VDDD_BO_OFFSET 0x4 66 1.3.2.2 yamt #define VDDD_LINREG_OFFSET 0x02 67 1.3.2.2 yamt 68 1.3.2.2 yamt #define VDDA_TARGET 0x0A 69 1.3.2.2 yamt #define VDDA_BO_OFFSET 0x07 70 1.3.2.2 yamt #define VDDA_LINREG_OFFSET 0x02 71 1.3.2.2 yamt 72 1.3.2.2 yamt #define VDDIO_TARGET 0x0C 73 1.3.2.2 yamt #define VDDIO_BO_OFFSET 0x07 74 1.3.2.2 yamt #define VDDIO_LINREG_OFFSET 0x02 75 1.3.2.2 yamt 76 1.3.2.2 yamt #define VDDMEM_TARGET 0x10 77 1.3.2.2 yamt 78 1.3.2.2 yamt /* 79 1.3.2.2 yamt * Threshold voltage for the VBUSVALID comparator. 80 1.3.2.2 yamt * Always make sure that the VDD5V voltage level is higher. 81 1.3.2.2 yamt */ 82 1.3.2.2 yamt #define VBUSVALID_TRSH 0x02 /* 4.1 V */ 83 1.3.2.2 yamt 84 1.3.2.2 yamt /* Limits for BATT charger + 4P2 current */ 85 1.3.2.2 yamt #define P4P2_ILIMIT_MIN 0x01 /* 10 mA */ 86 1.3.2.2 yamt #define P4P2_ILIMIT_MAX 0x3f /* 780 mA */ 87 1.3.2.2 yamt 88 1.3.2.2 yamt /* 89 1.3.2.2 yamt * Trip point for the comparison between the DCDC_4P2 and BATTERY pin. 90 1.3.2.2 yamt * If this voltage comparation is true then 5 V originated power will supply 91 1.3.2.2 yamt * the DCDC. Otherwise battery will be used. 92 1.3.2.2 yamt */ 93 1.3.2.2 yamt #define DCDC4P2_CMPTRIP 0x00 /* DCDC_4P2 pin > 0.85 * BATTERY pin */ 94 1.3.2.2 yamt 95 1.3.2.2 yamt /* 96 1.3.2.2 yamt * Adjust the behavior of the DCDC and 4.2 V circuit. 97 1.3.2.2 yamt * Two MSBs control the VDD4P2 brownout below the DCDC4P2_TRG before the 98 1.3.2.2 yamt * regulation circuit steals battery charge. Two LSBs control which power 99 1.3.2.2 yamt * source is selected by the DCDC. 100 1.3.2.2 yamt */ 101 1.3.2.2 yamt #define DCDC4P2_DROPOUT_CTRL_BO_200 0x0C 102 1.3.2.2 yamt #define DCDC4P2_DROPOUT_CTRL_BO_100 0x08 103 1.3.2.2 yamt #define DCDC4P2_DROPOUT_CTRL_BO_050 0x04 104 1.3.2.2 yamt #define DCDC4P2_DROPOUT_CTRL_BO_025 0x00 105 1.3.2.2 yamt 106 1.3.2.2 yamt #define DCDC4P2_DROPOUT_CTRL_SEL_4P2 0x00 /* Don't use battery at all. */ 107 1.3.2.2 yamt #define DCDC4P2_DROPOUT_CTRL_SEL_BATT_IF_GT_4P2 0x01 /* BATT if 4P2 < BATT */ 108 1.3.2.2 yamt #define DCDC4P2_DROPOUT_CTRL_SEL_HIGHER 0x02 /* Selects which ever is 109 1.3.2.2 yamt * higher. */ 110 1.3.2.2 yamt 111 1.3.2.2 yamt #define DCDC4P2_DROPOUT_CTRL (DCDC4P2_DROPOUT_CTRL_BO_200 |\ 112 1.3.2.2 yamt DCDC4P2_DROPOUT_CTRL_SEL_4P2) 113 1.3.2.2 yamt 114 1.3.2.2 yamt /* 115 1.3.2.2 yamt * Prepare system for a 5 V operation. 116 1.3.2.2 yamt * 117 1.3.2.2 yamt * The system uses inefficient linear regulators as a power source after boot. 118 1.3.2.2 yamt * This code enables the use of more energy efficient DC-DC converter as a 119 1.3.2.2 yamt * power source. 120 1.3.2.2 yamt */ 121 1.3.2.2 yamt int 122 1.3.2.2 yamt power_prep(void) 123 1.3.2.2 yamt { 124 1.3.2.2 yamt 125 1.3.2.2 yamt /* Enable clocks to the power block */ 126 1.3.2.2 yamt REG_WRITE(HW_POWER_BASE + HW_POWER_CTRL_CLR, HW_POWER_CTRL_CLKGATE); 127 1.3.2.2 yamt 128 1.3.2.2 yamt set_targets(); 129 1.3.2.2 yamt enable_vbusvalid_comparator(); 130 1.3.2.2 yamt enable_4p2_linreg(); 131 1.3.2.2 yamt charge_4p2_capacitance(); 132 1.3.2.2 yamt enable_dcdc(); 133 1.3.2.2 yamt enable_vddmem(); 134 1.3.2.2 yamt 135 1.3.2.2 yamt return 0; 136 1.3.2.2 yamt } 137 1.3.2.2 yamt 138 1.3.2.2 yamt /* 139 1.3.2.2 yamt * Set switching converter voltage targets, brownout levels and linear 140 1.3.2.2 yamt * regulator output offsets. 141 1.3.2.2 yamt */ 142 1.3.2.2 yamt void 143 1.3.2.2 yamt set_targets(void) 144 1.3.2.2 yamt { 145 1.3.2.2 yamt uint32_t vddctrl; 146 1.3.2.2 yamt 147 1.3.2.2 yamt /* VDDD */ 148 1.3.2.2 yamt vddctrl = REG_READ(HW_POWER_BASE + HW_POWER_VDDDCTRL); 149 1.3.2.2 yamt 150 1.3.2.2 yamt vddctrl &= ~(HW_POWER_VDDDCTRL_LINREG_OFFSET | 151 1.3.2.2 yamt HW_POWER_VDDDCTRL_BO_OFFSET | 152 1.3.2.2 yamt HW_POWER_VDDDCTRL_TRG); 153 1.3.2.2 yamt vddctrl |= 154 1.3.2.2 yamt __SHIFTIN(VDDD_LINREG_OFFSET, HW_POWER_VDDDCTRL_LINREG_OFFSET) | 155 1.3.2.2 yamt __SHIFTIN(VDDD_BO_OFFSET, HW_POWER_VDDDCTRL_BO_OFFSET) | 156 1.3.2.2 yamt __SHIFTIN(VDDD_TARGET, HW_POWER_VDDDCTRL_TRG); 157 1.3.2.2 yamt 158 1.3.2.2 yamt REG_WRITE(HW_POWER_BASE + HW_POWER_VDDDCTRL, vddctrl); 159 1.3.2.2 yamt 160 1.3.2.2 yamt /* VDDA */ 161 1.3.2.2 yamt vddctrl = REG_READ(HW_POWER_BASE + HW_POWER_VDDACTRL); 162 1.3.2.2 yamt 163 1.3.2.2 yamt vddctrl &= ~(HW_POWER_VDDACTRL_LINREG_OFFSET | 164 1.3.2.2 yamt HW_POWER_VDDACTRL_BO_OFFSET | 165 1.3.2.2 yamt HW_POWER_VDDACTRL_TRG); 166 1.3.2.2 yamt vddctrl |= 167 1.3.2.2 yamt __SHIFTIN(VDDA_LINREG_OFFSET, HW_POWER_VDDACTRL_LINREG_OFFSET) | 168 1.3.2.2 yamt __SHIFTIN(VDDA_BO_OFFSET, HW_POWER_VDDACTRL_BO_OFFSET) | 169 1.3.2.2 yamt __SHIFTIN(VDDA_TARGET, HW_POWER_VDDACTRL_TRG); 170 1.3.2.2 yamt 171 1.3.2.2 yamt REG_WRITE(HW_POWER_BASE + HW_POWER_VDDACTRL, vddctrl); 172 1.3.2.2 yamt 173 1.3.2.2 yamt /* VDDIO */ 174 1.3.2.2 yamt vddctrl = REG_READ(HW_POWER_BASE + HW_POWER_VDDIOCTRL); 175 1.3.2.2 yamt 176 1.3.2.2 yamt vddctrl &= ~(HW_POWER_VDDIOCTRL_LINREG_OFFSET | 177 1.3.2.2 yamt HW_POWER_VDDIOCTRL_BO_OFFSET | 178 1.3.2.2 yamt HW_POWER_VDDIOCTRL_TRG); 179 1.3.2.2 yamt vddctrl |= 180 1.3.2.2 yamt __SHIFTIN(VDDIO_LINREG_OFFSET, HW_POWER_VDDACTRL_LINREG_OFFSET) | 181 1.3.2.2 yamt __SHIFTIN(VDDIO_BO_OFFSET, HW_POWER_VDDACTRL_BO_OFFSET) | 182 1.3.2.2 yamt __SHIFTIN(VDDIO_TARGET, HW_POWER_VDDACTRL_TRG); 183 1.3.2.2 yamt 184 1.3.2.2 yamt REG_WRITE(HW_POWER_BASE + HW_POWER_VDDIOCTRL, vddctrl); 185 1.3.2.2 yamt 186 1.3.2.2 yamt /* VDDMEM */ 187 1.3.2.2 yamt vddctrl = REG_READ(HW_POWER_BASE + HW_POWER_VDDMEMCTRL); 188 1.3.2.2 yamt vddctrl &= ~(HW_POWER_VDDMEMCTRL_TRG); 189 1.3.2.2 yamt vddctrl |= __SHIFTIN(VDDMEM_TARGET, HW_POWER_VDDMEMCTRL_TRG); 190 1.3.2.2 yamt 191 1.3.2.2 yamt REG_WRITE(HW_POWER_BASE + HW_POWER_VDDMEMCTRL, vddctrl); 192 1.3.2.2 yamt 193 1.3.2.2 yamt return; 194 1.3.2.2 yamt } 195 1.3.2.2 yamt 196 1.3.2.2 yamt /* 197 1.3.2.2 yamt * VBUSVALID comparator is accurate method to determine the presence of 5 V. 198 1.3.2.2 yamt * Turn on the comparator, set its voltage treshold and instruct DC-DC to 199 1.3.2.2 yamt * use it. 200 1.3.2.2 yamt */ 201 1.3.2.2 yamt void 202 1.3.2.2 yamt enable_vbusvalid_comparator() 203 1.3.2.2 yamt { 204 1.3.2.2 yamt uint32_t p5vctrl; 205 1.3.2.2 yamt 206 1.3.2.2 yamt /* 207 1.3.2.2 yamt * Disable 5 V brownout detection temporarily because setting 208 1.3.2.2 yamt * VBUSVALID_5VDETECT can cause false brownout. 209 1.3.2.2 yamt */ 210 1.3.2.2 yamt REG_WRITE(HW_POWER_BASE + HW_POWER_5VCTRL_CLR, 211 1.3.2.2 yamt HW_POWER_5VCTRL_PWDN_5VBRNOUT); 212 1.3.2.2 yamt 213 1.3.2.2 yamt p5vctrl = REG_READ(HW_POWER_BASE + HW_POWER_5VCTRL); 214 1.3.2.2 yamt 215 1.3.2.2 yamt p5vctrl &= ~HW_POWER_5VCTRL_VBUSVALID_TRSH; 216 1.3.2.2 yamt p5vctrl |= 217 1.3.2.2 yamt /* Turn on VBUS comparators. */ 218 1.3.2.2 yamt (HW_POWER_5VCTRL_PWRUP_VBUS_CMPS | 219 1.3.2.2 yamt /* Set treshold for VBUSVALID comparator. */ 220 1.3.2.2 yamt __SHIFTIN(VBUSVALID_TRSH, HW_POWER_5VCTRL_VBUSVALID_TRSH) | 221 1.3.2.2 yamt /* Set DC-DC to use VBUSVALID comparator. */ 222 1.3.2.2 yamt HW_POWER_5VCTRL_VBUSVALID_5VDETECT); 223 1.3.2.2 yamt 224 1.3.2.2 yamt REG_WRITE(HW_POWER_BASE + HW_POWER_5VCTRL, p5vctrl); 225 1.3.2.2 yamt 226 1.3.2.2 yamt /* Enable temporarily disabled 5 V brownout detection. */ 227 1.3.2.2 yamt REG_WRITE(HW_POWER_BASE + HW_POWER_5VCTRL_SET, 228 1.3.2.2 yamt HW_POWER_5VCTRL_PWDN_5VBRNOUT); 229 1.3.2.2 yamt 230 1.3.2.2 yamt return; 231 1.3.2.2 yamt } 232 1.3.2.2 yamt 233 1.3.2.2 yamt /* 234 1.3.2.2 yamt * Enable 4P2 linear regulator. 235 1.3.2.2 yamt */ 236 1.3.2.2 yamt void 237 1.3.2.2 yamt enable_4p2_linreg(void) 238 1.3.2.2 yamt { 239 1.3.2.2 yamt uint32_t dcdc4p2; 240 1.3.2.2 yamt uint32_t p5vctrl; 241 1.3.2.2 yamt 242 1.3.2.2 yamt dcdc4p2 = REG_READ(HW_POWER_BASE + HW_POWER_DCDC4P2); 243 1.3.2.2 yamt /* Set the 4P2 target to 4.2 V and BO to 3.6V by clearing TRG and BO 244 1.3.2.2 yamt * field. */ 245 1.3.2.2 yamt dcdc4p2 &= ~(HW_POWER_DCDC4P2_TRG | HW_POWER_DCDC4P2_BO); 246 1.3.2.2 yamt /* Enable the 4P2 circuitry to control the LinReg. */ 247 1.3.2.2 yamt dcdc4p2 |= HW_POWER_DCDC4P2_ENABLE_4P2; 248 1.3.2.2 yamt REG_WRITE(HW_POWER_BASE + HW_POWER_DCDC4P2, dcdc4p2); 249 1.3.2.2 yamt 250 1.3.2.2 yamt /* The 4P2 LinReg needs a static load to operate correctly. Since the 251 1.3.2.2 yamt * DC-DC is not yet loading the LinReg, another load must be used. */ 252 1.3.2.2 yamt REG_WRITE(HW_POWER_BASE + HW_POWER_CHARGE_SET, 253 1.3.2.2 yamt HW_POWER_CHARGE_ENABLE_LOAD); 254 1.3.2.2 yamt 255 1.3.2.2 yamt p5vctrl = REG_READ(HW_POWER_BASE + HW_POWER_5VCTRL); 256 1.3.2.2 yamt p5vctrl &= ~(HW_POWER_5VCTRL_CHARGE_4P2_ILIMIT | 257 1.3.2.2 yamt /* Power on the 4P2 LinReg. ON = 0x0, OFF = 0x1 */ 258 1.3.2.2 yamt HW_POWER_5VCTRL_PWD_CHARGE_4P2); 259 1.3.2.2 yamt p5vctrl |= 260 1.3.2.2 yamt /* Provide an initial current limit for the 4P2 LinReg with the 261 1.3.2.2 yamt * smallest value possible. */ 262 1.3.2.2 yamt __SHIFTIN(P4P2_ILIMIT_MIN, HW_POWER_5VCTRL_CHARGE_4P2_ILIMIT); 263 1.3.2.2 yamt REG_WRITE(HW_POWER_BASE + HW_POWER_5VCTRL, p5vctrl); 264 1.3.2.2 yamt 265 1.3.2.2 yamt /* Ungate the path from 4P2 LinReg to DC-DC. */ 266 1.3.2.2 yamt dcdc4p2_enable_dcdc(); 267 1.3.2.2 yamt 268 1.3.2.2 yamt return; 269 1.3.2.2 yamt } 270 1.3.2.2 yamt 271 1.3.2.2 yamt /* 272 1.3.2.2 yamt * There is capacitor on the 4P2 output which must be charged before powering 273 1.3.2.2 yamt * on the 4P2 linear regulator to avoid brownouts on the 5 V source. 274 1.3.2.2 yamt * Charging is done by slowly increasing current limit until it reaches 275 1.3.2.2 yamt * P4P2_ILIMIT_MAX. 276 1.3.2.2 yamt */ 277 1.3.2.2 yamt void 278 1.3.2.2 yamt charge_4p2_capacitance(void) 279 1.3.2.2 yamt { 280 1.3.2.2 yamt uint32_t ilimit; 281 1.3.2.2 yamt uint32_t p5vctrl; 282 1.3.2.2 yamt 283 1.3.2.2 yamt p5vctrl = REG_READ(HW_POWER_BASE + HW_POWER_5VCTRL); 284 1.3.2.2 yamt ilimit = __SHIFTOUT(p5vctrl, HW_POWER_5VCTRL_CHARGE_4P2_ILIMIT); 285 1.3.2.2 yamt 286 1.3.2.2 yamt /* Increment current limit slowly. */ 287 1.3.2.2 yamt while (ilimit < P4P2_ILIMIT_MAX) { 288 1.3.2.2 yamt ilimit++; 289 1.3.2.2 yamt p5vctrl &= ~(HW_POWER_5VCTRL_CHARGE_4P2_ILIMIT); 290 1.3.2.2 yamt p5vctrl |= __SHIFTIN(ilimit, HW_POWER_5VCTRL_CHARGE_4P2_ILIMIT); 291 1.3.2.2 yamt REG_WRITE(HW_POWER_BASE + HW_POWER_5VCTRL, p5vctrl); 292 1.3.2.2 yamt delay_us(10000); 293 1.3.2.2 yamt } 294 1.3.2.2 yamt 295 1.3.2.2 yamt return; 296 1.3.2.2 yamt } 297 1.3.2.2 yamt 298 1.3.2.2 yamt /* 299 1.3.2.2 yamt * Enable DCDC to use 4P2 regulator and set its power source selection logic. 300 1.3.2.2 yamt */ 301 1.3.2.2 yamt void 302 1.3.2.2 yamt enable_dcdc(void) 303 1.3.2.2 yamt { 304 1.3.2.2 yamt uint32_t dcdc4p2; 305 1.3.2.2 yamt uint32_t vddctrl; 306 1.3.2.2 yamt 307 1.3.2.2 yamt dcdc4p2 = REG_READ(HW_POWER_BASE + HW_POWER_DCDC4P2); 308 1.3.2.2 yamt dcdc4p2 &= ~(HW_POWER_DCDC4P2_CMPTRIP | HW_POWER_DCDC4P2_DROPOUT_CTRL); 309 1.3.2.2 yamt /* Comparison between the DCDC_4P2 pin and BATTERY pin to choose which 310 1.3.2.2 yamt * will supply the DCDC. */ 311 1.3.2.2 yamt dcdc4p2 |= __SHIFTIN(DCDC4P2_CMPTRIP, HW_POWER_DCDC4P2_CMPTRIP); 312 1.3.2.2 yamt /* DC-DC brownout and select logic. */ 313 1.3.2.2 yamt dcdc4p2 |= __SHIFTIN(DCDC4P2_DROPOUT_CTRL, 314 1.3.2.2 yamt HW_POWER_DCDC4P2_DROPOUT_CTRL); 315 1.3.2.2 yamt REG_WRITE(HW_POWER_BASE + HW_POWER_DCDC4P2, dcdc4p2); 316 1.3.2.2 yamt 317 1.3.2.2 yamt /* Disable the automatic DC-DC startup when 5 V is lost (it is on 318 1.3.2.2 yamt * already) */ 319 1.3.2.2 yamt REG_WRITE(HW_POWER_BASE + HW_POWER_5VCTRL_CLR, 320 1.3.2.2 yamt HW_POWER_5VCTRL_DCDC_XFER); 321 1.3.2.2 yamt 322 1.3.2.2 yamt p5vctrl_enable_dcdc(); 323 1.3.2.2 yamt 324 1.3.2.2 yamt /* Enable switching converter outputs and disable linear regulators 325 1.3.2.2 yamt * for VDDD, VDDIO and VDDA. */ 326 1.3.2.2 yamt vddctrl = REG_READ(HW_POWER_BASE + HW_POWER_VDDDCTRL); 327 1.3.2.2 yamt vddctrl &= ~(HW_POWER_VDDDCTRL_DISABLE_FET | 328 1.3.2.2 yamt HW_POWER_VDDDCTRL_ENABLE_LINREG); 329 1.3.2.2 yamt REG_WRITE(HW_POWER_BASE + HW_POWER_VDDDCTRL, vddctrl); 330 1.3.2.2 yamt 331 1.3.2.2 yamt vddctrl = REG_READ(HW_POWER_BASE + HW_POWER_VDDIOCTRL); 332 1.3.2.2 yamt vddctrl &= ~HW_POWER_VDDIOCTRL_DISABLE_FET; 333 1.3.2.2 yamt REG_WRITE(HW_POWER_BASE + HW_POWER_VDDIOCTRL, vddctrl); 334 1.3.2.2 yamt 335 1.3.2.2 yamt vddctrl = REG_READ(HW_POWER_BASE + HW_POWER_VDDACTRL); 336 1.3.2.2 yamt vddctrl &= ~(HW_POWER_VDDACTRL_DISABLE_FET | 337 1.3.2.2 yamt HW_POWER_VDDACTRL_ENABLE_LINREG); 338 1.3.2.2 yamt REG_WRITE(HW_POWER_BASE + HW_POWER_VDDACTRL, vddctrl); 339 1.3.2.2 yamt 340 1.3.2.2 yamt /* The 4P2 LinReg needs a static load to operate correctly. Since the 341 1.3.2.2 yamt * DC-DC is already running we can remove extra 100 ohm load enabled 342 1.3.2.2 yamt * before. */ 343 1.3.2.2 yamt REG_WRITE(HW_POWER_BASE + HW_POWER_CHARGE_CLR, 344 1.3.2.2 yamt HW_POWER_CHARGE_ENABLE_LOAD); 345 1.3.2.2 yamt 346 1.3.2.2 yamt return; 347 1.3.2.2 yamt } 348 1.3.2.2 yamt 349 1.3.2.2 yamt /* 350 1.3.2.2 yamt * DCDC4P2 DCDC enable sequence according to errata #5837 351 1.3.2.2 yamt */ 352 1.3.2.2 yamt void 353 1.3.2.2 yamt dcdc4p2_enable_dcdc(void) 354 1.3.2.2 yamt { 355 1.3.2.2 yamt uint32_t dcdc4p2; 356 1.3.2.2 yamt uint32_t p5vctrl; 357 1.3.2.2 yamt uint32_t p5vctrl_saved; 358 1.3.2.2 yamt uint32_t pctrl; 359 1.3.2.2 yamt uint32_t pctrl_saved; 360 1.3.2.2 yamt 361 1.3.2.2 yamt pctrl_saved = REG_READ(HW_POWER_BASE + HW_POWER_CTRL); 362 1.3.2.2 yamt p5vctrl_saved = REG_READ(HW_POWER_BASE + HW_POWER_5VCTRL); 363 1.3.2.2 yamt 364 1.3.2.2 yamt /* Disable the power rail brownout interrupts. */ 365 1.3.2.2 yamt REG_WRITE(HW_POWER_BASE + HW_POWER_CTRL_CLR, 366 1.3.2.2 yamt (HW_POWER_CTRL_ENIRQ_VDDA_BO | 367 1.3.2.2 yamt HW_POWER_CTRL_ENIRQ_VDDD_BO | 368 1.3.2.2 yamt HW_POWER_CTRL_ENIRQ_VDDIO_BO)); 369 1.3.2.2 yamt 370 1.3.2.2 yamt /* Set the HW_POWER_5VCTRL PWRUP_VBUS_CMPS bit (may already be set) */ 371 1.3.2.2 yamt REG_WRITE(HW_POWER_BASE + HW_POWER_5VCTRL_SET, 372 1.3.2.2 yamt HW_POWER_5VCTRL_PWRUP_VBUS_CMPS); 373 1.3.2.2 yamt 374 1.3.2.2 yamt /* Set the HW_POWER_5VCTRL VBUSVALID_5VDETECT bit to 0 */ 375 1.3.2.2 yamt REG_WRITE(HW_POWER_BASE + HW_POWER_5VCTRL_CLR, 376 1.3.2.2 yamt HW_POWER_5VCTRL_VBUSVALID_5VDETECT); 377 1.3.2.2 yamt 378 1.3.2.2 yamt /* Set the HW_POWER_5VCTRL VBUSVALID_TRSH to 0x0 (2.9 V) */ 379 1.3.2.2 yamt REG_WRITE(HW_POWER_BASE + HW_POWER_5VCTRL_CLR, 380 1.3.2.2 yamt HW_POWER_5VCTRL_VBUSVALID_TRSH); 381 1.3.2.2 yamt 382 1.3.2.2 yamt /* Disable VBUSDROOP status and interrupt. */ 383 1.3.2.2 yamt REG_WRITE(HW_POWER_BASE + HW_POWER_CTRL_CLR, 384 1.3.2.2 yamt (HW_POWER_CTRL_VDD5V_DROOP_IRQ | HW_POWER_CTRL_ENIRQ_VDD5V_DROOP)); 385 1.3.2.2 yamt 386 1.3.2.2 yamt /* Set the ENABLE_DCDC bit in HW_POWER_DCDC4P2. */ 387 1.3.2.2 yamt dcdc4p2 = REG_READ(HW_POWER_BASE + HW_POWER_DCDC4P2); 388 1.3.2.2 yamt dcdc4p2 |= HW_POWER_DCDC4P2_ENABLE_DCDC; 389 1.3.2.2 yamt REG_WRITE(HW_POWER_BASE + HW_POWER_DCDC4P2, dcdc4p2); 390 1.3.2.2 yamt 391 1.3.2.2 yamt delay_us(100); 392 1.3.2.2 yamt 393 1.3.2.2 yamt pctrl = REG_READ(HW_POWER_BASE + HW_POWER_CTRL); 394 1.3.2.2 yamt /* VBUSVALID_IRQ is set. */ 395 1.3.2.2 yamt if (__SHIFTOUT(pctrl, HW_POWER_CTRL_VBUSVALID_IRQ)) { 396 1.3.2.2 yamt /* Set and clear the PWD_CHARGE_4P2 bit to repower on the 4P2 397 1.3.2.2 yamt * regulator because it is automatically shut off on a 398 1.3.2.2 yamt * VBUSVALID false condition. */ 399 1.3.2.2 yamt REG_WRITE(HW_POWER_BASE + HW_POWER_5VCTRL_SET, 400 1.3.2.2 yamt HW_POWER_5VCTRL_PWD_CHARGE_4P2); 401 1.3.2.2 yamt REG_WRITE(HW_POWER_BASE + HW_POWER_5VCTRL_CLR, 402 1.3.2.2 yamt HW_POWER_5VCTRL_PWD_CHARGE_4P2); 403 1.3.2.2 yamt /* Ramp up the CHARGE_4P2_ILIMIT value at this point. */ 404 1.3.2.2 yamt charge_4p2_capacitance(); 405 1.3.2.2 yamt } 406 1.3.2.2 yamt 407 1.3.2.2 yamt /* Restore modified bits back to HW_POWER_CTRL. */ 408 1.3.2.2 yamt if (pctrl_saved & HW_POWER_CTRL_ENIRQ_VDDA_BO) 409 1.3.2.2 yamt REG_WRITE(HW_POWER_BASE + HW_POWER_CTRL_SET, 410 1.3.2.2 yamt HW_POWER_CTRL_ENIRQ_VDDA_BO); 411 1.3.2.2 yamt else 412 1.3.2.2 yamt REG_WRITE(HW_POWER_BASE + HW_POWER_CTRL_CLR, 413 1.3.2.2 yamt HW_POWER_CTRL_ENIRQ_VDDA_BO); 414 1.3.2.2 yamt 415 1.3.2.2 yamt if (pctrl_saved & HW_POWER_CTRL_ENIRQ_VDDD_BO) 416 1.3.2.2 yamt REG_WRITE(HW_POWER_BASE + HW_POWER_CTRL_SET, 417 1.3.2.2 yamt HW_POWER_CTRL_ENIRQ_VDDD_BO); 418 1.3.2.2 yamt else 419 1.3.2.2 yamt REG_WRITE(HW_POWER_BASE + HW_POWER_CTRL_CLR, 420 1.3.2.2 yamt HW_POWER_CTRL_ENIRQ_VDDD_BO); 421 1.3.2.2 yamt 422 1.3.2.2 yamt if (pctrl_saved & HW_POWER_CTRL_ENIRQ_VDDIO_BO) 423 1.3.2.2 yamt REG_WRITE(HW_POWER_BASE + HW_POWER_CTRL_SET, 424 1.3.2.2 yamt HW_POWER_CTRL_ENIRQ_VDDIO_BO); 425 1.3.2.2 yamt else 426 1.3.2.2 yamt REG_WRITE(HW_POWER_BASE + HW_POWER_CTRL_CLR, 427 1.3.2.2 yamt HW_POWER_CTRL_ENIRQ_VDDIO_BO); 428 1.3.2.2 yamt 429 1.3.2.2 yamt if (pctrl_saved & HW_POWER_CTRL_VDD5V_DROOP_IRQ) 430 1.3.2.2 yamt REG_WRITE(HW_POWER_BASE + HW_POWER_CTRL_SET, 431 1.3.2.2 yamt HW_POWER_CTRL_VDD5V_DROOP_IRQ); 432 1.3.2.2 yamt else 433 1.3.2.2 yamt REG_WRITE(HW_POWER_BASE + HW_POWER_CTRL_CLR, 434 1.3.2.2 yamt HW_POWER_CTRL_VDD5V_DROOP_IRQ); 435 1.3.2.2 yamt 436 1.3.2.2 yamt if (pctrl_saved & HW_POWER_CTRL_ENIRQ_VDD5V_DROOP) 437 1.3.2.2 yamt REG_WRITE(HW_POWER_BASE + HW_POWER_CTRL_SET, 438 1.3.2.2 yamt HW_POWER_CTRL_ENIRQ_VDD5V_DROOP); 439 1.3.2.2 yamt else 440 1.3.2.2 yamt REG_WRITE(HW_POWER_BASE + HW_POWER_CTRL_CLR, 441 1.3.2.2 yamt HW_POWER_CTRL_ENIRQ_VDD5V_DROOP); 442 1.3.2.2 yamt 443 1.3.2.2 yamt /* Restore modified bits back to HW_POWER_5VCTRL. */ 444 1.3.2.2 yamt p5vctrl = REG_READ(HW_POWER_BASE + HW_POWER_5VCTRL); 445 1.3.2.2 yamt p5vctrl &= ~(HW_POWER_5VCTRL_PWRUP_VBUS_CMPS | 446 1.3.2.2 yamt HW_POWER_5VCTRL_VBUSVALID_5VDETECT | 447 1.3.2.2 yamt HW_POWER_5VCTRL_VBUSVALID_TRSH); 448 1.3.2.2 yamt p5vctrl |= __SHIFTOUT(p5vctrl_saved, HW_POWER_5VCTRL_VBUSVALID_TRSH) | 449 1.3.2.2 yamt (p5vctrl_saved & HW_POWER_5VCTRL_PWRUP_VBUS_CMPS) | 450 1.3.2.2 yamt (p5vctrl_saved & HW_POWER_5VCTRL_VBUSVALID_5VDETECT); 451 1.3.2.2 yamt REG_WRITE(HW_POWER_BASE + HW_POWER_5VCTRL, p5vctrl); 452 1.3.2.2 yamt 453 1.3.2.2 yamt return; 454 1.3.2.2 yamt } 455 1.3.2.2 yamt 456 1.3.2.2 yamt /* 457 1.3.2.2 yamt * 5VCTRL DCDC enable sequence according to errata #5837 458 1.3.2.2 yamt */ 459 1.3.2.2 yamt void 460 1.3.2.2 yamt p5vctrl_enable_dcdc(void) 461 1.3.2.2 yamt { 462 1.3.2.2 yamt uint32_t p5vctrl; 463 1.3.2.2 yamt uint32_t p5vctrl_saved; 464 1.3.2.2 yamt uint32_t pctrl; 465 1.3.2.2 yamt uint32_t pctrl_saved; 466 1.3.2.2 yamt 467 1.3.2.2 yamt pctrl_saved = REG_READ(HW_POWER_BASE + HW_POWER_CTRL); 468 1.3.2.2 yamt p5vctrl_saved = REG_READ(HW_POWER_BASE + HW_POWER_5VCTRL); 469 1.3.2.2 yamt 470 1.3.2.2 yamt /* Disable the power rail brownout interrupts. */ 471 1.3.2.2 yamt REG_WRITE(HW_POWER_BASE + HW_POWER_CTRL_CLR, 472 1.3.2.2 yamt HW_POWER_CTRL_ENIRQ_VDDA_BO | 473 1.3.2.2 yamt HW_POWER_CTRL_ENIRQ_VDDD_BO | 474 1.3.2.2 yamt HW_POWER_CTRL_ENIRQ_VDDIO_BO); 475 1.3.2.2 yamt 476 1.3.2.2 yamt /* Set the HW_POWER_5VCTRL PWRUP_VBUS_CMPS bit (may already be set) */ 477 1.3.2.2 yamt REG_WRITE(HW_POWER_BASE + HW_POWER_5VCTRL_SET, 478 1.3.2.2 yamt HW_POWER_5VCTRL_PWRUP_VBUS_CMPS); 479 1.3.2.2 yamt 480 1.3.2.2 yamt /* Set the HW_POWER_5VCTRL VBUSVALID_5VDETECT bit to 1 */ 481 1.3.2.2 yamt REG_WRITE(HW_POWER_BASE + HW_POWER_5VCTRL_SET, 482 1.3.2.2 yamt HW_POWER_5VCTRL_VBUSVALID_5VDETECT); 483 1.3.2.2 yamt 484 1.3.2.2 yamt /* Set the HW_POWER_5VCTRL VBUSVALID_TRSH to 0x0 (2.9 V) */ 485 1.3.2.2 yamt REG_WRITE(HW_POWER_BASE + HW_POWER_5VCTRL_CLR, 486 1.3.2.2 yamt HW_POWER_5VCTRL_VBUSVALID_TRSH); 487 1.3.2.2 yamt 488 1.3.2.2 yamt /* Disable VBUSDROOP status and interrupt. */ 489 1.3.2.2 yamt REG_WRITE(HW_POWER_BASE + HW_POWER_CTRL_CLR, 490 1.3.2.2 yamt (HW_POWER_CTRL_VDD5V_DROOP_IRQ | HW_POWER_CTRL_ENIRQ_VDD5V_DROOP)); 491 1.3.2.2 yamt 492 1.3.2.2 yamt /* Work over errata #2816 by disabling 5 V brownout while modifying 493 1.3.2.2 yamt * ENABLE_DCDC. */ 494 1.3.2.2 yamt REG_WRITE(HW_POWER_BASE + HW_POWER_5VCTRL_CLR, 495 1.3.2.2 yamt HW_POWER_5VCTRL_PWDN_5VBRNOUT); 496 1.3.2.2 yamt 497 1.3.2.2 yamt /* Set the ENABLE_DCDC bit in HW_POWER_5VCTRL. */ 498 1.3.2.2 yamt REG_WRITE(HW_POWER_BASE + HW_POWER_5VCTRL_SET, 499 1.3.2.2 yamt HW_POWER_5VCTRL_ENABLE_DCDC); 500 1.3.2.2 yamt 501 1.3.2.2 yamt REG_WRITE(HW_POWER_BASE + HW_POWER_5VCTRL_SET, 502 1.3.2.2 yamt HW_POWER_5VCTRL_PWDN_5VBRNOUT); 503 1.3.2.2 yamt 504 1.3.2.2 yamt delay_us(100); 505 1.3.2.2 yamt 506 1.3.2.2 yamt pctrl = REG_READ(HW_POWER_BASE + HW_POWER_CTRL); 507 1.3.2.2 yamt /* VBUSVALID_IRQ is set. */ 508 1.3.2.2 yamt if (__SHIFTOUT(pctrl, HW_POWER_CTRL_VBUSVALID_IRQ)) { 509 1.3.2.2 yamt /* repeat the sequence for enabling the 4P2 regulator and DCDC 510 1.3.2.2 yamt * from 4P2. */ 511 1.3.2.2 yamt enable_4p2_linreg(); 512 1.3.2.2 yamt } 513 1.3.2.2 yamt /* Restore modified bits back to HW_POWER_CTRL. */ 514 1.3.2.2 yamt if (pctrl_saved & HW_POWER_CTRL_ENIRQ_VDDA_BO) 515 1.3.2.2 yamt REG_WRITE(HW_POWER_BASE + HW_POWER_CTRL_SET, 516 1.3.2.2 yamt HW_POWER_CTRL_ENIRQ_VDDA_BO); 517 1.3.2.2 yamt else 518 1.3.2.2 yamt REG_WRITE(HW_POWER_BASE + HW_POWER_CTRL_CLR, 519 1.3.2.2 yamt HW_POWER_CTRL_ENIRQ_VDDA_BO); 520 1.3.2.2 yamt 521 1.3.2.2 yamt if (pctrl_saved & HW_POWER_CTRL_ENIRQ_VDDD_BO) 522 1.3.2.2 yamt REG_WRITE(HW_POWER_BASE + HW_POWER_CTRL_SET, 523 1.3.2.2 yamt HW_POWER_CTRL_ENIRQ_VDDD_BO); 524 1.3.2.2 yamt else 525 1.3.2.2 yamt REG_WRITE(HW_POWER_BASE + HW_POWER_CTRL_CLR, 526 1.3.2.2 yamt HW_POWER_CTRL_ENIRQ_VDDD_BO); 527 1.3.2.2 yamt 528 1.3.2.2 yamt if (pctrl_saved & HW_POWER_CTRL_ENIRQ_VDDIO_BO) 529 1.3.2.2 yamt REG_WRITE(HW_POWER_BASE + HW_POWER_CTRL_SET, 530 1.3.2.2 yamt HW_POWER_CTRL_ENIRQ_VDDIO_BO); 531 1.3.2.2 yamt else 532 1.3.2.2 yamt REG_WRITE(HW_POWER_BASE + HW_POWER_CTRL_CLR, 533 1.3.2.2 yamt HW_POWER_CTRL_ENIRQ_VDDIO_BO); 534 1.3.2.2 yamt 535 1.3.2.2 yamt if (pctrl_saved & HW_POWER_CTRL_VDD5V_DROOP_IRQ) 536 1.3.2.2 yamt REG_WRITE(HW_POWER_BASE + HW_POWER_CTRL_SET, 537 1.3.2.2 yamt HW_POWER_CTRL_VDD5V_DROOP_IRQ); 538 1.3.2.2 yamt else 539 1.3.2.2 yamt REG_WRITE(HW_POWER_BASE + HW_POWER_CTRL_CLR, 540 1.3.2.2 yamt HW_POWER_CTRL_VDD5V_DROOP_IRQ); 541 1.3.2.2 yamt 542 1.3.2.2 yamt if (pctrl_saved & HW_POWER_CTRL_ENIRQ_VDD5V_DROOP) 543 1.3.2.2 yamt REG_WRITE(HW_POWER_BASE + HW_POWER_CTRL_SET, 544 1.3.2.2 yamt HW_POWER_CTRL_ENIRQ_VDD5V_DROOP); 545 1.3.2.2 yamt else 546 1.3.2.2 yamt REG_WRITE(HW_POWER_BASE + HW_POWER_CTRL_CLR, 547 1.3.2.2 yamt HW_POWER_CTRL_ENIRQ_VDD5V_DROOP); 548 1.3.2.2 yamt 549 1.3.2.2 yamt /* Restore modified bits back to HW_POWER_5VCTRL. */ 550 1.3.2.2 yamt p5vctrl = REG_READ(HW_POWER_BASE + HW_POWER_5VCTRL); 551 1.3.2.2 yamt p5vctrl &= ~(HW_POWER_5VCTRL_PWRUP_VBUS_CMPS | 552 1.3.2.2 yamt HW_POWER_5VCTRL_VBUSVALID_5VDETECT | 553 1.3.2.2 yamt HW_POWER_5VCTRL_VBUSVALID_TRSH); 554 1.3.2.2 yamt p5vctrl |= __SHIFTOUT(p5vctrl_saved, HW_POWER_5VCTRL_VBUSVALID_TRSH) | 555 1.3.2.2 yamt (p5vctrl_saved & HW_POWER_5VCTRL_PWRUP_VBUS_CMPS) | 556 1.3.2.2 yamt (p5vctrl_saved & HW_POWER_5VCTRL_VBUSVALID_5VDETECT); 557 1.3.2.2 yamt REG_WRITE(HW_POWER_BASE + HW_POWER_5VCTRL, p5vctrl); 558 1.3.2.2 yamt 559 1.3.2.2 yamt return; 560 1.3.2.2 yamt } 561 1.3.2.2 yamt 562 1.3.2.2 yamt void 563 1.3.2.2 yamt enable_vddmem(void) 564 1.3.2.2 yamt { 565 1.3.2.2 yamt uint32_t vddctrl; 566 1.3.2.2 yamt 567 1.3.2.2 yamt /* VDDMEM */ 568 1.3.2.2 yamt vddctrl = REG_READ(HW_POWER_BASE + HW_POWER_VDDMEMCTRL); 569 1.3.2.2 yamt vddctrl |= (HW_POWER_VDDMEMCTRL_PULLDOWN_ACTIVE | 570 1.3.2.2 yamt HW_POWER_VDDMEMCTRL_ENABLE_ILIMIT | 571 1.3.2.2 yamt HW_POWER_VDDMEMCTRL_ENABLE_LINREG); 572 1.3.2.2 yamt REG_WRITE(HW_POWER_BASE + HW_POWER_VDDMEMCTRL, vddctrl); 573 1.3.2.2 yamt delay_us(500); 574 1.3.2.2 yamt vddctrl &= ~(HW_POWER_VDDMEMCTRL_PULLDOWN_ACTIVE | 575 1.3.2.2 yamt HW_POWER_VDDMEMCTRL_ENABLE_ILIMIT); 576 1.3.2.2 yamt REG_WRITE(HW_POWER_BASE + HW_POWER_VDDMEMCTRL, vddctrl); 577 1.3.2.2 yamt delay_us(10000); 578 1.3.2.2 yamt 579 1.3.2.2 yamt return; 580 1.3.2.2 yamt } 581
Indexes created Wed Oct 15 07:09:58 GMT 2025