isa_machdep.c revision 1.1 1 1.1 joff /* $NetBSD: isa_machdep.c,v 1.1 2004/12/23 04:31:48 joff Exp $ */
2 1.1 joff
3 1.1 joff /*-
4 1.1 joff * Copyright (c) 1996-1998 The NetBSD Foundation, Inc.
5 1.1 joff * All rights reserved.
6 1.1 joff *
7 1.1 joff * This code is derived from software contributed to The NetBSD Foundation
8 1.1 joff * by Jesse Off
9 1.1 joff *
10 1.1 joff * This code is derived from software contributed to The NetBSD Foundation
11 1.1 joff * by Mark Brinicombe, Charles M. Hannum and by Jason R. Thorpe of the
12 1.1 joff * Numerical Aerospace Simulation Facility, NASA Ames Research Center.
13 1.1 joff *
14 1.1 joff * Redistribution and use in source and binary forms, with or without
15 1.1 joff * modification, are permitted provided that the following conditions
16 1.1 joff * are met:
17 1.1 joff * 1. Redistributions of source code must retain the above copyright
18 1.1 joff * notice, this list of conditions and the following disclaimer.
19 1.1 joff * 2. Redistributions in binary form must reproduce the above copyright
20 1.1 joff * notice, this list of conditions and the following disclaimer in the
21 1.1 joff * documentation and/or other materials provided with the distribution.
22 1.1 joff * 3. All advertising materials mentioning features or use of this software
23 1.1 joff * must display the following acknowledgement:
24 1.1 joff * This product includes software developed by the NetBSD
25 1.1 joff * Foundation, Inc. and its contributors.
26 1.1 joff * 4. Neither the name of The NetBSD Foundation nor the names of its
27 1.1 joff * contributors may be used to endorse or promote products derived
28 1.1 joff * from this software without specific prior written permission.
29 1.1 joff *
30 1.1 joff * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
31 1.1 joff * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
32 1.1 joff * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
33 1.1 joff * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
34 1.1 joff * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
35 1.1 joff * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
36 1.1 joff * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
37 1.1 joff * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
38 1.1 joff * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
39 1.1 joff * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
40 1.1 joff * POSSIBILITY OF SUCH DAMAGE.
41 1.1 joff */
42 1.1 joff
43 1.1 joff /*-
44 1.1 joff * Copyright (c) 1991 The Regents of the University of California.
45 1.1 joff * All rights reserved.
46 1.1 joff *
47 1.1 joff * This code is derived from software contributed to Berkeley by
48 1.1 joff * William Jolitz.
49 1.1 joff *
50 1.1 joff * Redistribution and use in source and binary forms, with or without
51 1.1 joff * modification, are permitted provided that the following conditions
52 1.1 joff * are met:
53 1.1 joff * 1. Redistributions of source code must retain the above copyright
54 1.1 joff * notice, this list of conditions and the following disclaimer.
55 1.1 joff * 2. Redistributions in binary form must reproduce the above copyright
56 1.1 joff * notice, this list of conditions and the following disclaimer in the
57 1.1 joff * documentation and/or other materials provided with the distribution.
58 1.1 joff * 3. Neither the name of the University nor the names of its contributors
59 1.1 joff * may be used to endorse or promote products derived from this software
60 1.1 joff * without specific prior written permission.
61 1.1 joff *
62 1.1 joff * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
63 1.1 joff * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
64 1.1 joff * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
65 1.1 joff * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
66 1.1 joff * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
67 1.1 joff * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
68 1.1 joff * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
69 1.1 joff * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
70 1.1 joff * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
71 1.1 joff * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
72 1.1 joff * SUCH DAMAGE.
73 1.1 joff *
74 1.1 joff * @(#)isa.c 7.2 (Berkeley) 5/13/91
75 1.1 joff */
76 1.1 joff
77 1.1 joff #include <sys/cdefs.h>
78 1.1 joff __KERNEL_RCSID(0, "$NetBSD: isa_machdep.c,v 1.1 2004/12/23 04:31:48 joff Exp $");
79 1.1 joff
80 1.1 joff #include "opt_irqstats.h"
81 1.1 joff
82 1.1 joff #include <sys/param.h>
83 1.1 joff #include <sys/systm.h>
84 1.1 joff #include <sys/kernel.h>
85 1.1 joff #include <sys/syslog.h>
86 1.1 joff #include <sys/device.h>
87 1.1 joff #include <sys/malloc.h>
88 1.1 joff #include <sys/proc.h>
89 1.1 joff
90 1.1 joff #include <machine/bus.h>
91 1.1 joff
92 1.1 joff #include <machine/intr.h>
93 1.1 joff #include <machine/pio.h>
94 1.1 joff #include <machine/bootconfig.h>
95 1.1 joff #include <machine/isa_machdep.h>
96 1.1 joff
97 1.1 joff #include <dev/isa/isareg.h>
98 1.1 joff #include <dev/isa/isavar.h>
99 1.1 joff
100 1.1 joff #include <arm/ep93xx/ep93xxvar.h>
101 1.1 joff #include <uvm/uvm_extern.h>
102 1.1 joff
103 1.1 joff /* prototypes */
104 1.1 joff void isa_tsarm_init(u_int, u_int);
105 1.1 joff struct arm32_isa_chipset isa_chipset_tag;
106 1.1 joff
107 1.1 joff static unsigned int ep93xxirq[3] = { 20, 33, 40 };
108 1.1 joff /* only have 3 irqs connected to real lines on TS-7xxx */
109 1.1 joff static unsigned int isairq[3] = { 5, 6, 7 };
110 1.1 joff static unsigned int isairq_nhandlers[3] = { 0, 0, 0 };
111 1.1 joff
112 1.1 joff int
113 1.1 joff isa_intr_alloc(ic, mask, type, irq)
114 1.1 joff isa_chipset_tag_t ic;
115 1.1 joff int mask;
116 1.1 joff int type;
117 1.1 joff int *irq;
118 1.1 joff {
119 1.1 joff int i, bestirq, count;
120 1.1 joff
121 1.1 joff if (type == IST_NONE)
122 1.1 joff panic("intr_alloc: bogus type");
123 1.1 joff
124 1.1 joff bestirq = -1;
125 1.1 joff count = -1;
126 1.1 joff
127 1.1 joff /* some interrupts should never be dynamically allocated */
128 1.1 joff mask &= 0xff1f;
129 1.1 joff
130 1.1 joff for (i = 0; i < sizeof(isairq); i++) {
131 1.1 joff if ((mask & (1<<isairq[i])) == 0)
132 1.1 joff continue;
133 1.1 joff if (isairq_nhandlers[i] < count || count == -1) {
134 1.1 joff bestirq = isairq[i];
135 1.1 joff count = isairq_nhandlers[i];
136 1.1 joff }
137 1.1 joff }
138 1.1 joff
139 1.1 joff if (bestirq == -1)
140 1.1 joff return (1);
141 1.1 joff
142 1.1 joff *irq = bestirq;
143 1.1 joff
144 1.1 joff return (0);
145 1.1 joff }
146 1.1 joff
147 1.1 joff const struct evcnt *
148 1.1 joff isa_intr_evcnt(isa_chipset_tag_t ic, int irq)
149 1.1 joff {
150 1.1 joff return NULL;
151 1.1 joff }
152 1.1 joff
153 1.1 joff /*
154 1.1 joff * Set up an interrupt handler to start being called.
155 1.1 joff */
156 1.1 joff void *
157 1.1 joff isa_intr_establish(ic, irq, type, level, ih_fun, ih_arg)
158 1.1 joff isa_chipset_tag_t ic;
159 1.1 joff int irq;
160 1.1 joff int type;
161 1.1 joff int level;
162 1.1 joff int (*ih_fun) __P((void *));
163 1.1 joff void *ih_arg;
164 1.1 joff {
165 1.1 joff int epirq = -1, i;
166 1.1 joff /* Find real EP93XX irq number */
167 1.1 joff for(i = 0; i < sizeof(isairq); i++) {
168 1.1 joff if (irq == isairq[i]) epirq = ep93xxirq[i];
169 1.1 joff }
170 1.1 joff
171 1.1 joff if (epirq == -1)
172 1.1 joff return NULL;
173 1.1 joff else
174 1.1 joff return (ep93xx_intr_establish(epirq, level, ih_fun, ih_arg));
175 1.1 joff }
176 1.1 joff
177 1.1 joff /*
178 1.1 joff * Deregister an interrupt handler.
179 1.1 joff */
180 1.1 joff void
181 1.1 joff isa_intr_disestablish(ic, arg)
182 1.1 joff isa_chipset_tag_t ic;
183 1.1 joff void *arg;
184 1.1 joff {
185 1.1 joff ep93xx_intr_disestablish(arg);
186 1.1 joff }
187 1.1 joff
188 1.1 joff void
189 1.1 joff isa_tsarm_init(iobase16, membase16)
190 1.1 joff u_int iobase16, membase16;
191 1.1 joff {
192 1.1 joff isa_io_init(iobase16, membase16);
193 1.1 joff }
194 1.1 joff
195 1.1 joff
196 1.1 joff /*
197 1.1 joff * isa_intr_init()
198 1.1 joff *
199 1.1 joff * TODO: Set up ISA IRQ 5 on GPIO pin
200 1.1 joff */
201 1.1 joff void
202 1.1 joff isa_intr_init(void)
203 1.1 joff {
204 1.1 joff }
205 1.1 joff
206 1.1 joff void
207 1.1 joff isa_attach_hook(parent, self, iba)
208 1.1 joff struct device *parent, *self;
209 1.1 joff struct isabus_attach_args *iba;
210 1.1 joff {
211 1.1 joff /*
212 1.1 joff * Since we can only have one ISA bus, we just use a single
213 1.1 joff * statically allocated ISA chipset structure. Pass it up
214 1.1 joff * now.
215 1.1 joff */
216 1.1 joff iba->iba_ic = &isa_chipset_tag;
217 1.1 joff printf(": PC/104 expansion bus");
218 1.1 joff }
219