machdep.c revision 1.17 1 1.17 simonb /* $NetBSD: machdep.c,v 1.17 2020/07/13 05:20:45 simonb Exp $ */
2 1.1 hikaru
3 1.1 hikaru /*
4 1.1 hikaru * Copyright 2001, 2002 Wasabi Systems, Inc.
5 1.1 hikaru * All rights reserved.
6 1.1 hikaru *
7 1.1 hikaru * Written by Jason R. Thorpe and Simon Burge for Wasabi Systems, Inc.
8 1.1 hikaru *
9 1.1 hikaru * Redistribution and use in source and binary forms, with or without
10 1.1 hikaru * modification, are permitted provided that the following conditions
11 1.1 hikaru * are met:
12 1.1 hikaru * 1. Redistributions of source code must retain the above copyright
13 1.1 hikaru * notice, this list of conditions and the following disclaimer.
14 1.1 hikaru * 2. Redistributions in binary form must reproduce the above copyright
15 1.1 hikaru * notice, this list of conditions and the following disclaimer in the
16 1.1 hikaru * documentation and/or other materials provided with the distribution.
17 1.1 hikaru * 3. All advertising materials mentioning features or use of this software
18 1.1 hikaru * must display the following acknowledgement:
19 1.1 hikaru * This product includes software developed for the NetBSD Project by
20 1.1 hikaru * Wasabi Systems, Inc.
21 1.1 hikaru * 4. The name of Wasabi Systems, Inc. may not be used to endorse
22 1.1 hikaru * or promote products derived from this software without specific prior
23 1.1 hikaru * written permission.
24 1.1 hikaru *
25 1.1 hikaru * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
26 1.1 hikaru * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
27 1.1 hikaru * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
28 1.1 hikaru * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
29 1.1 hikaru * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
30 1.1 hikaru * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
31 1.1 hikaru * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
32 1.1 hikaru * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
33 1.1 hikaru * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
34 1.1 hikaru * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
35 1.1 hikaru * POSSIBILITY OF SUCH DAMAGE.
36 1.1 hikaru */
37 1.1 hikaru
38 1.1 hikaru /*
39 1.1 hikaru * Copyright (c) 1992, 1993
40 1.1 hikaru * The Regents of the University of California. All rights reserved.
41 1.1 hikaru *
42 1.1 hikaru * This code is derived from software contributed to Berkeley by
43 1.1 hikaru * the Systems Programming Group of the University of Utah Computer
44 1.1 hikaru * Science Department, The Mach Operating System project at
45 1.1 hikaru * Carnegie-Mellon University and Ralph Campbell.
46 1.1 hikaru *
47 1.1 hikaru * Redistribution and use in source and binary forms, with or without
48 1.1 hikaru * modification, are permitted provided that the following conditions
49 1.1 hikaru * are met:
50 1.1 hikaru * 1. Redistributions of source code must retain the above copyright
51 1.1 hikaru * notice, this list of conditions and the following disclaimer.
52 1.1 hikaru * 2. Redistributions in binary form must reproduce the above copyright
53 1.1 hikaru * notice, this list of conditions and the following disclaimer in the
54 1.1 hikaru * documentation and/or other materials provided with the distribution.
55 1.1 hikaru * 3. Neither the name of the University nor the names of its contributors
56 1.1 hikaru * may be used to endorse or promote products derived from this software
57 1.1 hikaru * without specific prior written permission.
58 1.1 hikaru *
59 1.1 hikaru * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
60 1.1 hikaru * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
61 1.1 hikaru * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
62 1.1 hikaru * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
63 1.1 hikaru * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
64 1.1 hikaru * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
65 1.1 hikaru * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
66 1.1 hikaru * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
67 1.1 hikaru * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
68 1.1 hikaru * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
69 1.1 hikaru * SUCH DAMAGE.
70 1.1 hikaru *
71 1.1 hikaru * @(#)machdep.c 8.3 (Berkeley) 1/12/94
72 1.1 hikaru * from: Utah Hdr: machdep.c 1.63 91/04/24
73 1.1 hikaru */
74 1.1 hikaru /*
75 1.1 hikaru * Copyright (c) 1988 University of Utah.
76 1.1 hikaru *
77 1.1 hikaru * This code is derived from software contributed to Berkeley by
78 1.1 hikaru * the Systems Programming Group of the University of Utah Computer
79 1.1 hikaru * Science Department, The Mach Operating System project at
80 1.1 hikaru * Carnegie-Mellon University and Ralph Campbell.
81 1.1 hikaru *
82 1.1 hikaru * Redistribution and use in source and binary forms, with or without
83 1.1 hikaru * modification, are permitted provided that the following conditions
84 1.1 hikaru * are met:
85 1.1 hikaru * 1. Redistributions of source code must retain the above copyright
86 1.1 hikaru * notice, this list of conditions and the following disclaimer.
87 1.1 hikaru * 2. Redistributions in binary form must reproduce the above copyright
88 1.1 hikaru * notice, this list of conditions and the following disclaimer in the
89 1.1 hikaru * documentation and/or other materials provided with the distribution.
90 1.1 hikaru * 3. All advertising materials mentioning features or use of this software
91 1.1 hikaru * must display the following acknowledgement:
92 1.1 hikaru * This product includes software developed by the University of
93 1.1 hikaru * California, Berkeley and its contributors.
94 1.1 hikaru * 4. Neither the name of the University nor the names of its contributors
95 1.1 hikaru * may be used to endorse or promote products derived from this software
96 1.1 hikaru * without specific prior written permission.
97 1.1 hikaru *
98 1.1 hikaru * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
99 1.1 hikaru * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
100 1.1 hikaru * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
101 1.1 hikaru * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
102 1.1 hikaru * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
103 1.1 hikaru * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
104 1.1 hikaru * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
105 1.1 hikaru * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
106 1.1 hikaru * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
107 1.1 hikaru * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
108 1.1 hikaru * SUCH DAMAGE.
109 1.1 hikaru *
110 1.1 hikaru * @(#)machdep.c 8.3 (Berkeley) 1/12/94
111 1.1 hikaru * from: Utah Hdr: machdep.c 1.63 91/04/24
112 1.1 hikaru */
113 1.1 hikaru
114 1.5 matt #include "opt_multiprocessor.h"
115 1.5 matt
116 1.1 hikaru #include <sys/cdefs.h>
117 1.17 simonb __KERNEL_RCSID(0, "$NetBSD: machdep.c,v 1.17 2020/07/13 05:20:45 simonb Exp $");
118 1.1 hikaru
119 1.1 hikaru #include <sys/param.h>
120 1.1 hikaru #include <sys/systm.h>
121 1.1 hikaru #include <sys/kernel.h>
122 1.1 hikaru #include <sys/buf.h>
123 1.2 matt #include <sys/cpu.h>
124 1.1 hikaru #include <sys/reboot.h>
125 1.1 hikaru #include <sys/mount.h>
126 1.1 hikaru #include <sys/kcore.h>
127 1.1 hikaru #include <sys/boot_flag.h>
128 1.1 hikaru #include <sys/termios.h>
129 1.1 hikaru #include <sys/ksyms.h>
130 1.1 hikaru
131 1.1 hikaru #include <uvm/uvm_extern.h>
132 1.1 hikaru
133 1.1 hikaru #include <dev/cons.h>
134 1.1 hikaru
135 1.1 hikaru #include "ksyms.h"
136 1.1 hikaru
137 1.1 hikaru #if NKSYMS || defined(DDB) || defined(LKM)
138 1.1 hikaru #include <machine/db_machdep.h>
139 1.1 hikaru #include <ddb/db_extern.h>
140 1.1 hikaru #endif
141 1.1 hikaru
142 1.1 hikaru #include <machine/psl.h>
143 1.1 hikaru #include <machine/locore.h>
144 1.1 hikaru
145 1.1 hikaru #include <mips/cavium/autoconf.h>
146 1.1 hikaru #include <mips/cavium/octeonvar.h>
147 1.1 hikaru #include <mips/cavium/include/iobusvar.h>
148 1.1 hikaru #include <mips/cavium/include/bootbusvar.h>
149 1.1 hikaru
150 1.1 hikaru #include <mips/cavium/dev/octeon_uartreg.h>
151 1.1 hikaru #include <mips/cavium/dev/octeon_ciureg.h>
152 1.1 hikaru #include <mips/cavium/dev/octeon_gpioreg.h>
153 1.1 hikaru
154 1.1 hikaru #include <evbmips/cavium/octeon_uboot.h>
155 1.1 hikaru
156 1.1 hikaru static void mach_init_vector(void);
157 1.1 hikaru static void mach_init_bus_space(void);
158 1.1 hikaru static void mach_init_console(void);
159 1.13 simonb static void mach_init_memory(void);
160 1.16 simonb static void parse_boot_args(void);
161 1.1 hikaru
162 1.1 hikaru #include "com.h"
163 1.1 hikaru #if NCOM > 0
164 1.1 hikaru #include <dev/ic/comreg.h>
165 1.1 hikaru #include <dev/ic/comvar.h>
166 1.1 hikaru int comcnrate = 115200; /* XXX should be config option */
167 1.1 hikaru #endif /* NCOM > 0 */
168 1.1 hikaru
169 1.1 hikaru /* Maps for VM objects. */
170 1.1 hikaru struct vm_map *phys_map = NULL;
171 1.1 hikaru
172 1.1 hikaru int netboot;
173 1.1 hikaru
174 1.1 hikaru phys_ram_seg_t mem_clusters[VM_PHYSSEG_MAX];
175 1.1 hikaru int mem_cluster_cnt;
176 1.13 simonb extern char kernel_text[];
177 1.13 simonb extern char edata[];
178 1.13 simonb extern char end[];
179 1.1 hikaru
180 1.1 hikaru void mach_init(uint64_t, uint64_t, uint64_t, uint64_t);
181 1.1 hikaru
182 1.1 hikaru struct octeon_config octeon_configuration;
183 1.16 simonb struct octeon_btdesc octeon_btdesc;
184 1.1 hikaru struct octeon_btinfo octeon_btinfo;
185 1.1 hikaru
186 1.6 matt char octeon_nmi_stack[PAGE_SIZE] __section(".data1") __aligned(PAGE_SIZE);
187 1.6 matt
188 1.1 hikaru /*
189 1.1 hikaru * Do all the stuff that locore normally does before calling main().
190 1.1 hikaru */
191 1.1 hikaru void
192 1.1 hikaru mach_init(uint64_t arg0, uint64_t arg1, uint64_t arg2, uint64_t arg3)
193 1.1 hikaru {
194 1.1 hikaru uint64_t btinfo_paddr;
195 1.12 simonb
196 1.12 simonb /* clear the BSS segment */
197 1.12 simonb memset(edata, 0, end - edata);
198 1.1 hikaru
199 1.17 simonb cpu_reset_address = octeon_soft_reset;
200 1.17 simonb
201 1.1 hikaru KASSERT(MIPS_XKPHYS_P(arg3));
202 1.6 matt btinfo_paddr = mips3_ld(arg3 + OCTEON_BTINFO_PADDR_OFFSET);
203 1.1 hikaru
204 1.16 simonb /* XXX KASSERT these addresses? */
205 1.16 simonb memcpy(&octeon_btdesc, (void *)arg3, sizeof(octeon_btdesc));
206 1.16 simonb if ((octeon_btdesc.obt_desc_ver == OCTEON_SUPPORTED_DESCRIPTOR_VERSION) &&
207 1.16 simonb (octeon_btdesc.obt_desc_size == sizeof(octeon_btdesc))) {
208 1.16 simonb btinfo_paddr = MIPS_PHYS_TO_XKPHYS(CCA_CACHEABLE,
209 1.16 simonb octeon_btdesc.obt_boot_info_addr);
210 1.16 simonb } else {
211 1.16 simonb panic("unknown boot descriptor size %u",
212 1.16 simonb octeon_btdesc.obt_desc_size);
213 1.16 simonb }
214 1.16 simonb memcpy(&octeon_btinfo, (void *)btinfo_paddr, sizeof(octeon_btinfo));
215 1.16 simonb parse_boot_args();
216 1.1 hikaru
217 1.14 simonb octeon_cal_timer(octeon_btinfo.obt_eclock_hz);
218 1.1 hikaru
219 1.14 simonb cpu_setmodel("Cavium Octeon %s",
220 1.14 simonb octeon_cpu_model(mips_options.mips_cpu_id));
221 1.7 skrll
222 1.1 hikaru mach_init_vector();
223 1.1 hikaru
224 1.9 cherry uvm_md_init();
225 1.1 hikaru
226 1.1 hikaru mach_init_bus_space();
227 1.1 hikaru
228 1.1 hikaru mach_init_console();
229 1.1 hikaru
230 1.16 simonb #ifdef DEBUG
231 1.16 simonb /* Show a couple of boot desc/info params for positive feedback */
232 1.16 simonb printf(">> boot desc eclock = %d\n", octeon_btdesc.obt_eclock);
233 1.16 simonb printf(">> boot info board = %d\n", octeon_btinfo.obt_board_type);
234 1.16 simonb #endif /* DEBUG */
235 1.16 simonb
236 1.13 simonb mach_init_memory();
237 1.1 hikaru
238 1.1 hikaru /*
239 1.1 hikaru * Allocate uarea page for lwp0 and set it.
240 1.1 hikaru */
241 1.1 hikaru mips_init_lwp0_uarea();
242 1.1 hikaru
243 1.6 matt #if 0
244 1.6 matt curcpu()->ci_nmi_stack = octeon_nmi_stack + sizeof(octeon_nmi_stack) - sizeof(struct kernframe);
245 1.6 matt *(uint64_t *)MIPS_PHYS_TO_KSEG0(0x800) = (intptr_t)octeon_reset_vector;
246 1.6 matt const uint64_t wdog_reg = MIPS_PHYS_TO_XKPHYS_UNCACHED(CIU_WDOG0);
247 1.6 matt uint64_t wdog = mips3_ld(wdog_reg);
248 1.6 matt wdog &= ~(CIU_WDOGX_MODE|CIU_WDOGX_LEN);
249 1.6 matt wdog |= __SHIFTIN(3, CIU_WDOGX_MODE);
250 1.6 matt wdog |= CIU_WDOGX_LEN; // max period
251 1.6 matt mips64_sd_a64(wdog_reg, wdog);
252 1.6 matt printf("Watchdog enabled!\n");
253 1.6 matt #endif
254 1.6 matt
255 1.1 hikaru #if defined(DDB)
256 1.1 hikaru if (boothowto & RB_KDB)
257 1.1 hikaru Debugger();
258 1.1 hikaru #endif
259 1.1 hikaru }
260 1.1 hikaru
261 1.1 hikaru void
262 1.1 hikaru consinit(void)
263 1.1 hikaru {
264 1.1 hikaru
265 1.1 hikaru /*
266 1.1 hikaru * Everything related to console initialization is done
267 1.1 hikaru * in mach_init().
268 1.1 hikaru */
269 1.1 hikaru }
270 1.1 hikaru
271 1.1 hikaru void
272 1.1 hikaru mach_init_vector(void)
273 1.1 hikaru {
274 1.1 hikaru
275 1.1 hikaru /* Make sure exception base at 0 (MIPS_COP_0_EBASE) */
276 1.5 matt __asm __volatile("mtc0 %0, $15, 1" : : "r"(0x80000000) );
277 1.1 hikaru
278 1.1 hikaru /*
279 1.1 hikaru * Set up the exception vectors and CPU-specific function
280 1.1 hikaru * vectors early on. We need the wbflush() vector set up
281 1.1 hikaru * before comcnattach() is called (or at least before the
282 1.1 hikaru * first printf() after that is called).
283 1.1 hikaru * Also clears the I+D caches.
284 1.1 hikaru */
285 1.4 matt mips_vector_init(NULL, true);
286 1.1 hikaru }
287 1.1 hikaru
288 1.1 hikaru void
289 1.1 hikaru mach_init_bus_space(void)
290 1.1 hikaru {
291 1.1 hikaru struct octeon_config *mcp = &octeon_configuration;
292 1.1 hikaru
293 1.1 hikaru octeon_dma_init(mcp);
294 1.1 hikaru
295 1.1 hikaru iobus_bootstrap(mcp);
296 1.1 hikaru bootbus_bootstrap(mcp);
297 1.1 hikaru }
298 1.1 hikaru
299 1.1 hikaru void
300 1.1 hikaru mach_init_console(void)
301 1.1 hikaru {
302 1.1 hikaru #if NCOM > 0
303 1.1 hikaru struct octeon_config *mcp = &octeon_configuration;
304 1.1 hikaru int status;
305 1.11 simonb extern int octuart_com_cnattach(bus_space_tag_t, int, int);
306 1.1 hikaru
307 1.1 hikaru /*
308 1.1 hikaru * Delay to allow firmware putchars to complete.
309 1.1 hikaru * FIFO depth * character time.
310 1.1 hikaru * character time = (1000000 / (defaultrate / 10))
311 1.1 hikaru */
312 1.1 hikaru delay(640000000 / comcnrate);
313 1.1 hikaru
314 1.11 simonb status = octuart_com_cnattach(
315 1.1 hikaru &mcp->mc_iobus_bust,
316 1.1 hikaru 0, /* XXX port 0 */
317 1.1 hikaru comcnrate);
318 1.1 hikaru if (status != 0)
319 1.1 hikaru panic("can't initialize console!"); /* XXX print to nowhere! */
320 1.1 hikaru #else
321 1.1 hikaru panic("octeon: not configured to use serial console");
322 1.1 hikaru #endif /* NCOM > 0 */
323 1.1 hikaru }
324 1.1 hikaru
325 1.13 simonb static void
326 1.13 simonb mach_init_memory(void)
327 1.1 hikaru {
328 1.13 simonb struct octeon_bootmem_desc *memdesc;
329 1.13 simonb struct octeon_bootmem_block_header *block;
330 1.13 simonb paddr_t blockaddr;
331 1.13 simonb int i;
332 1.13 simonb
333 1.13 simonb mem_cluster_cnt = 0;
334 1.13 simonb
335 1.13 simonb if (octeon_btinfo.obt_phy_mem_desc_addr == 0)
336 1.13 simonb panic("bootmem desc is missing");
337 1.13 simonb
338 1.13 simonb memdesc = (void *)MIPS_PHYS_TO_XKPHYS(CCA_CACHEABLE,
339 1.13 simonb octeon_btinfo.obt_phy_mem_desc_addr);
340 1.13 simonb printf("u-boot bootmem desc @ 0x%x version %d.%d\n",
341 1.13 simonb octeon_btinfo.obt_phy_mem_desc_addr,
342 1.13 simonb memdesc->bmd_major_version, memdesc->bmd_minor_version);
343 1.13 simonb if (memdesc->bmd_major_version > 3)
344 1.13 simonb panic("unhandled bootmem desc version %d.%d",
345 1.13 simonb memdesc->bmd_major_version, memdesc->bmd_minor_version);
346 1.13 simonb
347 1.13 simonb blockaddr = memdesc->bmd_head_addr;
348 1.13 simonb if (blockaddr == 0)
349 1.13 simonb panic("bootmem list is empty");
350 1.13 simonb
351 1.13 simonb for (i = 0; i < VM_PHYSSEG_MAX && blockaddr != 0;
352 1.13 simonb i++, blockaddr = block->bbh_next_block_addr) {
353 1.13 simonb block = (void *)MIPS_PHYS_TO_XKPHYS(CCA_CACHEABLE, blockaddr);
354 1.13 simonb
355 1.13 simonb mem_clusters[mem_cluster_cnt].start = blockaddr;
356 1.13 simonb mem_clusters[mem_cluster_cnt].size = block->bbh_size;
357 1.13 simonb mem_cluster_cnt++;
358 1.1 hikaru }
359 1.1 hikaru
360 1.13 simonb physmem = btoc(octeon_btinfo.obt_dram_size * 1024 * 1024);
361 1.7 skrll
362 1.3 matt #ifdef MULTIPROCESSOR
363 1.3 matt const u_int cores = mipsNN_cp0_ebase_read() & MIPS_EBASE_CPUNUM;
364 1.3 matt mem_clusters[0].start = cores * 4096;
365 1.3 matt #endif
366 1.3 matt
367 1.1 hikaru /*
368 1.1 hikaru * Load the rest of the available pages into the VM system.
369 1.1 hikaru */
370 1.3 matt mips_page_physload(mips_trunc_page(kernel_text), mips_round_page(end),
371 1.1 hikaru mem_clusters, mem_cluster_cnt, NULL, 0);
372 1.1 hikaru
373 1.1 hikaru /*
374 1.1 hikaru * Initialize error message buffer (at end of core).
375 1.1 hikaru */
376 1.1 hikaru mips_init_msgbuf();
377 1.1 hikaru
378 1.1 hikaru pmap_bootstrap();
379 1.1 hikaru }
380 1.1 hikaru
381 1.16 simonb void
382 1.16 simonb parse_boot_args(void)
383 1.16 simonb {
384 1.16 simonb int i;
385 1.16 simonb char *arg, *p;
386 1.16 simonb
387 1.16 simonb for (i = 0; i < octeon_btdesc.obt_argc; i++) {
388 1.16 simonb arg = (char *)MIPS_PHYS_TO_KSEG0(octeon_btdesc.obt_argv[i]);
389 1.16 simonb if (*arg == '-') {
390 1.16 simonb for (p = arg + 1; *p; p++) {
391 1.16 simonb switch (*p) {
392 1.16 simonb case '1':
393 1.16 simonb boothowto |= RB_MD1;
394 1.16 simonb break;
395 1.16 simonb case 's':
396 1.16 simonb boothowto |= RB_SINGLE;
397 1.16 simonb break;
398 1.16 simonb case 'd':
399 1.16 simonb boothowto |= RB_KDB;
400 1.16 simonb break;
401 1.16 simonb case 'a':
402 1.16 simonb boothowto |= RB_ASKNAME;
403 1.16 simonb break;
404 1.16 simonb case 'q':
405 1.16 simonb boothowto |= AB_QUIET;
406 1.16 simonb break;
407 1.16 simonb case 'v':
408 1.16 simonb boothowto |= AB_VERBOSE;
409 1.16 simonb break;
410 1.16 simonb case 'x':
411 1.16 simonb boothowto |= AB_DEBUG;
412 1.16 simonb break;
413 1.16 simonb case 'z':
414 1.16 simonb boothowto |= AB_SILENT;
415 1.16 simonb break;
416 1.16 simonb }
417 1.16 simonb }
418 1.16 simonb }
419 1.16 simonb if (strncmp(arg, "root=", 5) == 0)
420 1.16 simonb rootspec = strchr(arg, '=') + 1;
421 1.16 simonb }
422 1.16 simonb }
423 1.16 simonb
424 1.1 hikaru /*
425 1.1 hikaru * cpu_startup
426 1.1 hikaru * cpu_reboot
427 1.1 hikaru */
428 1.1 hikaru
429 1.1 hikaru int waittime = -1;
430 1.1 hikaru
431 1.1 hikaru /*
432 1.1 hikaru * Allocate memory for variable-sized tables,
433 1.1 hikaru */
434 1.1 hikaru void
435 1.1 hikaru cpu_startup(void)
436 1.1 hikaru {
437 1.5 matt #ifdef MULTIPROCESSOR
438 1.5 matt // Create a kcpuset so we can see on which CPUs the kernel was started.
439 1.5 matt kcpuset_create(&cpus_booted, true);
440 1.5 matt #endif
441 1.5 matt
442 1.1 hikaru /*
443 1.1 hikaru * Do the common startup items.
444 1.1 hikaru */
445 1.1 hikaru cpu_startup_common();
446 1.1 hikaru
447 1.1 hikaru /*
448 1.1 hikaru * Virtual memory is bootstrapped -- notify the bus spaces
449 1.1 hikaru * that memory allocation is now safe.
450 1.1 hikaru */
451 1.1 hikaru octeon_configuration.mc_mallocsafe = 1;
452 1.1 hikaru }
453 1.1 hikaru
454 1.1 hikaru void
455 1.1 hikaru cpu_reboot(int howto, char *bootstr)
456 1.1 hikaru {
457 1.1 hikaru
458 1.1 hikaru /* Take a snapshot before clobbering any registers. */
459 1.1 hikaru savectx(curpcb);
460 1.1 hikaru
461 1.1 hikaru if (cold) {
462 1.1 hikaru howto |= RB_HALT;
463 1.1 hikaru goto haltsys;
464 1.1 hikaru }
465 1.1 hikaru
466 1.1 hikaru /* If "always halt" was specified as a boot flag, obey. */
467 1.1 hikaru if (boothowto & RB_HALT)
468 1.1 hikaru howto |= RB_HALT;
469 1.1 hikaru
470 1.1 hikaru boothowto = howto;
471 1.1 hikaru if ((howto & RB_NOSYNC) == 0 && (waittime < 0)) {
472 1.1 hikaru waittime = 0;
473 1.1 hikaru vfs_shutdown();
474 1.1 hikaru
475 1.1 hikaru /*
476 1.1 hikaru * If we've been adjusting the clock, the todr
477 1.1 hikaru * will be out of synch; adjust it now.
478 1.1 hikaru */
479 1.1 hikaru resettodr();
480 1.1 hikaru }
481 1.1 hikaru
482 1.1 hikaru splhigh();
483 1.1 hikaru
484 1.1 hikaru if (howto & RB_DUMP)
485 1.1 hikaru dumpsys();
486 1.1 hikaru
487 1.1 hikaru haltsys:
488 1.1 hikaru doshutdownhooks();
489 1.1 hikaru
490 1.1 hikaru if (howto & RB_HALT) {
491 1.1 hikaru printf("\n");
492 1.1 hikaru printf("The operating system has halted.\n");
493 1.1 hikaru printf("Please press any key to reboot.\n\n");
494 1.8 martin cnpollc(1); /* For proper keyboard command handling */
495 1.8 martin cngetc();
496 1.8 martin cnpollc(0);
497 1.1 hikaru }
498 1.1 hikaru
499 1.1 hikaru printf("%s\n\n", ((howto & RB_HALT) != 0) ? "halted." : "rebooting...");
500 1.1 hikaru
501 1.1 hikaru /*
502 1.1 hikaru * Need a small delay here, otherwise we see the first few characters of
503 1.1 hikaru * the warning below.
504 1.1 hikaru */
505 1.1 hikaru delay(80000);
506 1.1 hikaru
507 1.14 simonb octeon_soft_reset();
508 1.1 hikaru
509 1.1 hikaru delay(1000000);
510 1.1 hikaru
511 1.1 hikaru printf("WARNING: reset failed!\nSpinning...");
512 1.1 hikaru
513 1.1 hikaru for (;;)
514 1.1 hikaru /* spin forever */ ; /* XXX */
515 1.1 hikaru }
516