machdep.c revision 1.12
1 /* $NetBSD: machdep.c,v 1.12 2020/06/04 03:08:59 simonb Exp $ */ 2 3 /* 4 * Copyright 2001, 2002 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Jason R. Thorpe and Simon Burge for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 /* 39 * Copyright (c) 1992, 1993 40 * The Regents of the University of California. All rights reserved. 41 * 42 * This code is derived from software contributed to Berkeley by 43 * the Systems Programming Group of the University of Utah Computer 44 * Science Department, The Mach Operating System project at 45 * Carnegie-Mellon University and Ralph Campbell. 46 * 47 * Redistribution and use in source and binary forms, with or without 48 * modification, are permitted provided that the following conditions 49 * are met: 50 * 1. Redistributions of source code must retain the above copyright 51 * notice, this list of conditions and the following disclaimer. 52 * 2. Redistributions in binary form must reproduce the above copyright 53 * notice, this list of conditions and the following disclaimer in the 54 * documentation and/or other materials provided with the distribution. 55 * 3. Neither the name of the University nor the names of its contributors 56 * may be used to endorse or promote products derived from this software 57 * without specific prior written permission. 58 * 59 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 60 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 61 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 62 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 63 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 64 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 65 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 66 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 67 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 68 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 69 * SUCH DAMAGE. 70 * 71 * @(#)machdep.c 8.3 (Berkeley) 1/12/94 72 * from: Utah Hdr: machdep.c 1.63 91/04/24 73 */ 74 /* 75 * Copyright (c) 1988 University of Utah. 76 * 77 * This code is derived from software contributed to Berkeley by 78 * the Systems Programming Group of the University of Utah Computer 79 * Science Department, The Mach Operating System project at 80 * Carnegie-Mellon University and Ralph Campbell. 81 * 82 * Redistribution and use in source and binary forms, with or without 83 * modification, are permitted provided that the following conditions 84 * are met: 85 * 1. Redistributions of source code must retain the above copyright 86 * notice, this list of conditions and the following disclaimer. 87 * 2. Redistributions in binary form must reproduce the above copyright 88 * notice, this list of conditions and the following disclaimer in the 89 * documentation and/or other materials provided with the distribution. 90 * 3. All advertising materials mentioning features or use of this software 91 * must display the following acknowledgement: 92 * This product includes software developed by the University of 93 * California, Berkeley and its contributors. 94 * 4. Neither the name of the University nor the names of its contributors 95 * may be used to endorse or promote products derived from this software 96 * without specific prior written permission. 97 * 98 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 99 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 100 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 101 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 102 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 103 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 104 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 105 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 106 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 107 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 108 * SUCH DAMAGE. 109 * 110 * @(#)machdep.c 8.3 (Berkeley) 1/12/94 111 * from: Utah Hdr: machdep.c 1.63 91/04/24 112 */ 113 114 #include "opt_multiprocessor.h" 115 #include "opt_cavium.h" 116 117 #include <sys/cdefs.h> 118 __KERNEL_RCSID(0, "$NetBSD: machdep.c,v 1.12 2020/06/04 03:08:59 simonb Exp $"); 119 120 #include <sys/param.h> 121 #include <sys/systm.h> 122 #include <sys/kernel.h> 123 #include <sys/buf.h> 124 #include <sys/cpu.h> 125 #include <sys/reboot.h> 126 #include <sys/mount.h> 127 #include <sys/kcore.h> 128 #include <sys/boot_flag.h> 129 #include <sys/termios.h> 130 #include <sys/ksyms.h> 131 132 #include <uvm/uvm_extern.h> 133 134 #include <dev/cons.h> 135 136 #include "ksyms.h" 137 138 #if NKSYMS || defined(DDB) || defined(LKM) 139 #include <machine/db_machdep.h> 140 #include <ddb/db_extern.h> 141 #endif 142 143 #include <machine/psl.h> 144 #include <machine/locore.h> 145 146 #include <mips/cavium/autoconf.h> 147 #include <mips/cavium/octeonvar.h> 148 #include <mips/cavium/include/iobusvar.h> 149 #include <mips/cavium/include/bootbusvar.h> 150 151 #include <mips/cavium/dev/octeon_uartreg.h> 152 #include <mips/cavium/dev/octeon_ciureg.h> 153 #include <mips/cavium/dev/octeon_gpioreg.h> 154 155 #include <evbmips/cavium/octeon_uboot.h> 156 157 static void mach_init_vector(void); 158 static void mach_init_bus_space(void); 159 static void mach_init_console(void); 160 static void mach_init_memory(u_quad_t); 161 162 #include "com.h" 163 #if NCOM > 0 164 #include <dev/ic/comreg.h> 165 #include <dev/ic/comvar.h> 166 int comcnrate = 115200; /* XXX should be config option */ 167 #endif /* NCOM > 0 */ 168 169 /* Maps for VM objects. */ 170 struct vm_map *phys_map = NULL; 171 172 int netboot; 173 174 phys_ram_seg_t mem_clusters[VM_PHYSSEG_MAX]; 175 int mem_cluster_cnt; 176 177 void mach_init(uint64_t, uint64_t, uint64_t, uint64_t); 178 179 struct octeon_config octeon_configuration; 180 struct octeon_btinfo octeon_btinfo; 181 182 char octeon_nmi_stack[PAGE_SIZE] __section(".data1") __aligned(PAGE_SIZE); 183 184 /* 185 * Do all the stuff that locore normally does before calling main(). 186 */ 187 void 188 mach_init(uint64_t arg0, uint64_t arg1, uint64_t arg2, uint64_t arg3) 189 { 190 uint64_t btinfo_paddr; 191 u_quad_t memsize; 192 int corefreq; 193 extern char edata[], end[]; 194 195 /* clear the BSS segment */ 196 memset(edata, 0, end - edata); 197 198 199 KASSERT(MIPS_XKPHYS_P(arg3)); 200 btinfo_paddr = mips3_ld(arg3 + OCTEON_BTINFO_PADDR_OFFSET); 201 202 /* Should be in first 256MB segment */ 203 KASSERT(btinfo_paddr < 256 * 1024 * 1024); 204 memcpy(&octeon_btinfo, 205 (struct octeon_btinfo *)MIPS_PHYS_TO_KSEG0(btinfo_paddr), 206 sizeof(octeon_btinfo)); 207 208 corefreq = octeon_btinfo.obt_eclock_hz; 209 #ifdef OCTEON_MEMSIZE // avoid uvm issue 210 memsize = OCTEON_MEMSIZE; 211 #else 212 memsize = octeon_btinfo.obt_dram_size * 1024 * 1024; 213 #endif 214 215 octeon_cal_timer(corefreq); 216 217 switch (MIPS_PRID_IMPL(mips_options.mips_cpu_id)) { 218 case 0: cpu_setmodel("Cavium Octeon CN38XX/CN36XX"); break; 219 case 1: cpu_setmodel("Cavium Octeon CN31XX/CN3020"); break; 220 case 2: cpu_setmodel("Cavium Octeon CN3005/CN3010"); break; 221 case 3: cpu_setmodel("Cavium Octeon CN58XX"); break; 222 case 4: cpu_setmodel("Cavium Octeon CN5[4-7]XX"); break; 223 case 6: cpu_setmodel("Cavium Octeon CN50XX"); break; 224 case 7: cpu_setmodel("Cavium Octeon CN52XX"); break; 225 default: cpu_setmodel("Cavium Octeon"); break; 226 } 227 228 mach_init_vector(); 229 230 uvm_md_init(); 231 232 mach_init_bus_space(); 233 234 mach_init_console(); 235 236 mach_init_memory(memsize); 237 238 /* 239 * Allocate uarea page for lwp0 and set it. 240 */ 241 mips_init_lwp0_uarea(); 242 243 boothowto = RB_AUTOBOOT; 244 boothowto |= AB_VERBOSE; 245 246 #if 0 247 curcpu()->ci_nmi_stack = octeon_nmi_stack + sizeof(octeon_nmi_stack) - sizeof(struct kernframe); 248 *(uint64_t *)MIPS_PHYS_TO_KSEG0(0x800) = (intptr_t)octeon_reset_vector; 249 const uint64_t wdog_reg = MIPS_PHYS_TO_XKPHYS_UNCACHED(CIU_WDOG0); 250 uint64_t wdog = mips3_ld(wdog_reg); 251 wdog &= ~(CIU_WDOGX_MODE|CIU_WDOGX_LEN); 252 wdog |= __SHIFTIN(3, CIU_WDOGX_MODE); 253 wdog |= CIU_WDOGX_LEN; // max period 254 mips64_sd_a64(wdog_reg, wdog); 255 printf("Watchdog enabled!\n"); 256 #endif 257 258 #if defined(DDB) 259 if (boothowto & RB_KDB) 260 Debugger(); 261 #endif 262 } 263 264 void 265 consinit(void) 266 { 267 268 /* 269 * Everything related to console initialization is done 270 * in mach_init(). 271 */ 272 } 273 274 void 275 mach_init_vector(void) 276 { 277 278 /* Make sure exception base at 0 (MIPS_COP_0_EBASE) */ 279 __asm __volatile("mtc0 %0, $15, 1" : : "r"(0x80000000) ); 280 281 /* 282 * Set up the exception vectors and CPU-specific function 283 * vectors early on. We need the wbflush() vector set up 284 * before comcnattach() is called (or at least before the 285 * first printf() after that is called). 286 * Also clears the I+D caches. 287 */ 288 mips_vector_init(NULL, true); 289 } 290 291 void 292 mach_init_bus_space(void) 293 { 294 struct octeon_config *mcp = &octeon_configuration; 295 296 octeon_dma_init(mcp); 297 298 iobus_bootstrap(mcp); 299 bootbus_bootstrap(mcp); 300 } 301 302 void 303 mach_init_console(void) 304 { 305 #if NCOM > 0 306 struct octeon_config *mcp = &octeon_configuration; 307 int status; 308 extern int octuart_com_cnattach(bus_space_tag_t, int, int); 309 310 /* 311 * Delay to allow firmware putchars to complete. 312 * FIFO depth * character time. 313 * character time = (1000000 / (defaultrate / 10)) 314 */ 315 delay(640000000 / comcnrate); 316 317 status = octuart_com_cnattach( 318 &mcp->mc_iobus_bust, 319 0, /* XXX port 0 */ 320 comcnrate); 321 if (status != 0) 322 panic("can't initialize console!"); /* XXX print to nowhere! */ 323 #else 324 panic("octeon: not configured to use serial console"); 325 #endif /* NCOM > 0 */ 326 } 327 328 void 329 mach_init_memory(u_quad_t memsize) 330 { 331 extern char kernel_text[]; 332 extern char end[]; 333 334 physmem = btoc(memsize); 335 336 if (memsize <= 256 * 1024 * 1024) { 337 mem_clusters[0].start = 0; 338 mem_clusters[0].size = memsize; 339 mem_cluster_cnt = 1; 340 } else if (memsize <= 512 * 1024 * 1024) { 341 mem_clusters[0].start = 0; 342 mem_clusters[0].size = 256 * 1024 * 1024; 343 mem_clusters[1].start = 0x410000000ULL; 344 mem_clusters[1].size = memsize - 256 * 1024 * 1024; 345 mem_cluster_cnt = 2; 346 } else { 347 mem_clusters[0].start = 0; 348 mem_clusters[0].size = 256 * 1024 * 1024; 349 mem_clusters[1].start = 0x20000000; 350 mem_clusters[1].size = memsize - 512 * 1024 * 1024; 351 mem_clusters[2].start = 0x410000000ULL; 352 mem_clusters[2].size = 256 * 1024 * 1024; 353 mem_cluster_cnt = 3; 354 } 355 356 357 #ifdef MULTIPROCESSOR 358 const u_int cores = mipsNN_cp0_ebase_read() & MIPS_EBASE_CPUNUM; 359 mem_clusters[0].start = cores * 4096; 360 #endif 361 362 /* 363 * Load the rest of the available pages into the VM system. 364 */ 365 mips_page_physload(mips_trunc_page(kernel_text), mips_round_page(end), 366 mem_clusters, mem_cluster_cnt, NULL, 0); 367 368 /* 369 * Initialize error message buffer (at end of core). 370 */ 371 mips_init_msgbuf(); 372 373 pmap_bootstrap(); 374 } 375 376 /* 377 * cpu_startup 378 * cpu_reboot 379 */ 380 381 int waittime = -1; 382 383 /* 384 * Allocate memory for variable-sized tables, 385 */ 386 void 387 cpu_startup(void) 388 { 389 #ifdef MULTIPROCESSOR 390 // Create a kcpuset so we can see on which CPUs the kernel was started. 391 kcpuset_create(&cpus_booted, true); 392 #endif 393 394 /* 395 * Do the common startup items. 396 */ 397 cpu_startup_common(); 398 399 /* 400 * Virtual memory is bootstrapped -- notify the bus spaces 401 * that memory allocation is now safe. 402 */ 403 octeon_configuration.mc_mallocsafe = 1; 404 } 405 406 void 407 cpu_reboot(int howto, char *bootstr) 408 { 409 410 /* Take a snapshot before clobbering any registers. */ 411 savectx(curpcb); 412 413 if (cold) { 414 howto |= RB_HALT; 415 goto haltsys; 416 } 417 418 /* If "always halt" was specified as a boot flag, obey. */ 419 if (boothowto & RB_HALT) 420 howto |= RB_HALT; 421 422 boothowto = howto; 423 if ((howto & RB_NOSYNC) == 0 && (waittime < 0)) { 424 waittime = 0; 425 vfs_shutdown(); 426 427 /* 428 * If we've been adjusting the clock, the todr 429 * will be out of synch; adjust it now. 430 */ 431 resettodr(); 432 } 433 434 splhigh(); 435 436 if (howto & RB_DUMP) 437 dumpsys(); 438 439 haltsys: 440 doshutdownhooks(); 441 442 if (howto & RB_HALT) { 443 printf("\n"); 444 printf("The operating system has halted.\n"); 445 printf("Please press any key to reboot.\n\n"); 446 cnpollc(1); /* For proper keyboard command handling */ 447 cngetc(); 448 cnpollc(0); 449 } 450 451 printf("%s\n\n", ((howto & RB_HALT) != 0) ? "halted." : "rebooting..."); 452 453 /* 454 * Need a small delay here, otherwise we see the first few characters of 455 * the warning below. 456 */ 457 delay(80000); 458 459 /* initiate chip soft-reset */ 460 uint64_t fuse = octeon_read_csr(CIU_FUSE); 461 octeon_write_csr(CIU_SOFT_BIST, fuse); 462 octeon_read_csr(CIU_SOFT_RST); 463 octeon_write_csr(CIU_SOFT_RST, fuse); 464 465 delay(1000000); 466 467 printf("WARNING: reset failed!\nSpinning..."); 468 469 for (;;) 470 /* spin forever */ ; /* XXX */ 471 } 472
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