machdep.c revision 1.4.2.2
1 /* $NetBSD: machdep.c,v 1.4.2.2 2015/06/06 14:39:59 skrll Exp $ */ 2 3 /* 4 * Copyright 2001, 2002 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Jason R. Thorpe and Simon Burge for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 /* 39 * Copyright (c) 1992, 1993 40 * The Regents of the University of California. All rights reserved. 41 * 42 * This code is derived from software contributed to Berkeley by 43 * the Systems Programming Group of the University of Utah Computer 44 * Science Department, The Mach Operating System project at 45 * Carnegie-Mellon University and Ralph Campbell. 46 * 47 * Redistribution and use in source and binary forms, with or without 48 * modification, are permitted provided that the following conditions 49 * are met: 50 * 1. Redistributions of source code must retain the above copyright 51 * notice, this list of conditions and the following disclaimer. 52 * 2. Redistributions in binary form must reproduce the above copyright 53 * notice, this list of conditions and the following disclaimer in the 54 * documentation and/or other materials provided with the distribution. 55 * 3. Neither the name of the University nor the names of its contributors 56 * may be used to endorse or promote products derived from this software 57 * without specific prior written permission. 58 * 59 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 60 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 61 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 62 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 63 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 64 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 65 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 66 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 67 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 68 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 69 * SUCH DAMAGE. 70 * 71 * @(#)machdep.c 8.3 (Berkeley) 1/12/94 72 * from: Utah Hdr: machdep.c 1.63 91/04/24 73 */ 74 /* 75 * Copyright (c) 1988 University of Utah. 76 * 77 * This code is derived from software contributed to Berkeley by 78 * the Systems Programming Group of the University of Utah Computer 79 * Science Department, The Mach Operating System project at 80 * Carnegie-Mellon University and Ralph Campbell. 81 * 82 * Redistribution and use in source and binary forms, with or without 83 * modification, are permitted provided that the following conditions 84 * are met: 85 * 1. Redistributions of source code must retain the above copyright 86 * notice, this list of conditions and the following disclaimer. 87 * 2. Redistributions in binary form must reproduce the above copyright 88 * notice, this list of conditions and the following disclaimer in the 89 * documentation and/or other materials provided with the distribution. 90 * 3. All advertising materials mentioning features or use of this software 91 * must display the following acknowledgement: 92 * This product includes software developed by the University of 93 * California, Berkeley and its contributors. 94 * 4. Neither the name of the University nor the names of its contributors 95 * may be used to endorse or promote products derived from this software 96 * without specific prior written permission. 97 * 98 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 99 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 100 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 101 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 102 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 103 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 104 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 105 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 106 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 107 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 108 * SUCH DAMAGE. 109 * 110 * @(#)machdep.c 8.3 (Berkeley) 1/12/94 111 * from: Utah Hdr: machdep.c 1.63 91/04/24 112 */ 113 114 #include <sys/cdefs.h> 115 __KERNEL_RCSID(0, "$NetBSD: machdep.c,v 1.4.2.2 2015/06/06 14:39:59 skrll Exp $"); 116 117 #include <sys/param.h> 118 #include <sys/systm.h> 119 #include <sys/kernel.h> 120 #include <sys/buf.h> 121 #include <sys/cpu.h> 122 #include <sys/reboot.h> 123 #include <sys/mount.h> 124 #include <sys/kcore.h> 125 #include <sys/boot_flag.h> 126 #include <sys/termios.h> 127 #include <sys/ksyms.h> 128 129 #include <uvm/uvm_extern.h> 130 131 #include <dev/cons.h> 132 133 #include "ksyms.h" 134 135 #if NKSYMS || defined(DDB) || defined(LKM) 136 #include <machine/db_machdep.h> 137 #include <ddb/db_extern.h> 138 #endif 139 140 #include <machine/psl.h> 141 #include <machine/locore.h> 142 143 #include <mips/cavium/autoconf.h> 144 #include <mips/cavium/octeonvar.h> 145 #include <mips/cavium/include/iobusvar.h> 146 #include <mips/cavium/include/bootbusvar.h> 147 148 #include <mips/cavium/dev/octeon_uartreg.h> 149 #include <mips/cavium/dev/octeon_ciureg.h> 150 #include <mips/cavium/dev/octeon_gpioreg.h> 151 152 #include <evbmips/cavium/octeon_uboot.h> 153 154 static void mach_init_bss(void); 155 static void mach_init_vector(void); 156 static void mach_init_bus_space(void); 157 static void mach_init_console(void); 158 static void mach_init_memory(u_quad_t); 159 160 #include "com.h" 161 #if NCOM > 0 162 #include <dev/ic/comreg.h> 163 #include <dev/ic/comvar.h> 164 int comcnrate = 115200; /* XXX should be config option */ 165 #endif /* NCOM > 0 */ 166 167 /* Maps for VM objects. */ 168 struct vm_map *phys_map = NULL; 169 170 int netboot; 171 172 phys_ram_seg_t mem_clusters[VM_PHYSSEG_MAX]; 173 int mem_cluster_cnt; 174 175 176 void configure(void); 177 void mach_init(uint64_t, uint64_t, uint64_t, uint64_t); 178 179 struct octeon_config octeon_configuration; 180 struct octeon_btinfo octeon_btinfo; 181 182 /* 183 * Do all the stuff that locore normally does before calling main(). 184 */ 185 void 186 mach_init(uint64_t arg0, uint64_t arg1, uint64_t arg2, uint64_t arg3) 187 { 188 uint64_t btinfo_paddr; 189 u_quad_t memsize; 190 int corefreq; 191 192 mach_init_bss(); 193 194 KASSERT(MIPS_XKPHYS_P(arg3)); 195 btinfo_paddr = mips64_ld_a64(arg3 + OCTEON_BTINFO_PADDR_OFFSET); 196 197 /* Should be in first 256MB segment */ 198 KASSERT(btinfo_paddr < 256 * 1024 * 1024); 199 memcpy(&octeon_btinfo, 200 (struct octeon_btinfo *)MIPS_PHYS_TO_KSEG0(btinfo_paddr), 201 sizeof(octeon_btinfo)); 202 203 corefreq = octeon_btinfo.obt_eclock_hz; 204 memsize = octeon_btinfo.obt_dram_size * 1024 * 1024; 205 206 octeon_cal_timer(corefreq); 207 208 switch (MIPS_PRID_IMPL(mips_options.mips_cpu_id)) { 209 case 0: cpu_setmodel("Cavium Octeon CN38XX/CN36XX"); break; 210 case 1: cpu_setmodel("Cavium Octeon CN31XX/CN3020"); break; 211 case 2: cpu_setmodel("Cavium Octeon CN3005/CN3010"); break; 212 case 3: cpu_setmodel("Cavium Octeon CN58XX"); break; 213 case 4: cpu_setmodel("Cavium Octeon CN5[4-7]XX"); break; 214 case 6: cpu_setmodel("Cavium Octeon CN50XX"); break; 215 case 7: cpu_setmodel("Cavium Octeon CN52XX"); break; 216 default: cpu_setmodel("Cavium Octeon"); break; 217 } 218 219 mach_init_vector(); 220 221 /* set the VM page size */ 222 uvm_setpagesize(); 223 224 mach_init_bus_space(); 225 226 mach_init_console(); 227 228 mach_init_memory(memsize); 229 230 /* 231 * Allocate uarea page for lwp0 and set it. 232 */ 233 mips_init_lwp0_uarea(); 234 235 boothowto = RB_AUTOBOOT; 236 237 #if defined(DDB) 238 if (boothowto & RB_KDB) 239 Debugger(); 240 #endif 241 } 242 243 void 244 consinit(void) 245 { 246 247 /* 248 * Everything related to console initialization is done 249 * in mach_init(). 250 */ 251 } 252 253 void 254 mach_init_bss(void) 255 { 256 extern char edata[], end[]; 257 258 /* 259 * Clear the BSS segment. 260 */ 261 memset(edata, 0, mips_round_page(end) - (uintptr_t)edata); 262 } 263 264 void 265 mach_init_vector(void) 266 { 267 268 /* Make sure exception base at 0 (MIPS_COP_0_EBASE) */ 269 asm volatile("mtc0 %0, $15, 1" : : "r"(0x80000000) ); 270 271 /* 272 * Set up the exception vectors and CPU-specific function 273 * vectors early on. We need the wbflush() vector set up 274 * before comcnattach() is called (or at least before the 275 * first printf() after that is called). 276 * Also clears the I+D caches. 277 */ 278 #if MULTIPROCESSOR 279 mips_vector_init(NULL, true); 280 #else 281 mips_vector_init(NULL, false); 282 #endif 283 } 284 285 void 286 mach_init_bus_space(void) 287 { 288 struct octeon_config *mcp = &octeon_configuration; 289 290 octeon_dma_init(mcp); 291 292 iobus_bootstrap(mcp); 293 bootbus_bootstrap(mcp); 294 } 295 296 void 297 mach_init_console(void) 298 { 299 #if NCOM > 0 300 struct octeon_config *mcp = &octeon_configuration; 301 int status; 302 extern int octeon_uart_com_cnattach(bus_space_tag_t, int, int); 303 304 /* 305 * Delay to allow firmware putchars to complete. 306 * FIFO depth * character time. 307 * character time = (1000000 / (defaultrate / 10)) 308 */ 309 delay(640000000 / comcnrate); 310 311 status = octeon_uart_com_cnattach( 312 &mcp->mc_iobus_bust, 313 0, /* XXX port 0 */ 314 comcnrate); 315 if (status != 0) 316 panic("can't initialize console!"); /* XXX print to nowhere! */ 317 #else 318 panic("octeon: not configured to use serial console"); 319 #endif /* NCOM > 0 */ 320 } 321 322 void 323 mach_init_memory(u_quad_t memsize) 324 { 325 extern char kernel_text[]; 326 extern char end[]; 327 328 physmem = btoc(memsize); 329 330 if (memsize <= 256 * 1024 * 1024) { 331 mem_clusters[0].start = 0; 332 mem_clusters[0].size = memsize; 333 mem_cluster_cnt = 1; 334 } else if (memsize <= 512 * 1024 * 1024) { 335 mem_clusters[0].start = 0; 336 mem_clusters[0].size = 256 * 1024 * 1024; 337 mem_clusters[1].start = 0x410000000ULL; 338 mem_clusters[1].size = memsize - 256 * 1024 * 1024; 339 mem_cluster_cnt = 2; 340 } else { 341 mem_clusters[0].start = 0; 342 mem_clusters[0].size = 256 * 1024 * 1024; 343 mem_clusters[1].start = 0x20000000; 344 mem_clusters[1].size = memsize - 512 * 1024 * 1024; 345 mem_clusters[2].start = 0x410000000ULL; 346 mem_clusters[2].size = 256 * 1024 * 1024; 347 mem_cluster_cnt = 3; 348 } 349 350 351 #ifdef MULTIPROCESSOR 352 const u_int cores = mipsNN_cp0_ebase_read() & MIPS_EBASE_CPUNUM; 353 mem_clusters[0].start = cores * 4096; 354 #endif 355 356 /* 357 * Load the rest of the available pages into the VM system. 358 */ 359 mips_page_physload(mips_trunc_page(kernel_text), mips_round_page(end), 360 mem_clusters, mem_cluster_cnt, NULL, 0); 361 362 /* 363 * Initialize error message buffer (at end of core). 364 */ 365 mips_init_msgbuf(); 366 367 pmap_bootstrap(); 368 } 369 370 /* 371 * cpu_startup 372 * cpu_reboot 373 */ 374 375 int waittime = -1; 376 377 /* 378 * Allocate memory for variable-sized tables, 379 */ 380 void 381 cpu_startup(void) 382 { 383 /* 384 * Do the common startup items. 385 */ 386 cpu_startup_common(); 387 388 /* 389 * Virtual memory is bootstrapped -- notify the bus spaces 390 * that memory allocation is now safe. 391 */ 392 octeon_configuration.mc_mallocsafe = 1; 393 } 394 395 void 396 cpu_reboot(int howto, char *bootstr) 397 { 398 399 /* Take a snapshot before clobbering any registers. */ 400 savectx(curpcb); 401 402 if (cold) { 403 howto |= RB_HALT; 404 goto haltsys; 405 } 406 407 /* If "always halt" was specified as a boot flag, obey. */ 408 if (boothowto & RB_HALT) 409 howto |= RB_HALT; 410 411 boothowto = howto; 412 if ((howto & RB_NOSYNC) == 0 && (waittime < 0)) { 413 waittime = 0; 414 vfs_shutdown(); 415 416 /* 417 * If we've been adjusting the clock, the todr 418 * will be out of synch; adjust it now. 419 */ 420 resettodr(); 421 } 422 423 splhigh(); 424 425 if (howto & RB_DUMP) 426 dumpsys(); 427 428 haltsys: 429 doshutdownhooks(); 430 431 if (howto & RB_HALT) { 432 printf("\n"); 433 printf("The operating system has halted.\n"); 434 printf("Please press any key to reboot.\n\n"); 435 } 436 437 printf("%s\n\n", ((howto & RB_HALT) != 0) ? "halted." : "rebooting..."); 438 439 /* 440 * Need a small delay here, otherwise we see the first few characters of 441 * the warning below. 442 */ 443 delay(80000); 444 445 /* initiate chip soft-reset */ 446 uint64_t fuse = octeon_read_csr(CIU_FUSE); 447 octeon_write_csr(CIU_SOFT_BIST, fuse); 448 octeon_read_csr(CIU_SOFT_RST); 449 octeon_write_csr(CIU_SOFT_RST, fuse); 450 451 delay(1000000); 452 453 printf("WARNING: reset failed!\nSpinning..."); 454 455 for (;;) 456 /* spin forever */ ; /* XXX */ 457 } 458
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