machdep.c revision 1.5
1 /* $NetBSD: machdep.c,v 1.5 2015/06/10 22:31:00 matt Exp $ */ 2 3 /* 4 * Copyright 2001, 2002 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Jason R. Thorpe and Simon Burge for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 /* 39 * Copyright (c) 1992, 1993 40 * The Regents of the University of California. All rights reserved. 41 * 42 * This code is derived from software contributed to Berkeley by 43 * the Systems Programming Group of the University of Utah Computer 44 * Science Department, The Mach Operating System project at 45 * Carnegie-Mellon University and Ralph Campbell. 46 * 47 * Redistribution and use in source and binary forms, with or without 48 * modification, are permitted provided that the following conditions 49 * are met: 50 * 1. Redistributions of source code must retain the above copyright 51 * notice, this list of conditions and the following disclaimer. 52 * 2. Redistributions in binary form must reproduce the above copyright 53 * notice, this list of conditions and the following disclaimer in the 54 * documentation and/or other materials provided with the distribution. 55 * 3. Neither the name of the University nor the names of its contributors 56 * may be used to endorse or promote products derived from this software 57 * without specific prior written permission. 58 * 59 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 60 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 61 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 62 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 63 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 64 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 65 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 66 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 67 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 68 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 69 * SUCH DAMAGE. 70 * 71 * @(#)machdep.c 8.3 (Berkeley) 1/12/94 72 * from: Utah Hdr: machdep.c 1.63 91/04/24 73 */ 74 /* 75 * Copyright (c) 1988 University of Utah. 76 * 77 * This code is derived from software contributed to Berkeley by 78 * the Systems Programming Group of the University of Utah Computer 79 * Science Department, The Mach Operating System project at 80 * Carnegie-Mellon University and Ralph Campbell. 81 * 82 * Redistribution and use in source and binary forms, with or without 83 * modification, are permitted provided that the following conditions 84 * are met: 85 * 1. Redistributions of source code must retain the above copyright 86 * notice, this list of conditions and the following disclaimer. 87 * 2. Redistributions in binary form must reproduce the above copyright 88 * notice, this list of conditions and the following disclaimer in the 89 * documentation and/or other materials provided with the distribution. 90 * 3. All advertising materials mentioning features or use of this software 91 * must display the following acknowledgement: 92 * This product includes software developed by the University of 93 * California, Berkeley and its contributors. 94 * 4. Neither the name of the University nor the names of its contributors 95 * may be used to endorse or promote products derived from this software 96 * without specific prior written permission. 97 * 98 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 99 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 100 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 101 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 102 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 103 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 104 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 105 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 106 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 107 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 108 * SUCH DAMAGE. 109 * 110 * @(#)machdep.c 8.3 (Berkeley) 1/12/94 111 * from: Utah Hdr: machdep.c 1.63 91/04/24 112 */ 113 114 #include "opt_multiprocessor.h" 115 116 #include <sys/cdefs.h> 117 __KERNEL_RCSID(0, "$NetBSD: machdep.c,v 1.5 2015/06/10 22:31:00 matt Exp $"); 118 119 #include <sys/param.h> 120 #include <sys/systm.h> 121 #include <sys/kernel.h> 122 #include <sys/buf.h> 123 #include <sys/cpu.h> 124 #include <sys/reboot.h> 125 #include <sys/mount.h> 126 #include <sys/kcore.h> 127 #include <sys/boot_flag.h> 128 #include <sys/termios.h> 129 #include <sys/ksyms.h> 130 131 #include <uvm/uvm_extern.h> 132 133 #include <dev/cons.h> 134 135 #include "ksyms.h" 136 137 #if NKSYMS || defined(DDB) || defined(LKM) 138 #include <machine/db_machdep.h> 139 #include <ddb/db_extern.h> 140 #endif 141 142 #include <machine/psl.h> 143 #include <machine/locore.h> 144 145 #include <mips/cavium/autoconf.h> 146 #include <mips/cavium/octeonvar.h> 147 #include <mips/cavium/include/iobusvar.h> 148 #include <mips/cavium/include/bootbusvar.h> 149 150 #include <mips/cavium/dev/octeon_uartreg.h> 151 #include <mips/cavium/dev/octeon_ciureg.h> 152 #include <mips/cavium/dev/octeon_gpioreg.h> 153 154 #include <evbmips/cavium/octeon_uboot.h> 155 156 static void mach_init_bss(void); 157 static void mach_init_vector(void); 158 static void mach_init_bus_space(void); 159 static void mach_init_console(void); 160 static void mach_init_memory(u_quad_t); 161 162 #include "com.h" 163 #if NCOM > 0 164 #include <dev/ic/comreg.h> 165 #include <dev/ic/comvar.h> 166 int comcnrate = 115200; /* XXX should be config option */ 167 #endif /* NCOM > 0 */ 168 169 /* Maps for VM objects. */ 170 struct vm_map *phys_map = NULL; 171 172 int netboot; 173 174 phys_ram_seg_t mem_clusters[VM_PHYSSEG_MAX]; 175 int mem_cluster_cnt; 176 177 void mach_init(uint64_t, uint64_t, uint64_t, uint64_t); 178 179 struct octeon_config octeon_configuration; 180 struct octeon_btinfo octeon_btinfo; 181 182 /* 183 * Do all the stuff that locore normally does before calling main(). 184 */ 185 void 186 mach_init(uint64_t arg0, uint64_t arg1, uint64_t arg2, uint64_t arg3) 187 { 188 uint64_t btinfo_paddr; 189 u_quad_t memsize; 190 int corefreq; 191 192 mach_init_bss(); 193 194 KASSERT(MIPS_XKPHYS_P(arg3)); 195 btinfo_paddr = mips64_ld_a64(arg3 + OCTEON_BTINFO_PADDR_OFFSET); 196 197 /* Should be in first 256MB segment */ 198 KASSERT(btinfo_paddr < 256 * 1024 * 1024); 199 memcpy(&octeon_btinfo, 200 (struct octeon_btinfo *)MIPS_PHYS_TO_KSEG0(btinfo_paddr), 201 sizeof(octeon_btinfo)); 202 203 corefreq = octeon_btinfo.obt_eclock_hz; 204 memsize = octeon_btinfo.obt_dram_size * 1024 * 1024; 205 206 octeon_cal_timer(corefreq); 207 208 switch (MIPS_PRID_IMPL(mips_options.mips_cpu_id)) { 209 case 0: cpu_setmodel("Cavium Octeon CN38XX/CN36XX"); break; 210 case 1: cpu_setmodel("Cavium Octeon CN31XX/CN3020"); break; 211 case 2: cpu_setmodel("Cavium Octeon CN3005/CN3010"); break; 212 case 3: cpu_setmodel("Cavium Octeon CN58XX"); break; 213 case 4: cpu_setmodel("Cavium Octeon CN5[4-7]XX"); break; 214 case 6: cpu_setmodel("Cavium Octeon CN50XX"); break; 215 case 7: cpu_setmodel("Cavium Octeon CN52XX"); break; 216 default: cpu_setmodel("Cavium Octeon"); break; 217 } 218 219 mach_init_vector(); 220 221 /* set the VM page size */ 222 uvm_setpagesize(); 223 224 mach_init_bus_space(); 225 226 mach_init_console(); 227 228 mach_init_memory(memsize); 229 230 /* 231 * Allocate uarea page for lwp0 and set it. 232 */ 233 mips_init_lwp0_uarea(); 234 235 boothowto = RB_AUTOBOOT; 236 boothowto |= AB_VERBOSE; 237 238 #if defined(DDB) 239 if (boothowto & RB_KDB) 240 Debugger(); 241 #endif 242 } 243 244 void 245 consinit(void) 246 { 247 248 /* 249 * Everything related to console initialization is done 250 * in mach_init(). 251 */ 252 } 253 254 void 255 mach_init_bss(void) 256 { 257 extern char edata[], end[]; 258 259 /* 260 * Clear the BSS segment. 261 */ 262 memset(edata, 0, mips_round_page(end) - (uintptr_t)edata); 263 } 264 265 void 266 mach_init_vector(void) 267 { 268 269 /* Make sure exception base at 0 (MIPS_COP_0_EBASE) */ 270 __asm __volatile("mtc0 %0, $15, 1" : : "r"(0x80000000) ); 271 272 /* 273 * Set up the exception vectors and CPU-specific function 274 * vectors early on. We need the wbflush() vector set up 275 * before comcnattach() is called (or at least before the 276 * first printf() after that is called). 277 * Also clears the I+D caches. 278 */ 279 mips_vector_init(NULL, true); 280 } 281 282 void 283 mach_init_bus_space(void) 284 { 285 struct octeon_config *mcp = &octeon_configuration; 286 287 octeon_dma_init(mcp); 288 289 iobus_bootstrap(mcp); 290 bootbus_bootstrap(mcp); 291 } 292 293 void 294 mach_init_console(void) 295 { 296 #if NCOM > 0 297 struct octeon_config *mcp = &octeon_configuration; 298 int status; 299 extern int octeon_uart_com_cnattach(bus_space_tag_t, int, int); 300 301 /* 302 * Delay to allow firmware putchars to complete. 303 * FIFO depth * character time. 304 * character time = (1000000 / (defaultrate / 10)) 305 */ 306 delay(640000000 / comcnrate); 307 308 status = octeon_uart_com_cnattach( 309 &mcp->mc_iobus_bust, 310 0, /* XXX port 0 */ 311 comcnrate); 312 if (status != 0) 313 panic("can't initialize console!"); /* XXX print to nowhere! */ 314 #else 315 panic("octeon: not configured to use serial console"); 316 #endif /* NCOM > 0 */ 317 } 318 319 void 320 mach_init_memory(u_quad_t memsize) 321 { 322 extern char kernel_text[]; 323 extern char end[]; 324 325 physmem = btoc(memsize); 326 327 if (memsize <= 256 * 1024 * 1024) { 328 mem_clusters[0].start = 0; 329 mem_clusters[0].size = memsize; 330 mem_cluster_cnt = 1; 331 } else if (memsize <= 512 * 1024 * 1024) { 332 mem_clusters[0].start = 0; 333 mem_clusters[0].size = 256 * 1024 * 1024; 334 mem_clusters[1].start = 0x410000000ULL; 335 mem_clusters[1].size = memsize - 256 * 1024 * 1024; 336 mem_cluster_cnt = 2; 337 } else { 338 mem_clusters[0].start = 0; 339 mem_clusters[0].size = 256 * 1024 * 1024; 340 mem_clusters[1].start = 0x20000000; 341 mem_clusters[1].size = memsize - 512 * 1024 * 1024; 342 mem_clusters[2].start = 0x410000000ULL; 343 mem_clusters[2].size = 256 * 1024 * 1024; 344 mem_cluster_cnt = 3; 345 } 346 347 348 #ifdef MULTIPROCESSOR 349 const u_int cores = mipsNN_cp0_ebase_read() & MIPS_EBASE_CPUNUM; 350 mem_clusters[0].start = cores * 4096; 351 #endif 352 353 /* 354 * Load the rest of the available pages into the VM system. 355 */ 356 mips_page_physload(mips_trunc_page(kernel_text), mips_round_page(end), 357 mem_clusters, mem_cluster_cnt, NULL, 0); 358 359 /* 360 * Initialize error message buffer (at end of core). 361 */ 362 mips_init_msgbuf(); 363 364 pmap_bootstrap(); 365 } 366 367 /* 368 * cpu_startup 369 * cpu_reboot 370 */ 371 372 int waittime = -1; 373 374 /* 375 * Allocate memory for variable-sized tables, 376 */ 377 void 378 cpu_startup(void) 379 { 380 #ifdef MULTIPROCESSOR 381 // Create a kcpuset so we can see on which CPUs the kernel was started. 382 kcpuset_create(&cpus_booted, true); 383 #endif 384 385 /* 386 * Do the common startup items. 387 */ 388 cpu_startup_common(); 389 390 /* 391 * Virtual memory is bootstrapped -- notify the bus spaces 392 * that memory allocation is now safe. 393 */ 394 octeon_configuration.mc_mallocsafe = 1; 395 } 396 397 void 398 cpu_reboot(int howto, char *bootstr) 399 { 400 401 /* Take a snapshot before clobbering any registers. */ 402 savectx(curpcb); 403 404 if (cold) { 405 howto |= RB_HALT; 406 goto haltsys; 407 } 408 409 /* If "always halt" was specified as a boot flag, obey. */ 410 if (boothowto & RB_HALT) 411 howto |= RB_HALT; 412 413 boothowto = howto; 414 if ((howto & RB_NOSYNC) == 0 && (waittime < 0)) { 415 waittime = 0; 416 vfs_shutdown(); 417 418 /* 419 * If we've been adjusting the clock, the todr 420 * will be out of synch; adjust it now. 421 */ 422 resettodr(); 423 } 424 425 splhigh(); 426 427 if (howto & RB_DUMP) 428 dumpsys(); 429 430 haltsys: 431 doshutdownhooks(); 432 433 if (howto & RB_HALT) { 434 printf("\n"); 435 printf("The operating system has halted.\n"); 436 printf("Please press any key to reboot.\n\n"); 437 } 438 439 printf("%s\n\n", ((howto & RB_HALT) != 0) ? "halted." : "rebooting..."); 440 441 /* 442 * Need a small delay here, otherwise we see the first few characters of 443 * the warning below. 444 */ 445 delay(80000); 446 447 /* initiate chip soft-reset */ 448 uint64_t fuse = octeon_read_csr(CIU_FUSE); 449 octeon_write_csr(CIU_SOFT_BIST, fuse); 450 octeon_read_csr(CIU_SOFT_RST); 451 octeon_write_csr(CIU_SOFT_RST, fuse); 452 453 delay(1000000); 454 455 printf("WARNING: reset failed!\nSpinning..."); 456 457 for (;;) 458 /* spin forever */ ; /* XXX */ 459 } 460
Indexes created Wed Oct 01 18:09:54 GMT 2025