machdep.c revision 1.9
1 /* $NetBSD: machdep.c,v 1.9 2016/12/22 14:47:56 cherry Exp $ */ 2 3 /* 4 * Copyright 2001, 2002 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Jason R. Thorpe and Simon Burge for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 /* 39 * Copyright (c) 1992, 1993 40 * The Regents of the University of California. All rights reserved. 41 * 42 * This code is derived from software contributed to Berkeley by 43 * the Systems Programming Group of the University of Utah Computer 44 * Science Department, The Mach Operating System project at 45 * Carnegie-Mellon University and Ralph Campbell. 46 * 47 * Redistribution and use in source and binary forms, with or without 48 * modification, are permitted provided that the following conditions 49 * are met: 50 * 1. Redistributions of source code must retain the above copyright 51 * notice, this list of conditions and the following disclaimer. 52 * 2. Redistributions in binary form must reproduce the above copyright 53 * notice, this list of conditions and the following disclaimer in the 54 * documentation and/or other materials provided with the distribution. 55 * 3. Neither the name of the University nor the names of its contributors 56 * may be used to endorse or promote products derived from this software 57 * without specific prior written permission. 58 * 59 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 60 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 61 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 62 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 63 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 64 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 65 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 66 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 67 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 68 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 69 * SUCH DAMAGE. 70 * 71 * @(#)machdep.c 8.3 (Berkeley) 1/12/94 72 * from: Utah Hdr: machdep.c 1.63 91/04/24 73 */ 74 /* 75 * Copyright (c) 1988 University of Utah. 76 * 77 * This code is derived from software contributed to Berkeley by 78 * the Systems Programming Group of the University of Utah Computer 79 * Science Department, The Mach Operating System project at 80 * Carnegie-Mellon University and Ralph Campbell. 81 * 82 * Redistribution and use in source and binary forms, with or without 83 * modification, are permitted provided that the following conditions 84 * are met: 85 * 1. Redistributions of source code must retain the above copyright 86 * notice, this list of conditions and the following disclaimer. 87 * 2. Redistributions in binary form must reproduce the above copyright 88 * notice, this list of conditions and the following disclaimer in the 89 * documentation and/or other materials provided with the distribution. 90 * 3. All advertising materials mentioning features or use of this software 91 * must display the following acknowledgement: 92 * This product includes software developed by the University of 93 * California, Berkeley and its contributors. 94 * 4. Neither the name of the University nor the names of its contributors 95 * may be used to endorse or promote products derived from this software 96 * without specific prior written permission. 97 * 98 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 99 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 100 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 101 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 102 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 103 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 104 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 105 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 106 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 107 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 108 * SUCH DAMAGE. 109 * 110 * @(#)machdep.c 8.3 (Berkeley) 1/12/94 111 * from: Utah Hdr: machdep.c 1.63 91/04/24 112 */ 113 114 #include "opt_multiprocessor.h" 115 116 #include <sys/cdefs.h> 117 __KERNEL_RCSID(0, "$NetBSD: machdep.c,v 1.9 2016/12/22 14:47:56 cherry Exp $"); 118 119 #include <sys/param.h> 120 #include <sys/systm.h> 121 #include <sys/kernel.h> 122 #include <sys/buf.h> 123 #include <sys/cpu.h> 124 #include <sys/reboot.h> 125 #include <sys/mount.h> 126 #include <sys/kcore.h> 127 #include <sys/boot_flag.h> 128 #include <sys/termios.h> 129 #include <sys/ksyms.h> 130 131 #include <uvm/uvm_extern.h> 132 133 #include <dev/cons.h> 134 135 #include "ksyms.h" 136 137 #if NKSYMS || defined(DDB) || defined(LKM) 138 #include <machine/db_machdep.h> 139 #include <ddb/db_extern.h> 140 #endif 141 142 #include <machine/psl.h> 143 #include <machine/locore.h> 144 145 #include <mips/cavium/autoconf.h> 146 #include <mips/cavium/octeonvar.h> 147 #include <mips/cavium/include/iobusvar.h> 148 #include <mips/cavium/include/bootbusvar.h> 149 150 #include <mips/cavium/dev/octeon_uartreg.h> 151 #include <mips/cavium/dev/octeon_ciureg.h> 152 #include <mips/cavium/dev/octeon_gpioreg.h> 153 154 #include <evbmips/cavium/octeon_uboot.h> 155 156 static void mach_init_bss(void); 157 static void mach_init_vector(void); 158 static void mach_init_bus_space(void); 159 static void mach_init_console(void); 160 static void mach_init_memory(u_quad_t); 161 162 #include "com.h" 163 #if NCOM > 0 164 #include <dev/ic/comreg.h> 165 #include <dev/ic/comvar.h> 166 int comcnrate = 115200; /* XXX should be config option */ 167 #endif /* NCOM > 0 */ 168 169 /* Maps for VM objects. */ 170 struct vm_map *phys_map = NULL; 171 172 int netboot; 173 174 phys_ram_seg_t mem_clusters[VM_PHYSSEG_MAX]; 175 int mem_cluster_cnt; 176 177 void mach_init(uint64_t, uint64_t, uint64_t, uint64_t); 178 179 struct octeon_config octeon_configuration; 180 struct octeon_btinfo octeon_btinfo; 181 182 char octeon_nmi_stack[PAGE_SIZE] __section(".data1") __aligned(PAGE_SIZE); 183 184 /* 185 * Do all the stuff that locore normally does before calling main(). 186 */ 187 void 188 mach_init(uint64_t arg0, uint64_t arg1, uint64_t arg2, uint64_t arg3) 189 { 190 uint64_t btinfo_paddr; 191 u_quad_t memsize; 192 int corefreq; 193 194 mach_init_bss(); 195 196 KASSERT(MIPS_XKPHYS_P(arg3)); 197 btinfo_paddr = mips3_ld(arg3 + OCTEON_BTINFO_PADDR_OFFSET); 198 199 /* Should be in first 256MB segment */ 200 KASSERT(btinfo_paddr < 256 * 1024 * 1024); 201 memcpy(&octeon_btinfo, 202 (struct octeon_btinfo *)MIPS_PHYS_TO_KSEG0(btinfo_paddr), 203 sizeof(octeon_btinfo)); 204 205 corefreq = octeon_btinfo.obt_eclock_hz; 206 memsize = octeon_btinfo.obt_dram_size * 1024 * 1024; 207 208 octeon_cal_timer(corefreq); 209 210 switch (MIPS_PRID_IMPL(mips_options.mips_cpu_id)) { 211 case 0: cpu_setmodel("Cavium Octeon CN38XX/CN36XX"); break; 212 case 1: cpu_setmodel("Cavium Octeon CN31XX/CN3020"); break; 213 case 2: cpu_setmodel("Cavium Octeon CN3005/CN3010"); break; 214 case 3: cpu_setmodel("Cavium Octeon CN58XX"); break; 215 case 4: cpu_setmodel("Cavium Octeon CN5[4-7]XX"); break; 216 case 6: cpu_setmodel("Cavium Octeon CN50XX"); break; 217 case 7: cpu_setmodel("Cavium Octeon CN52XX"); break; 218 default: cpu_setmodel("Cavium Octeon"); break; 219 } 220 221 mach_init_vector(); 222 223 uvm_md_init(); 224 225 mach_init_bus_space(); 226 227 mach_init_console(); 228 229 mach_init_memory(memsize); 230 231 /* 232 * Allocate uarea page for lwp0 and set it. 233 */ 234 mips_init_lwp0_uarea(); 235 236 boothowto = RB_AUTOBOOT; 237 boothowto |= AB_VERBOSE; 238 239 #if 0 240 curcpu()->ci_nmi_stack = octeon_nmi_stack + sizeof(octeon_nmi_stack) - sizeof(struct kernframe); 241 *(uint64_t *)MIPS_PHYS_TO_KSEG0(0x800) = (intptr_t)octeon_reset_vector; 242 const uint64_t wdog_reg = MIPS_PHYS_TO_XKPHYS_UNCACHED(CIU_WDOG0); 243 uint64_t wdog = mips3_ld(wdog_reg); 244 wdog &= ~(CIU_WDOGX_MODE|CIU_WDOGX_LEN); 245 wdog |= __SHIFTIN(3, CIU_WDOGX_MODE); 246 wdog |= CIU_WDOGX_LEN; // max period 247 mips64_sd_a64(wdog_reg, wdog); 248 printf("Watchdog enabled!\n"); 249 #endif 250 251 #if defined(DDB) 252 if (boothowto & RB_KDB) 253 Debugger(); 254 #endif 255 } 256 257 void 258 consinit(void) 259 { 260 261 /* 262 * Everything related to console initialization is done 263 * in mach_init(). 264 */ 265 } 266 267 void 268 mach_init_bss(void) 269 { 270 extern char edata[], end[]; 271 272 /* 273 * Clear the BSS segment. 274 */ 275 memset(edata, 0, mips_round_page(end) - (uintptr_t)edata); 276 } 277 278 void 279 mach_init_vector(void) 280 { 281 282 /* Make sure exception base at 0 (MIPS_COP_0_EBASE) */ 283 __asm __volatile("mtc0 %0, $15, 1" : : "r"(0x80000000) ); 284 285 /* 286 * Set up the exception vectors and CPU-specific function 287 * vectors early on. We need the wbflush() vector set up 288 * before comcnattach() is called (or at least before the 289 * first printf() after that is called). 290 * Also clears the I+D caches. 291 */ 292 mips_vector_init(NULL, true); 293 } 294 295 void 296 mach_init_bus_space(void) 297 { 298 struct octeon_config *mcp = &octeon_configuration; 299 300 octeon_dma_init(mcp); 301 302 iobus_bootstrap(mcp); 303 bootbus_bootstrap(mcp); 304 } 305 306 void 307 mach_init_console(void) 308 { 309 #if NCOM > 0 310 struct octeon_config *mcp = &octeon_configuration; 311 int status; 312 extern int octeon_uart_com_cnattach(bus_space_tag_t, int, int); 313 314 /* 315 * Delay to allow firmware putchars to complete. 316 * FIFO depth * character time. 317 * character time = (1000000 / (defaultrate / 10)) 318 */ 319 delay(640000000 / comcnrate); 320 321 status = octeon_uart_com_cnattach( 322 &mcp->mc_iobus_bust, 323 0, /* XXX port 0 */ 324 comcnrate); 325 if (status != 0) 326 panic("can't initialize console!"); /* XXX print to nowhere! */ 327 #else 328 panic("octeon: not configured to use serial console"); 329 #endif /* NCOM > 0 */ 330 } 331 332 void 333 mach_init_memory(u_quad_t memsize) 334 { 335 extern char kernel_text[]; 336 extern char end[]; 337 338 physmem = btoc(memsize); 339 340 if (memsize <= 256 * 1024 * 1024) { 341 mem_clusters[0].start = 0; 342 mem_clusters[0].size = memsize; 343 mem_cluster_cnt = 1; 344 } else if (memsize <= 512 * 1024 * 1024) { 345 mem_clusters[0].start = 0; 346 mem_clusters[0].size = 256 * 1024 * 1024; 347 mem_clusters[1].start = 0x410000000ULL; 348 mem_clusters[1].size = memsize - 256 * 1024 * 1024; 349 mem_cluster_cnt = 2; 350 } else { 351 mem_clusters[0].start = 0; 352 mem_clusters[0].size = 256 * 1024 * 1024; 353 mem_clusters[1].start = 0x20000000; 354 mem_clusters[1].size = memsize - 512 * 1024 * 1024; 355 mem_clusters[2].start = 0x410000000ULL; 356 mem_clusters[2].size = 256 * 1024 * 1024; 357 mem_cluster_cnt = 3; 358 } 359 360 361 #ifdef MULTIPROCESSOR 362 const u_int cores = mipsNN_cp0_ebase_read() & MIPS_EBASE_CPUNUM; 363 mem_clusters[0].start = cores * 4096; 364 #endif 365 366 /* 367 * Load the rest of the available pages into the VM system. 368 */ 369 mips_page_physload(mips_trunc_page(kernel_text), mips_round_page(end), 370 mem_clusters, mem_cluster_cnt, NULL, 0); 371 372 /* 373 * Initialize error message buffer (at end of core). 374 */ 375 mips_init_msgbuf(); 376 377 pmap_bootstrap(); 378 } 379 380 /* 381 * cpu_startup 382 * cpu_reboot 383 */ 384 385 int waittime = -1; 386 387 /* 388 * Allocate memory for variable-sized tables, 389 */ 390 void 391 cpu_startup(void) 392 { 393 #ifdef MULTIPROCESSOR 394 // Create a kcpuset so we can see on which CPUs the kernel was started. 395 kcpuset_create(&cpus_booted, true); 396 #endif 397 398 /* 399 * Do the common startup items. 400 */ 401 cpu_startup_common(); 402 403 /* 404 * Virtual memory is bootstrapped -- notify the bus spaces 405 * that memory allocation is now safe. 406 */ 407 octeon_configuration.mc_mallocsafe = 1; 408 } 409 410 void 411 cpu_reboot(int howto, char *bootstr) 412 { 413 414 /* Take a snapshot before clobbering any registers. */ 415 savectx(curpcb); 416 417 if (cold) { 418 howto |= RB_HALT; 419 goto haltsys; 420 } 421 422 /* If "always halt" was specified as a boot flag, obey. */ 423 if (boothowto & RB_HALT) 424 howto |= RB_HALT; 425 426 boothowto = howto; 427 if ((howto & RB_NOSYNC) == 0 && (waittime < 0)) { 428 waittime = 0; 429 vfs_shutdown(); 430 431 /* 432 * If we've been adjusting the clock, the todr 433 * will be out of synch; adjust it now. 434 */ 435 resettodr(); 436 } 437 438 splhigh(); 439 440 if (howto & RB_DUMP) 441 dumpsys(); 442 443 haltsys: 444 doshutdownhooks(); 445 446 if (howto & RB_HALT) { 447 printf("\n"); 448 printf("The operating system has halted.\n"); 449 printf("Please press any key to reboot.\n\n"); 450 cnpollc(1); /* For proper keyboard command handling */ 451 cngetc(); 452 cnpollc(0); 453 } 454 455 printf("%s\n\n", ((howto & RB_HALT) != 0) ? "halted." : "rebooting..."); 456 457 /* 458 * Need a small delay here, otherwise we see the first few characters of 459 * the warning below. 460 */ 461 delay(80000); 462 463 /* initiate chip soft-reset */ 464 uint64_t fuse = octeon_read_csr(CIU_FUSE); 465 octeon_write_csr(CIU_SOFT_BIST, fuse); 466 octeon_read_csr(CIU_SOFT_RST); 467 octeon_write_csr(CIU_SOFT_RST, fuse); 468 469 delay(1000000); 470 471 printf("WARNING: reset failed!\nSpinning..."); 472 473 for (;;) 474 /* spin forever */ ; /* XXX */ 475 } 476
Indexes created Wed Oct 01 13:09:50 GMT 2025