OMSAL400 revision 1.4
1 1.4 shige # $NetBSD: OMSAL400,v 1.4 2006/03/28 16:56:50 shige Exp $ 2 1.1 shige # 3 1.1 shige # Kernel config for the Open Micro Server AL400. 4 1.1 shige 5 1.1 shige include "arch/evbmips/conf/ALCHEMY" 6 1.1 shige 7 1.1 shige no options ALCHEMY_AU1000 8 1.1 shige no options ALCHEMY_AU1100 9 1.1 shige no options ALCHEMY_AU1500 10 1.1 shige no options ALCHEMY_AU1550 11 1.1 shige no options ALCHEMY_GENERIC 12 1.1 shige 13 1.1 shige # configure out local board support 14 1.1 shige makeoptions TEXTADDR="0x80100000" 15 1.1 shige options ALCHEMY_AU1550 16 1.1 shige options ALCHEMY_OMSAL400 17 1.1 shige options PCI_NETBSD_CONFIGURE 18 1.1 shige 19 1.4 shige # OMS-AL400 doesn't use aurtc. 20 1.4 shige no aurtc* at aubus? 21 1.4 shige 22 1.3 shige # Alchemy On-chip Programmable Serial Controllers 23 1.3 shige aupsc* at aubus? addr ? 24 1.1 shige 25 1.3 shige # SMBus 26 1.3 shige ausmbus0 at aupsc0 27 1.3 shige iic0 at ausmbus0 28 1.3 shige r2025rtc* at iic0 addr 0x32 # R2025S RTC 29 1.3 shige seeprom* at iic0 addr 0x50 size 4096 # Serial EEPROM AT24C04 30 1.3 shige 31 1.3 shige # Alchemy On-chip PCI 32 1.3 shige aupci* at aubus? addr ? 33 1.3 shige pci* at aupci? 34 1.1 shige 35 1.1 shige # PCI devices 36 1.1 shige wm* at pci? dev ? function ? # Intel 8254x gigabit 37 1.1 shige ehci* at pci? dev ? function ? # Enhanced Host Controller 38 1.1 shige ohci* at pci? dev ? function ? # Open Host Controller 39 1.1 shige 40 1.1 shige # MII 41 1.1 shige lxtphy* at mii? phy ? # Level One LXT-970 PHYs 42 1.1 shige igphy* at mii? phy ? # Intel IGP01E1000 43 1.1 shige 44 1.1 shige # USB 45 1.1 shige usb* at ohci? 46 1.1 shige usb* at ehci? 47
Indexes created Tue Oct 27 00:25:24 UTC 2026