gdium_intr.c revision 1.2.6.1
1 /* $NetBSD: gdium_intr.c,v 1.2.6.1 2011/06/12 00:23:56 rmind Exp $ */ 2 3 /*- 4 * Copyright (c) 2001 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Platform-specific interrupt support for the Algorithmics P-6032. 34 * 35 * The Algorithmics P-6032's interrupts are wired to GPIO pins 36 * on the BONITO system controller. 37 */ 38 39 #include <sys/cdefs.h> 40 __KERNEL_RCSID(0, "$NetBSD: gdium_intr.c,v 1.2.6.1 2011/06/12 00:23:56 rmind Exp $"); 41 42 #define __INTR_PRIVATE 43 44 45 #include "opt_ddb.h" 46 47 #include <sys/param.h> 48 #include <sys/queue.h> 49 #include <sys/malloc.h> 50 #include <sys/systm.h> 51 #include <sys/device.h> 52 #include <sys/kernel.h> 53 #include <sys/cpu.h> 54 55 #include <machine/bus.h> 56 #include <machine/intr.h> 57 58 #include <mips/locore.h> 59 60 #include <mips/bonito/bonitoreg.h> 61 #include <evbmips/gdium/gdiumvar.h> 62 63 #include <dev/pci/pcireg.h> 64 #include <dev/pci/pcivar.h> 65 66 /* 67 * The GDIUM interrupts are wired up in the following way: 68 * 69 * GPIN0 ISA_NMI (in) 70 * GPIN1 ISA_INTR (in) 71 * GPIN2 ETH_INT~ (in) 72 * GPIN3 BONIDE_INT (in) 73 * 74 * PCI_INTA 75 * GPIN4 ISA IRQ3 (in, also on piix4) 76 * GPIN5 ISA IRQ4 (in, also on piix4) 77 * 78 * GPIO0 PIRQ A~ (in) 79 * GPIO1 PIRQ B~ (in) 80 * GPIO2 PIRQ C~ (in) 81 * GPIO3 PIRQ D~ (in) 82 */ 83 84 struct gdium_irqmap { 85 const char *name; 86 uint8_t irqidx; 87 uint8_t flags; 88 }; 89 90 #define IRQ_F_INVERT 0x80 /* invert polarity */ 91 #define IRQ_F_EDGE 0x40 /* edge trigger */ 92 #define IRQ_F_INT0 0x00 /* INT0 */ 93 #define IRQ_F_INT1 0x01 /* INT1 */ 94 #define IRQ_F_INT2 0x02 /* INT2 */ 95 #define IRQ_F_INT3 0x03 /* INT3 */ 96 #define IRQ_F_INTMASK 0x07 /* INT mask */ 97 98 const struct gdium_irqmap gdium_irqmap[] = { 99 { "gpio0", GDIUM_IRQ_GPIO0, IRQ_F_INT0 }, 100 { "gpio1", GDIUM_IRQ_GPIO1, IRQ_F_INT0 }, 101 { "gpio2", GDIUM_IRQ_GPIO2, IRQ_F_INT0 }, 102 { "gpio3", GDIUM_IRQ_GPIO3, IRQ_F_INT0 }, 103 104 { "pci inta", GDIUM_IRQ_PCI_INTA, IRQ_F_INT0 }, 105 { "pci intb", GDIUM_IRQ_PCI_INTB, IRQ_F_INT0 }, 106 { "pci intc", GDIUM_IRQ_PCI_INTC, IRQ_F_INT0 }, 107 { "pci intd", GDIUM_IRQ_PCI_INTD, IRQ_F_INT0 }, 108 109 { "pci perr", GDIUM_IRQ_PCI_PERR, IRQ_F_EDGE|IRQ_F_INT1 }, 110 { "pci serr", GDIUM_IRQ_PCI_SERR, IRQ_F_EDGE|IRQ_F_INT1 }, 111 112 { "denali", GDIUM_IRQ_DENALI, IRQ_F_INT1 }, 113 114 { "mips int0", GDIUM_IRQ_INT0, IRQ_F_INT0 }, 115 { "mips int1", GDIUM_IRQ_INT1, IRQ_F_INT1 }, 116 { "mips int2", GDIUM_IRQ_INT2, IRQ_F_INT2 }, 117 { "mips int3", GDIUM_IRQ_INT3, IRQ_F_INT3 }, 118 }; 119 120 struct gdium_intrhead { 121 struct evcnt intr_count; 122 int intr_refcnt; 123 }; 124 struct gdium_intrhead gdium_intrtab[__arraycount(gdium_irqmap)]; 125 126 #define NINTRS 2 /* MIPS INT0 - INT1 */ 127 128 struct gdium_cpuintr { 129 LIST_HEAD(, evbmips_intrhand) cintr_list; 130 struct evcnt cintr_count; 131 int cintr_refcnt; 132 }; 133 134 struct gdium_cpuintr gdium_cpuintrs[NINTRS]; 135 const char * const gdium_cpuintrnames[NINTRS] = { 136 "int 0 (pci)", 137 "int 1 (errors)", 138 }; 139 140 /* 141 * This is a mask of bits to clear in the SR when we go to a 142 * given hardware interrupt priority level. 143 */ 144 static const struct ipl_sr_map gdium_ipl_sr_map = { 145 .sr_bits = { 146 [IPL_NONE] = 0, 147 [IPL_SOFTCLOCK] = MIPS_SOFT_INT_MASK_0, 148 [IPL_SOFTNET] = MIPS_SOFT_INT_MASK_0 | MIPS_SOFT_INT_MASK_1, 149 [IPL_VM] = 150 MIPS_SOFT_INT_MASK_0 | MIPS_SOFT_INT_MASK_1 | 151 MIPS_INT_MASK_0 | 152 MIPS_INT_MASK_1 | 153 MIPS_INT_MASK_2 | 154 MIPS_INT_MASK_3 | 155 MIPS_INT_MASK_4, 156 [IPL_SCHED] = 157 MIPS_SOFT_INT_MASK_0 | MIPS_SOFT_INT_MASK_1 | 158 MIPS_INT_MASK_0 | 159 MIPS_INT_MASK_1 | 160 MIPS_INT_MASK_2 | 161 MIPS_INT_MASK_3 | 162 MIPS_INT_MASK_4 | 163 MIPS_INT_MASK_5, 164 [IPL_DDB] = MIPS_INT_MASK, 165 [IPL_HIGH] = MIPS_INT_MASK, 166 }, 167 }; 168 169 int gdium_pci_intr_map(const struct pci_attach_args *, pci_intr_handle_t *); 170 const char *gdium_pci_intr_string(void *, pci_intr_handle_t); 171 const struct evcnt *gdium_pci_intr_evcnt(void *, pci_intr_handle_t); 172 void *gdium_pci_intr_establish(void *, pci_intr_handle_t, int, 173 int (*)(void *), void *); 174 void gdium_pci_intr_disestablish(void *, void *); 175 void gdium_pci_conf_interrupt(void *, int, int, int, int, int *); 176 177 void 178 evbmips_intr_init(void) 179 { 180 struct gdium_config * const gc = &gdium_configuration; 181 struct bonito_config *bc = &gc->gc_bonito; 182 const struct gdium_irqmap *irqmap; 183 uint32_t intbit; 184 size_t i; 185 186 ipl_sr_map = gdium_ipl_sr_map; 187 188 for (i = 0; i < NINTRS; i++) { 189 LIST_INIT(&gdium_cpuintrs[i].cintr_list); 190 evcnt_attach_dynamic(&gdium_cpuintrs[i].cintr_count, 191 EVCNT_TYPE_INTR, NULL, "mips", gdium_cpuintrnames[i]); 192 } 193 //evcnt_attach_static(&mips_int5_evcnt); 194 195 for (i = 0; i < __arraycount(gdium_irqmap); i++) { 196 irqmap = &gdium_irqmap[i]; 197 intbit = 1 << irqmap->irqidx; 198 199 evcnt_attach_dynamic(&gdium_intrtab[i].intr_count, 200 EVCNT_TYPE_INTR, NULL, "bonito", irqmap->name); 201 202 if (irqmap->irqidx < 4) 203 bc->bc_gpioIE |= intbit; 204 if (irqmap->flags & IRQ_F_INVERT) 205 bc->bc_intPol |= intbit; 206 if (irqmap->flags & IRQ_F_EDGE) 207 bc->bc_intEdge |= intbit; 208 if ((irqmap->flags & IRQ_F_INTMASK) == IRQ_F_INT1) 209 bc->bc_intSteer |= intbit; 210 211 REGVAL(BONITO_INTENCLR) = intbit; 212 } 213 214 REGVAL(BONITO_GPIOIE) = bc->bc_gpioIE; 215 REGVAL(BONITO_INTEDGE) = bc->bc_intEdge; 216 REGVAL(BONITO_INTSTEER) = bc->bc_intSteer; 217 REGVAL(BONITO_INTPOL) = bc->bc_intPol; 218 219 gc->gc_pc.pc_intr_v = NULL; 220 gc->gc_pc.pc_intr_map = gdium_pci_intr_map; 221 gc->gc_pc.pc_intr_string = gdium_pci_intr_string; 222 gc->gc_pc.pc_intr_evcnt = gdium_pci_intr_evcnt; 223 gc->gc_pc.pc_intr_establish = gdium_pci_intr_establish; 224 gc->gc_pc.pc_intr_disestablish = gdium_pci_intr_disestablish; 225 gc->gc_pc.pc_conf_interrupt = gdium_pci_conf_interrupt; 226 227 /* We let the PCI-ISA bridge code handle this. */ 228 gc->gc_pc.pc_pciide_compat_intr_establish = NULL; 229 } 230 231 void * 232 evbmips_intr_establish(int irq, int (*func)(void *), void *arg) 233 { 234 const struct gdium_irqmap *irqmap; 235 struct evbmips_intrhand *ih; 236 int level; 237 int s; 238 239 irqmap = &gdium_irqmap[irq]; 240 KASSERT(irq < __arraycount(gdium_irqmap)); 241 242 KASSERT(irq == irqmap->irqidx); 243 244 ih = malloc(sizeof(*ih), M_DEVBUF, M_NOWAIT|M_ZERO); 245 if (ih == NULL) 246 return NULL; 247 248 ih->ih_func = func; 249 ih->ih_arg = arg; 250 ih->ih_irq = irq; 251 252 s = splhigh(); 253 254 /* 255 * First, link it into the tables. 256 */ 257 level = (irqmap->flags & IRQ_F_INT1) != 0; 258 LIST_INSERT_HEAD(&gdium_cpuintrs[level].cintr_list, ih, ih_q); 259 gdium_cpuintrs[level].cintr_refcnt++; 260 261 /* 262 * Now enable it. 263 */ 264 if (gdium_intrtab[ih->ih_irq].intr_refcnt++ == 0) 265 REGVAL(BONITO_INTENSET) = (1 << ih->ih_irq); 266 267 splx(s); 268 269 return (ih); 270 } 271 272 void 273 evbmips_intr_disestablish(void *cookie) 274 { 275 const struct gdium_irqmap *irqmap; 276 struct evbmips_intrhand *ih = cookie; 277 int s; 278 279 irqmap = &gdium_irqmap[ih->ih_irq]; 280 281 s = splhigh(); 282 283 /* 284 * First, remove it from the table. 285 */ 286 LIST_REMOVE(ih, ih_q); 287 gdium_cpuintrs[(irqmap->flags & IRQ_F_INT1) != 0].cintr_refcnt--; 288 289 /* 290 * Now, disable it, if there is nothing remaining on the 291 * list. 292 */ 293 if (gdium_intrtab[ih->ih_irq].intr_refcnt-- == 1) 294 REGVAL(BONITO_INTENCLR) = (1 << ih->ih_irq); 295 296 splx(s); 297 298 free(ih, M_DEVBUF); 299 } 300 301 void 302 evbmips_iointr(int ipl, vaddr_t pc, uint32_t ipending) 303 { 304 const struct gdium_irqmap *irqmap; 305 struct evbmips_intrhand *ih; 306 int level; 307 uint32_t isr; 308 309 /* 310 * Read the interrupt pending registers, mask them with the 311 * ones we have enabled, and service them in order of decreasing 312 * priority. 313 */ 314 isr = REGVAL(BONITO_INTISR) & REGVAL(BONITO_INTEN); 315 for (level = 1; level >= 0; level--) { 316 if ((ipending & (MIPS_INT_MASK_4 << level)) == 0) 317 continue; 318 gdium_cpuintrs[level].cintr_count.ev_count++; 319 LIST_FOREACH (ih, &gdium_cpuintrs[level].cintr_list, ih_q) { 320 irqmap = &gdium_irqmap[ih->ih_irq]; 321 if (isr & (1 << ih->ih_irq)) { 322 gdium_intrtab[ih->ih_irq].intr_count.ev_count++; 323 (*ih->ih_func)(ih->ih_arg); 324 } 325 } 326 } 327 } 328 329 /***************************************************************************** 330 * PCI interrupt support 331 *****************************************************************************/ 332 333 int 334 gdium_pci_intr_map(const struct pci_attach_args *pa, 335 pci_intr_handle_t *ihp) 336 { 337 static const int8_t pciirqmap[5/*device*/] = { 338 GDIUM_IRQ_PCI_INTC, /* 13: PCI 802.11 */ 339 GDIUM_IRQ_PCI_INTA, /* 14: SM501 */ 340 GDIUM_IRQ_PCI_INTB, /* 15: NEC USB (2 func) */ 341 GDIUM_IRQ_PCI_INTD, /* 16: Ethernet */ 342 GDIUM_IRQ_PCI_INTC, /* 17: NEC USB (2 func) */ 343 }; 344 pcitag_t bustag = pa->pa_intrtag; 345 int buspin = pa->pa_intrpin; 346 pci_chipset_tag_t pc = pa->pa_pc; 347 int device; 348 349 if (buspin == 0) { 350 /* No IRQ used. */ 351 return (1); 352 } 353 354 if (buspin > 4) { 355 printf("gdium_pci_intr_map: bad interrupt pin %d\n", 356 buspin); 357 return (1); 358 } 359 360 pci_decompose_tag(pc, bustag, NULL, &device, NULL); 361 if (device < 13 || device > 17) { 362 printf("gdium_pci_intr_map: bad device %d\n", 363 device); 364 return (1); 365 } 366 367 *ihp = pciirqmap[device - 13]; 368 return (0); 369 } 370 371 const char * 372 gdium_pci_intr_string(void *v, pci_intr_handle_t ih) 373 { 374 375 if (ih >= __arraycount(gdium_irqmap)) 376 panic("gdium_intr_string: bogus IRQ %ld", ih); 377 378 return gdium_irqmap[ih].name; 379 } 380 381 const struct evcnt * 382 gdium_pci_intr_evcnt(void *v, pci_intr_handle_t ih) 383 { 384 385 return &gdium_intrtab[ih].intr_count; 386 } 387 388 void * 389 gdium_pci_intr_establish(void *v, pci_intr_handle_t ih, int level, 390 int (*func)(void *), void *arg) 391 { 392 393 if (ih >= __arraycount(gdium_irqmap)) 394 panic("gdium_pci_intr_establish: bogus IRQ %ld", ih); 395 396 return evbmips_intr_establish(ih, func, arg); 397 } 398 399 void 400 gdium_pci_intr_disestablish(void *v, void *cookie) 401 { 402 403 return (evbmips_intr_disestablish(cookie)); 404 } 405 406 void 407 gdium_pci_conf_interrupt(void *v, int bus, int dev, int pin, int swiz, 408 int *iline) 409 { 410 411 /* 412 * We actually don't need to do anything; everything is handled 413 * in pci_intr_map(). 414 */ 415 *iline = 0; 416 } 417
Indexes created Wed Oct 22 13:09:56 GMT 2025