cpu.c revision 1.1 
1/*	$NetBSD: cpu.c,v 1.1 2016/01/29 01:54:14 macallan Exp $	*/
2
3/*
4 * Copyright 2002 Wasabi Systems, Inc.
5 * All rights reserved.
6 *
7 * Written by Simon Burge for Wasabi Systems, Inc.
8 *
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
11 * are met:
12 * 1. Redistributions of source code must retain the above copyright
13 *    notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 *    notice, this list of conditions and the following disclaimer in the
16 *    documentation and/or other materials provided with the distribution.
17 * 3. All advertising materials mentioning features or use of this software
18 *    must display the following acknowledgement:
19 *      This product includes software developed for the NetBSD Project by
20 *      Wasabi Systems, Inc.
21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse
22 *    or promote products derived from this software without specific prior
23 *    written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
28 * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL WASABI SYSTEMS, INC
29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
35 * POSSIBILITY OF SUCH DAMAGE.
36 */
37
38#include <sys/cdefs.h>
39__KERNEL_RCSID(0, "$NetBSD: cpu.c,v 1.1 2016/01/29 01:54:14 macallan Exp $");
40
41#include <sys/param.h>
42#include <sys/device.h>
43#include <sys/systm.h>
44#include <sys/cpu.h>
45
46#include <mips/locore.h>
47#include <mips/asm.h>
48#include <mips/ingenic/ingenic_regs.h>
49
50#include "opt_ingenic.h"
51
52static int	cpu_match(device_t, cfdata_t, void *);
53static void	cpu_attach(device_t, device_t, void *);
54
55CFATTACH_DECL_NEW(cpu, 0,
56    cpu_match, cpu_attach, NULL, NULL);
57
58struct cpu_info *startup_cpu_info;
59extern void *ingenic_wakeup;
60
61static int
62cpu_match(device_t parent, cfdata_t match, void *aux)
63{
64	struct mainbusdev {
65		const char *md_name;
66	} *aa = aux;
67	if (strcmp(aa->md_name, "cpu") == 0) return 1;
68	return 0;
69}
70
71static void
72cpu_attach(device_t parent, device_t self, void *aux)
73{
74	struct cpu_info *ci = curcpu();
75	int unit;
76
77	if ((unit = device_unit(self)) > 0) {
78#ifdef MULTIPROCESSOR
79		uint32_t vec, reg;
80		int bail = 10000;
81
82		startup_cpu_info = cpu_info_alloc(NULL, unit, 0, unit, 0);
83		startup_cpu_info->ci_cpu_freq = ci->ci_cpu_freq;
84		ci = startup_cpu_info;
85		wbflush();
86		vec = (uint32_t)&ingenic_wakeup;
87		reg = MFC0(12, 4);	/* reset entry reg */
88		reg &= ~REIM_ENTRY_M;
89		reg |= vec;
90		MTC0(reg, 12, 4);
91		reg = MFC0(12, 2);	/* core control reg */
92		reg |= CC_RPC1;		/* use our exception vector */
93		reg &= ~CC_SW_RST1;	/* get core 1 out of reset */
94		MTC0(reg, 12, 2);
95		while ((!kcpuset_isset(cpus_hatched, cpu_index(startup_cpu_info))) && (bail > 0)) {
96			delay(1000);
97			bail--;
98		}
99		if (!kcpuset_isset(cpus_hatched, cpu_index(startup_cpu_info))) {
100			aprint_error_dev(self, "did not hatch\n");
101			return;
102		}
103#else
104		aprint_normal_dev(self,
105		    "processor off-line; "
106		    "multiprocessor support not present in kernel\n");
107		return;
108#endif
109
110	}
111	ci->ci_dev = self;
112	self->dv_private = ci;
113
114	aprint_normal(": %lu.%02luMHz (hz cycles = %lu, delay divisor = %lu)\n",
115	    ci->ci_cpu_freq / 1000000,
116	    (ci->ci_cpu_freq % 1000000) / 10000,
117	    ci->ci_cycles_per_hz, ci->ci_divisor_delay);
118
119	aprint_normal_dev(self, "");
120	cpu_identify(self);
121	cpu_attach_common(self, ci);
122}
123