intr.c revision 1.6
1 /* $NetBSD: intr.c,v 1.6 2015/03/07 15:37:46 macallan Exp $ */ 2 3 /*- 4 * Copyright (c) 2014 Michael Lorenz 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 17 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 * POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: intr.c,v 1.6 2015/03/07 15:37:46 macallan Exp $"); 31 32 #define __INTR_PRIVATE 33 34 #include <sys/param.h> 35 #include <sys/cpu.h> 36 #include <sys/device.h> 37 #include <sys/kernel.h> 38 #include <sys/systm.h> 39 #include <sys/timetc.h> 40 #include <sys/bitops.h> 41 42 #include <mips/locore.h> 43 #include <machine/intr.h> 44 45 #include <mips/ingenic/ingenic_regs.h> 46 47 #include "opt_ingenic.h" 48 49 extern void ingenic_clockintr(uint32_t); 50 extern void ingenic_puts(const char *); 51 52 /* 53 * This is a mask of bits to clear in the SR when we go to a 54 * given hardware interrupt priority level. 55 */ 56 static const struct ipl_sr_map ingenic_ipl_sr_map = { 57 .sr_bits = { 58 [IPL_NONE] = 0, 59 [IPL_SOFTCLOCK] = MIPS_SOFT_INT_MASK_0, 60 [IPL_SOFTNET] = MIPS_SOFT_INT_MASK_0 | MIPS_SOFT_INT_MASK_1, 61 [IPL_VM] = 62 MIPS_SOFT_INT_MASK_0 | MIPS_SOFT_INT_MASK_1 | 63 MIPS_INT_MASK_0 | 64 MIPS_INT_MASK_3 | 65 MIPS_INT_MASK_4 | 66 MIPS_INT_MASK_5, 67 [IPL_SCHED] = 68 MIPS_SOFT_INT_MASK_0 | MIPS_SOFT_INT_MASK_1 | 69 MIPS_INT_MASK_0 | 70 MIPS_INT_MASK_1 | 71 MIPS_INT_MASK_2 | 72 MIPS_INT_MASK_3 | 73 MIPS_INT_MASK_4 | 74 MIPS_INT_MASK_5, 75 [IPL_DDB] = MIPS_INT_MASK, 76 [IPL_HIGH] = MIPS_INT_MASK, 77 }, 78 }; 79 80 #define NINTR 64 81 82 /* some timer channels share interrupts, couldn't find any others */ 83 struct intrhand { 84 struct evcnt ih_count; 85 char ih_name[16]; 86 int (*ih_func)(void *); 87 void *ih_arg; 88 int ih_ipl; 89 }; 90 91 struct intrhand intrs[NINTR]; 92 93 void ingenic_irq(int); 94 95 void 96 evbmips_intr_init(void) 97 { 98 uint32_t reg; 99 int i; 100 101 ipl_sr_map = ingenic_ipl_sr_map; 102 103 /* zero all handlers */ 104 for (i = 0; i < NINTR; i++) { 105 intrs[i].ih_func = NULL; 106 intrs[i].ih_arg = NULL; 107 snprintf(intrs[i].ih_name, sizeof(intrs[i].ih_name), 108 "irq %d", i); 109 evcnt_attach_dynamic(&intrs[i].ih_count, EVCNT_TYPE_INTR, 110 NULL, "PIC", intrs[i].ih_name); 111 } 112 113 /* mask all peripheral IRQs */ 114 writereg(JZ_ICMR0, 0xffffffff); 115 writereg(JZ_ICMR1, 0xffffffff); 116 117 /* allow peripheral interrupts to core 0 only */ 118 reg = MFC0(12, 4); /* reset entry and interrupts */ 119 reg &= 0xffff0000; 120 reg |= REIM_IRQ0_M | REIM_MIRQ0_M | REIM_MIRQ1_M; 121 MTC0(reg, 12, 4); 122 } 123 124 void 125 evbmips_iointr(int ipl, vaddr_t pc, uint32_t ipending) 126 { 127 uint32_t id; 128 #ifdef INGENIC_INTR_DEBUG 129 char buffer[256]; 130 131 #if 0 132 snprintf(buffer, 256, "pending: %08x CR %08x\n", ipending, 133 MFC0(MIPS_COP_0_CAUSE, 0)); 134 ingenic_puts(buffer); 135 #endif 136 #endif 137 /* see which core we're on */ 138 id = MFC0(15, 1) & 7; 139 140 /* 141 * XXX 142 * the manual counts the softint bits as INT0 and INT1, out headers 143 * don't so everything here looks off by two 144 */ 145 if (ipending & MIPS_INT_MASK_1) { 146 /* 147 * this is a mailbox interrupt / IPI 148 * for now just print the message and clear it 149 */ 150 uint32_t reg; 151 152 /* read pending IPIs */ 153 reg = MFC0(12, 3); 154 if (id == 0) { 155 if (reg & CS_MIRQ0_P) { 156 157 #ifdef INGENIC_INTR_DEBUG 158 snprintf(buffer, 256, 159 "IPI for core 0, msg %08x\n", 160 MFC0(CP0_CORE_MBOX, 0)); 161 ingenic_puts(buffer); 162 #endif 163 reg &= (~CS_MIRQ0_P); 164 /* clear it */ 165 MTC0(reg, 12, 3); 166 } 167 } else if (id == 1) { 168 if (reg & CS_MIRQ1_P) { 169 #ifdef INGENIC_INTR_DEBUG 170 snprintf(buffer, 256, 171 "IPI for core 1, msg %08x\n", 172 MFC0(CP0_CORE_MBOX, 1)); 173 ingenic_puts(buffer); 174 #endif 175 reg &= ( 7 - CS_MIRQ1_P); 176 /* clear it */ 177 MTC0(reg, 12, 3); 178 } 179 } 180 } 181 if (ipending & MIPS_INT_MASK_2) { 182 /* this is a timer interrupt */ 183 ingenic_clockintr(id); 184 ingenic_puts("INT2\n"); 185 } 186 if (ipending & MIPS_INT_MASK_0) { 187 uint32_t mask; 188 /* peripheral interrupt */ 189 190 /* 191 * XXX 192 * OS timer interrupts are supposed to show up as INT2 as well 193 * but I haven't seen them there so for now we just weed them 194 * out right here. 195 * The idea is to allow peripheral interrupts on both cores but 196 * block INT0 on core1 so it would see only timer interrupts 197 * and IPIs. If that doesn't work we'll have to send an IPI to 198 * core1 for each timer tick. 199 */ 200 mask = readreg(JZ_ICPR0); 201 if (mask & 0x0c000000) { 202 writereg(JZ_ICMSR0, mask); 203 ingenic_clockintr(id); 204 writereg(JZ_ICMCR0, mask); 205 } 206 ingenic_irq(ipl); 207 KASSERT(id == 0); 208 } 209 } 210 211 void 212 ingenic_irq(int ipl) 213 { 214 uint32_t irql, irqh, mask, ll, hh; 215 int bit, idx, bail; 216 #ifdef INGENIC_INTR_DEBUG 217 char buffer[16]; 218 #endif 219 220 irql = readreg(JZ_ICPR0); 221 irqh = readreg(JZ_ICPR1); 222 #ifdef INGENIC_INTR_DEBUG 223 if (irql != 0) { 224 snprintf(buffer, 16, " il%08x", irql); 225 ingenic_puts(buffer); 226 } 227 #endif 228 bail = 32; 229 ll = irql; 230 hh = irqh; 231 writereg(JZ_ICMSR0, ll); 232 writereg(JZ_ICMSR1, hh); 233 bit = ffs32(irql); 234 while (bit != 0) { 235 idx = bit - 1; 236 mask = 1 << idx; 237 intrs[idx].ih_count.ev_count++; 238 if (intrs[idx].ih_func != NULL) { 239 if (intrs[idx].ih_ipl == IPL_VM) 240 KERNEL_LOCK(1, NULL); 241 intrs[idx].ih_func(intrs[idx].ih_arg); 242 if (intrs[idx].ih_ipl == IPL_VM) 243 KERNEL_UNLOCK_ONE(NULL); 244 } else { 245 /* spurious interrupt, mask it */ 246 writereg(JZ_ICMSR0, mask); 247 } 248 irql &= ~mask; 249 bit = ffs32(irql); 250 bail--; 251 KASSERT(bail > 0); 252 } 253 254 #ifdef INGENIC_INTR_DEBUG 255 if (irqh != 0) { 256 snprintf(buffer, 16, " ih%08x", irqh); 257 ingenic_puts(buffer); 258 } 259 #endif 260 bit = ffs32(irqh); 261 while (bit != 0) { 262 idx = bit - 1; 263 mask = 1 << idx; 264 idx += 32; 265 intrs[idx].ih_count.ev_count++; 266 if (intrs[idx].ih_func != NULL) { 267 if (intrs[idx].ih_ipl == IPL_VM) 268 KERNEL_LOCK(1, NULL); 269 intrs[idx].ih_func(intrs[idx].ih_arg); 270 if (intrs[idx].ih_ipl == IPL_VM) 271 KERNEL_UNLOCK_ONE(NULL); 272 } else { 273 /* spurious interrupt, mask it */ 274 writereg(JZ_ICMSR1, mask); 275 } 276 irqh &= ~mask; 277 bit = ffs32(irqh); 278 } 279 writereg(JZ_ICMCR0, ll); 280 writereg(JZ_ICMCR1, hh); 281 } 282 283 void * 284 evbmips_intr_establish(int irq, int (*func)(void *), void *arg) 285 { 286 int s; 287 288 if ((irq < 0) || (irq >= NINTR)) { 289 aprint_error("%s: invalid irq %d\n", __func__, irq); 290 return NULL; 291 } 292 293 s = splhigh(); /* XXX probably needs a mutex */ 294 intrs[irq].ih_func = func; 295 intrs[irq].ih_arg = arg; 296 intrs[irq].ih_ipl = IPL_VM; 297 298 /* now enable the IRQ */ 299 if (irq >= 32) { 300 writereg(JZ_ICMCR1, 1 << (irq - 32)); 301 } else 302 writereg(JZ_ICMCR0, 1 << irq); 303 304 splx(s); 305 306 return ((void *)(irq + 1)); 307 } 308 309 void 310 evbmips_intr_disestablish(void *cookie) 311 { 312 int irq = ((int)cookie) - 1; 313 int s; 314 315 if ((irq < 0) || (irq >= NINTR)) { 316 aprint_error("%s: invalid irq %d\n", __func__, irq); 317 return; 318 } 319 320 s = splhigh(); 321 322 /* disable the IRQ */ 323 if (irq >= 32) { 324 writereg(JZ_ICMSR1, 1 << (irq - 32)); 325 } else 326 writereg(JZ_ICMSR0, 1 << irq); 327 328 intrs[irq].ih_func = NULL; 329 intrs[irq].ih_arg = NULL; 330 intrs[irq].ih_ipl = 0; 331 332 splx(s); 333 } 334
Indexes created Fri Oct 03 17:10:05 GMT 2025