intr.c revision 1.7
1 /* $NetBSD: intr.c,v 1.7 2015/03/11 12:40:36 macallan Exp $ */ 2 3 /*- 4 * Copyright (c) 2014 Michael Lorenz 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 17 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 * POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: intr.c,v 1.7 2015/03/11 12:40:36 macallan Exp $"); 31 32 #define __INTR_PRIVATE 33 34 #include <sys/param.h> 35 #include <sys/cpu.h> 36 #include <sys/device.h> 37 #include <sys/kernel.h> 38 #include <sys/systm.h> 39 #include <sys/timetc.h> 40 #include <sys/bitops.h> 41 42 #include <mips/locore.h> 43 #include <machine/intr.h> 44 45 #include <mips/ingenic/ingenic_regs.h> 46 47 #include "opt_ingenic.h" 48 49 extern void ingenic_clockintr(uint32_t); 50 extern void ingenic_puts(const char *); 51 52 /* 53 * This is a mask of bits to clear in the SR when we go to a 54 * given hardware interrupt priority level. 55 */ 56 static const struct ipl_sr_map ingenic_ipl_sr_map = { 57 .sr_bits = { 58 [IPL_NONE] = 0, 59 [IPL_SOFTCLOCK] = MIPS_SOFT_INT_MASK_0, 60 [IPL_SOFTNET] = MIPS_SOFT_INT_MASK_0 | MIPS_SOFT_INT_MASK_1, 61 [IPL_VM] = 62 MIPS_SOFT_INT_MASK_0 | MIPS_SOFT_INT_MASK_1 | 63 MIPS_INT_MASK_0 | 64 MIPS_INT_MASK_3 | 65 MIPS_INT_MASK_4 | 66 MIPS_INT_MASK_5, 67 [IPL_SCHED] = 68 MIPS_SOFT_INT_MASK_0 | MIPS_SOFT_INT_MASK_1 | 69 MIPS_INT_MASK_0 | 70 MIPS_INT_MASK_1 | 71 MIPS_INT_MASK_2 | 72 MIPS_INT_MASK_3 | 73 MIPS_INT_MASK_4 | 74 MIPS_INT_MASK_5, 75 [IPL_DDB] = MIPS_INT_MASK, 76 [IPL_HIGH] = MIPS_INT_MASK, 77 }, 78 }; 79 80 #define NINTR 64 81 82 /* some timer channels share interrupts, couldn't find any others */ 83 struct intrhand { 84 struct evcnt ih_count; 85 char ih_name[16]; 86 int (*ih_func)(void *); 87 void *ih_arg; 88 int ih_ipl; 89 }; 90 91 struct intrhand intrs[NINTR]; 92 struct evcnt clockintrs; 93 94 void ingenic_irq(int); 95 96 void 97 evbmips_intr_init(void) 98 { 99 uint32_t reg; 100 int i; 101 102 ipl_sr_map = ingenic_ipl_sr_map; 103 104 evcnt_attach_dynamic(&clockintrs, 105 EVCNT_TYPE_INTR, NULL, "timer", "intr"); 106 107 /* zero all handlers */ 108 for (i = 0; i < NINTR; i++) { 109 intrs[i].ih_func = NULL; 110 intrs[i].ih_arg = NULL; 111 snprintf(intrs[i].ih_name, sizeof(intrs[i].ih_name), 112 "irq %d", i); 113 evcnt_attach_dynamic(&intrs[i].ih_count, EVCNT_TYPE_INTR, 114 NULL, "PIC", intrs[i].ih_name); 115 } 116 117 /* mask all peripheral IRQs */ 118 writereg(JZ_ICMR0, 0xffffffff); 119 writereg(JZ_ICMR1, 0xffffffff); 120 121 /* allow peripheral interrupts to core 0 only */ 122 reg = MFC0(12, 4); /* reset entry and interrupts */ 123 reg &= 0xffff0000; 124 reg |= REIM_IRQ0_M | REIM_MIRQ0_M | REIM_MIRQ1_M; 125 MTC0(reg, 12, 4); 126 } 127 128 void 129 evbmips_iointr(int ipl, vaddr_t pc, uint32_t ipending) 130 { 131 uint32_t id; 132 #ifdef INGENIC_INTR_DEBUG 133 char buffer[256]; 134 135 #if 0 136 snprintf(buffer, 256, "pending: %08x CR %08x\n", ipending, 137 MFC0(MIPS_COP_0_CAUSE, 0)); 138 ingenic_puts(buffer); 139 #endif 140 #endif 141 /* see which core we're on */ 142 id = MFC0(15, 1) & 7; 143 144 /* 145 * XXX 146 * the manual counts the softint bits as INT0 and INT1, out headers 147 * don't so everything here looks off by two 148 */ 149 if (ipending & MIPS_INT_MASK_1) { 150 /* 151 * this is a mailbox interrupt / IPI 152 * for now just print the message and clear it 153 */ 154 uint32_t reg; 155 156 /* read pending IPIs */ 157 reg = MFC0(12, 3); 158 if (id == 0) { 159 if (reg & CS_MIRQ0_P) { 160 161 #ifdef INGENIC_INTR_DEBUG 162 snprintf(buffer, 256, 163 "IPI for core 0, msg %08x\n", 164 MFC0(CP0_CORE_MBOX, 0)); 165 ingenic_puts(buffer); 166 #endif 167 reg &= (~CS_MIRQ0_P); 168 /* clear it */ 169 MTC0(reg, 12, 3); 170 } 171 } else if (id == 1) { 172 if (reg & CS_MIRQ1_P) { 173 #ifdef INGENIC_INTR_DEBUG 174 snprintf(buffer, 256, 175 "IPI for core 1, msg %08x\n", 176 MFC0(CP0_CORE_MBOX, 1)); 177 ingenic_puts(buffer); 178 #endif 179 reg &= ( 7 - CS_MIRQ1_P); 180 /* clear it */ 181 MTC0(reg, 12, 3); 182 } 183 } 184 } 185 if (ipending & MIPS_INT_MASK_2) { 186 /* this is a timer interrupt */ 187 ingenic_clockintr(id); 188 clockintrs.ev_count++; 189 ingenic_puts("INT2\n"); 190 } 191 if (ipending & MIPS_INT_MASK_0) { 192 uint32_t mask; 193 /* peripheral interrupt */ 194 195 /* 196 * XXX 197 * OS timer interrupts are supposed to show up as INT2 as well 198 * but I haven't seen them there so for now we just weed them 199 * out right here. 200 * The idea is to allow peripheral interrupts on both cores but 201 * block INT0 on core1 so it would see only timer interrupts 202 * and IPIs. If that doesn't work we'll have to send an IPI to 203 * core1 for each timer tick. 204 */ 205 mask = readreg(JZ_ICPR0); 206 if (mask & 0x0c000000) { 207 writereg(JZ_ICMSR0, mask); 208 ingenic_clockintr(id); 209 writereg(JZ_ICMCR0, mask); 210 clockintrs.ev_count++; 211 } 212 ingenic_irq(ipl); 213 KASSERT(id == 0); 214 } 215 } 216 217 void 218 ingenic_irq(int ipl) 219 { 220 uint32_t irql, irqh, mask, ll, hh; 221 int bit, idx, bail; 222 #ifdef INGENIC_INTR_DEBUG 223 char buffer[16]; 224 #endif 225 226 irql = readreg(JZ_ICPR0); 227 irqh = readreg(JZ_ICPR1); 228 #ifdef INGENIC_INTR_DEBUG 229 if (irql != 0) { 230 snprintf(buffer, 16, " il%08x", irql); 231 ingenic_puts(buffer); 232 } 233 #endif 234 bail = 32; 235 ll = irql; 236 hh = irqh; 237 writereg(JZ_ICMSR0, ll); 238 writereg(JZ_ICMSR1, hh); 239 bit = ffs32(irql); 240 while (bit != 0) { 241 idx = bit - 1; 242 mask = 1 << idx; 243 intrs[idx].ih_count.ev_count++; 244 if (intrs[idx].ih_func != NULL) { 245 if (intrs[idx].ih_ipl == IPL_VM) 246 KERNEL_LOCK(1, NULL); 247 intrs[idx].ih_func(intrs[idx].ih_arg); 248 if (intrs[idx].ih_ipl == IPL_VM) 249 KERNEL_UNLOCK_ONE(NULL); 250 } else { 251 /* spurious interrupt, mask it */ 252 writereg(JZ_ICMSR0, mask); 253 } 254 irql &= ~mask; 255 bit = ffs32(irql); 256 bail--; 257 KASSERT(bail > 0); 258 } 259 260 #ifdef INGENIC_INTR_DEBUG 261 if (irqh != 0) { 262 snprintf(buffer, 16, " ih%08x", irqh); 263 ingenic_puts(buffer); 264 } 265 #endif 266 bit = ffs32(irqh); 267 while (bit != 0) { 268 idx = bit - 1; 269 mask = 1 << idx; 270 idx += 32; 271 intrs[idx].ih_count.ev_count++; 272 if (intrs[idx].ih_func != NULL) { 273 if (intrs[idx].ih_ipl == IPL_VM) 274 KERNEL_LOCK(1, NULL); 275 intrs[idx].ih_func(intrs[idx].ih_arg); 276 if (intrs[idx].ih_ipl == IPL_VM) 277 KERNEL_UNLOCK_ONE(NULL); 278 } else { 279 /* spurious interrupt, mask it */ 280 writereg(JZ_ICMSR1, mask); 281 } 282 irqh &= ~mask; 283 bit = ffs32(irqh); 284 } 285 writereg(JZ_ICMCR0, ll); 286 writereg(JZ_ICMCR1, hh); 287 } 288 289 void * 290 evbmips_intr_establish(int irq, int (*func)(void *), void *arg) 291 { 292 int s; 293 294 if ((irq < 0) || (irq >= NINTR)) { 295 aprint_error("%s: invalid irq %d\n", __func__, irq); 296 return NULL; 297 } 298 299 s = splhigh(); /* XXX probably needs a mutex */ 300 intrs[irq].ih_func = func; 301 intrs[irq].ih_arg = arg; 302 intrs[irq].ih_ipl = IPL_VM; 303 304 /* now enable the IRQ */ 305 if (irq >= 32) { 306 writereg(JZ_ICMCR1, 1 << (irq - 32)); 307 } else 308 writereg(JZ_ICMCR0, 1 << irq); 309 310 splx(s); 311 312 return ((void *)(irq + 1)); 313 } 314 315 void 316 evbmips_intr_disestablish(void *cookie) 317 { 318 int irq = ((int)cookie) - 1; 319 int s; 320 321 if ((irq < 0) || (irq >= NINTR)) { 322 aprint_error("%s: invalid irq %d\n", __func__, irq); 323 return; 324 } 325 326 s = splhigh(); 327 328 /* disable the IRQ */ 329 if (irq >= 32) { 330 writereg(JZ_ICMSR1, 1 << (irq - 32)); 331 } else 332 writereg(JZ_ICMSR0, 1 << irq); 333 334 intrs[irq].ih_func = NULL; 335 intrs[irq].ih_arg = NULL; 336 intrs[irq].ih_ipl = 0; 337 338 splx(s); 339 } 340
Indexes created Fri Oct 03 17:10:05 GMT 2025