generic2e_machdep.c revision 1.4
1 /* $OpenBSD: generic2e_machdep.c,v 1.2 2011/04/15 20:40:06 deraadt Exp $ */ 2 3 /* 4 * Copyright (c) 2010 Miodrag Vallat. 5 * 6 * Permission to use, copy, modify, and distribute this software for any 7 * purpose with or without fee is hereby granted, provided that the above 8 * copyright notice and this permission notice appear in all copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 17 */ 18 /*- 19 * Copyright (c) 2000, 2001 The NetBSD Foundation, Inc. 20 * All rights reserved. 21 * 22 * This code is derived from software contributed to The NetBSD Foundation 23 * by Jason R. Thorpe. 24 * 25 * Redistribution and use in source and binary forms, with or without 26 * modification, are permitted provided that the following conditions 27 * are met: 28 * 1. Redistributions of source code must retain the above copyright 29 * notice, this list of conditions and the following disclaimer. 30 * 2. Redistributions in binary form must reproduce the above copyright 31 * notice, this list of conditions and the following disclaimer in the 32 * documentation and/or other materials provided with the distribution. 33 * 34 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 35 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 36 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 37 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 38 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 39 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 40 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 41 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 42 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 43 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 44 * POSSIBILITY OF SUCH DAMAGE. 45 */ 46 47 /* 48 * Generic Loongson 2E code and configuration data. 49 */ 50 #include <sys/cdefs.h> 51 __KERNEL_RCSID(0, "$NetBSD: generic2e_machdep.c,v 1.4 2014/03/29 19:28:28 christos Exp $"); 52 53 #include <sys/param.h> 54 #include <sys/systm.h> 55 #include <sys/device.h> 56 #include <sys/types.h> 57 58 59 #include <dev/ic/i8259reg.h> 60 61 #include <dev/isa/isareg.h> 62 #include <dev/isa/isavar.h> 63 64 #include <dev/pci/pcireg.h> 65 #include <dev/pci/pcivar.h> 66 #include <dev/pci/pcidevs.h> 67 68 #include <mips/bonito/bonitoreg.h> 69 #include <mips/bonito/bonitovar.h> 70 71 #include <evbmips/loongson/autoconf.h> 72 #include <mips/pmon/pmon.h> 73 #include <evbmips/loongson/loongson_intr.h> 74 #include <evbmips/loongson/loongson_isa.h> 75 #include <evbmips/loongson/loongson_bus_defs.h> 76 77 #include "com.h" 78 #include "isa.h" 79 80 #if NCOM > 0 81 #include <sys/termios.h> 82 #include <dev/ic/comvar.h> 83 #endif 84 85 void generic2e_device_register(device_t, void *); 86 void generic2e_reset(void); 87 88 void generic2e_setup(void); 89 90 void generic2e_pci_attach_hook(device_t, device_t, 91 struct pcibus_attach_args *); 92 int generic2e_intr_map(int, int, int, pci_intr_handle_t *); 93 94 void generic2e_isa_attach_hook(device_t, device_t, 95 struct isabus_attach_args *); 96 void *generic2e_isa_intr_establish(void *, int, int, int, 97 int (*)(void *), void *); 98 void generic2e_isa_intr_disestablish(void *, void *); 99 const struct evcnt * generic2e_isa_intr_evcnt(void *, int); 100 const char * generic2e_isa_intr_string(void *, int, char *, size_t); 101 102 void generic2e_isa_intr(int, vaddr_t, uint32_t); 103 104 void via686sb_setup(pci_chipset_tag_t, int); 105 106 /* PnP IRQ assignment for VIA686 SuperIO components */ 107 #define VIA686_IRQ_PCIA 9 108 #define VIA686_IRQ_PCIB 10 109 #define VIA686_IRQ_PCIC 11 110 #define VIA686_IRQ_PCID 13 111 112 static int generic2e_via686sb_dev = -1; 113 114 const struct bonito_config generic2e_bonito = { 115 .bc_adbase = 11, 116 117 .bc_gpioIE = 0xffffffff, 118 .bc_intEdge = BONITO_INTRMASK_SYSTEMERR | BONITO_INTRMASK_MASTERERR | 119 BONITO_INTRMASK_RETRYERR | BONITO_INTRMASK_MBOX, 120 .bc_intSteer = 0, 121 .bc_intPol = 0, 122 123 .bc_attach_hook = generic2e_pci_attach_hook, 124 }; 125 126 const struct legacy_io_range generic2e_legacy_ranges[] = { 127 /* no isa space access restrictions */ 128 { 0, BONITO_PCIIO_LEGACY }, 129 130 { 0 } 131 }; 132 133 struct mips_isa_chipset generic2e_isa_chipset = { 134 .ic_v = NULL, 135 136 .ic_attach_hook = generic2e_isa_attach_hook, 137 .ic_intr_establish = generic2e_isa_intr_establish, 138 .ic_intr_disestablish = generic2e_isa_intr_disestablish, 139 .ic_intr_evcnt = generic2e_isa_intr_evcnt, 140 .ic_intr_string = generic2e_isa_intr_string, 141 }; 142 143 const struct platform generic2e_platform = { 144 .system_type = LOONGSON_2E, 145 .vendor = "Generic", 146 .product = "Loongson2E", 147 148 .bonito_config = &generic2e_bonito, 149 .isa_chipset = &generic2e_isa_chipset, 150 .legacy_io_ranges = generic2e_legacy_ranges, 151 .bonito_mips_intr = MIPS_INT_MASK_0, 152 .isa_mips_intr = MIPS_INT_MASK_3, 153 .isa_intr = generic2e_isa_intr, 154 .p_pci_intr_map = generic2e_intr_map, 155 .irq_map = loongson2e_irqmap, 156 157 .setup = generic2e_setup, 158 .device_register = generic2e_device_register, 159 160 .powerdown = NULL, 161 .reset = generic2e_reset 162 }; 163 164 /* 165 * PCI model specific routines 166 */ 167 168 void 169 generic2e_pci_attach_hook(device_t parent, device_t self, 170 struct pcibus_attach_args *pba) 171 { 172 pci_chipset_tag_t pc = pba->pba_pc; 173 pcireg_t id; 174 pcitag_t tag; 175 int dev; 176 177 if (pba->pba_bus != 0) 178 return; 179 180 /* 181 * Check for a VIA 686 southbridge; if one is found, remember 182 * its location, needed by generic2e_intr_map(). 183 */ 184 185 for (dev = pci_bus_maxdevs(pc, 0); dev >= 0; dev--) { 186 tag = pci_make_tag(pc, 0, dev, 0); 187 id = pci_conf_read(pc, tag, PCI_ID_REG); 188 if (id == PCI_ID_CODE(PCI_VENDOR_VIATECH, 189 PCI_PRODUCT_VIATECH_VT82C686A_ISA)) { 190 generic2e_via686sb_dev = dev; 191 break; 192 } 193 } 194 195 if (generic2e_via686sb_dev != 0) 196 via686sb_setup(pc, generic2e_via686sb_dev); 197 } 198 199 int 200 generic2e_intr_map(int dev, int fn, int pin, pci_intr_handle_t *ihp) 201 { 202 if (dev == generic2e_via686sb_dev) { 203 switch (fn) { 204 case 1: /* PCIIDE */ 205 /* will use compat interrupt */ 206 break; 207 case 2: /* USB */ 208 *ihp = BONITO_ISA_IRQ(VIA686_IRQ_PCIB); 209 return 0; 210 case 3: /* USB */ 211 *ihp = BONITO_ISA_IRQ(VIA686_IRQ_PCIC); 212 return 0; 213 case 4: /* power management, SMBus */ 214 break; 215 case 5: /* Audio */ 216 *ihp = BONITO_ISA_IRQ(VIA686_IRQ_PCIA); 217 return 0; 218 case 6: /* Modem */ 219 break; 220 default: 221 break; 222 } 223 } else { 224 *ihp = BONITO_DIRECT_IRQ(BONITO_INTR_GPIN + 225 pin - PCI_INTERRUPT_PIN_A); 226 return 0; 227 } 228 229 return 1; 230 } 231 232 /* 233 * ISA model specific routines 234 */ 235 236 void 237 generic2e_isa_attach_hook(device_t parent, device_t self, 238 struct isabus_attach_args *iba) 239 { 240 loongson_set_isa_imr(loongson_isaimr); 241 } 242 243 void * 244 generic2e_isa_intr_establish(void *v, int irq, int type, int level, 245 int (*handler)(void *), void *arg) 246 { 247 void *ih; 248 uint imr; 249 250 ih = evbmips_intr_establish(BONITO_ISA_IRQ(irq), handler, arg); 251 if (ih == NULL) 252 return NULL; 253 /* enable interrupt */ 254 imr = loongson_isaimr; 255 imr |= (1 << irq); 256 loongson_set_isa_imr(imr); 257 return ih; 258 } 259 260 void 261 generic2e_isa_intr_disestablish(void *v, void *ih) 262 { 263 evbmips_intr_disestablish(ih); 264 } 265 266 const struct evcnt * 267 generic2e_isa_intr_evcnt(void *v, int irq) 268 { 269 270 if (irq == 0 || irq >= BONITO_NISA || irq == 2) 271 panic("generic2e_isa_intr_evcnt: bogus isa irq 0x%x", irq); 272 273 return (&bonito_intrhead[BONITO_ISA_IRQ(irq)].intr_count); 274 } 275 276 const char * 277 generic2e_isa_intr_string(void *v, int irq, char *buf, size_t len) 278 { 279 if (irq == 0 || irq >= BONITO_NISA || irq == 2) 280 panic("generic2e_isa_intr_string: bogus isa irq 0x%x", irq); 281 282 return loongson_intr_string(&generic2e_bonito, irq, buf, len); 283 } 284 285 void 286 generic2e_isa_intr(int ipl, vaddr_t pc, uint32_t ipending) 287 { 288 #if NISA > 0 289 struct evbmips_intrhand *ih; 290 uint64_t isr, mask = 0; 291 int rc, irq, ret; 292 uint8_t ocw1, ocw2; 293 294 for (;;) { 295 REGVAL8(BONITO_PCIIO_BASE + IO_ICU1 + PIC_OCW3) = 296 OCW3_SELECT | OCW3_POLL; 297 ocw1 = REGVAL8(BONITO_PCIIO_BASE + IO_ICU1 + PIC_OCW3); 298 if ((ocw1 & OCW3_POLL_PENDING) == 0) 299 break; 300 301 irq = OCW3_POLL_IRQ(ocw1); 302 303 if (irq == 2) /* cascade */ { 304 REGVAL8(BONITO_PCIIO_BASE + IO_ICU2 + PIC_OCW3) = 305 OCW3_SELECT | OCW3_POLL; 306 ocw2 = REGVAL8(BONITO_PCIIO_BASE + IO_ICU2 + PIC_OCW3); 307 if (ocw2 & OCW3_POLL_PENDING) 308 irq = OCW3_POLL_IRQ(ocw2); 309 else 310 irq = 2; 311 } else 312 ocw2 = 0; 313 314 /* 315 * Mask the interrupt before servicing it. 316 */ 317 isr = 1UL << irq; 318 loongson_set_isa_imr(loongson_isaimr & ~isr); 319 320 mask |= isr; 321 322 rc = 0; 323 LIST_FOREACH(ih, 324 &bonito_intrhead[BONITO_ISA_IRQ(irq)].intrhand_head, 325 ih_q) { 326 ret = (*ih->ih_func)(ih->ih_arg); 327 if (ret) { 328 rc = 1; 329 bonito_intrhead[BONITO_ISA_IRQ(irq)].intr_count.ev_count++; 330 } 331 332 if (ret == 1) 333 break; 334 } 335 336 /* Send a specific EOI to the 8259. */ 337 loongson_isa_specific_eoi(irq); 338 339 if (rc == 0) { 340 printf("spurious isa interrupt %d\n", irq); 341 } 342 } 343 344 /* 345 * Reenable interrupts which have been serviced. 346 */ 347 if (mask != 0) 348 loongson_set_isa_imr(loongson_isaimr | mask); 349 350 #endif 351 } 352 353 /* 354 * Other model specific routines 355 */ 356 357 void 358 generic2e_reset(void) 359 { 360 REGVAL(BONITO_BONGENCFG) &= ~BONITO_BONGENCFG_CPUSELFRESET; 361 REGVAL(BONITO_BONGENCFG) |= BONITO_BONGENCFG_CPUSELFRESET; 362 delay(1000000); 363 } 364 365 void 366 generic2e_setup(void) 367 { 368 #if NCOM > 0 369 const char *envvar; 370 int serial; 371 372 envvar = pmon_getenv("nokbd"); 373 serial = envvar != NULL; 374 envvar = pmon_getenv("novga"); 375 serial = serial && envvar != NULL; 376 377 if (serial) { 378 comconsiot = &bonito_iot; 379 comconsaddr = 0x3f8; 380 comconsrate = 115200; /* default PMON console speed */ 381 } 382 #endif 383 } 384 385 void 386 generic2e_device_register(device_t dev, void *aux) 387 { 388 const char *name = device_xname(dev); 389 390 if (device_class(dev) != bootdev_class) 391 return; 392 393 /* 394 * The device numbering must match. There's no way 395 * pmon tells us more info. Depending on the usb slot 396 * and hubs used you may be lucky. Also, assume umass/sd for usb 397 * attached devices. 398 */ 399 switch (bootdev_class) { 400 case DV_DISK: 401 if (device_is_a(dev, "wd") && strcmp(name, bootdev) == 0) { 402 if (booted_device == NULL) 403 booted_device = dev; 404 } else { 405 /* XXX this really only works safely for usb0... */ 406 if ((device_is_a(dev, "sd") || 407 device_is_a(dev, "cd")) && 408 strncmp(bootdev, "usb", 3) == 0 && 409 strcmp(name + 2, bootdev + 3) == 0) { 410 if (booted_device == NULL) 411 booted_device = dev; 412 } 413 } 414 break; 415 case DV_IFNET: 416 /* 417 * This relies on the onboard Ethernet interface being 418 * attached before any other (usb) interface. 419 */ 420 if (booted_device == NULL) 421 booted_device = dev; 422 break; 423 default: 424 break; 425 } 426 } 427 428 /* 429 * Initialize a VIA686 south bridge. 430 * 431 * PMON apparently does not perform enough initialization; one may argue this 432 * could be done with a specific pcib(4) driver, but then no other system 433 * will hopefully need this, so keep it local to the 2E setup code. 434 */ 435 436 #define VIA686_ISA_ROM_CONTROL 0x40 437 #define VIA686_ROM_WRITE_ENABLE 0x00000001 438 #define VIA686_NO_ROM_WAIT_STATE 0x00000002 439 #define VIA686_EXTEND_ALE 0x00000004 440 #define VIA686_IO_RECOVERY_TIME 0x00000008 441 #define VIA686_CHIPSET_EXTRA_WAIT_STATES 0x00000010 442 #define VIA686_ISA_EXTRA_WAIT_STATES 0x00000020 443 #define VIA686_ISA_EXTENDED_BUS_READY 0x00000040 444 #define VIA686_ISA_EXTRA_COMMAND_DELAY 0x00000080 445 #define VIA686_ISA_REFRESH 0x00000100 446 #define VIA686_DOUBLE_DMA_CLOCK 0x00000800 447 #define VIA686_PORT_92_FAST_RESET 0x00002000 448 #define VIA686_IO_MEDIUM_RECOVERY_TIME 0x00004000 449 #define VIA686_KBC_DMA_MISC12 0x44 450 #define VIA686_ISA_MASTER_TO_LINE_BUFFER 0x00008000 451 #define VIA686_POSTED_MEMORY_WRITE_ENABLE 0x00010000 452 #define VIA686_PCI_BURST_INTERRUPTABLE 0x00020000 453 #define VIA686_FLUSH_LINE_BUFFER_ON_INTR 0x00200000 454 #define VIA686_GATE_INTR 0x00400000 455 #define VIA686_PCI_MASTER_WRITE_WAIT_STATE 0x00800000 456 #define VIA686_PCI_RESET 0x01000000 457 #define VIA686_PCI_READ_DELAY_TRANSACTION_TMO 0x02000000 458 #define VIA686_PCI_WRITE_DELAY_TRANSACTION_TMO 0x04000000 459 #define VIA686_ICR_SHADOW_ENABLE 0x10000000 460 #define VIA686_EISA_PORT_4D0_4D1_ENABLE 0x20000000 461 #define VIA686_PCI_DELAY_TRANSACTION_ENABLE 0x40000000 462 #define VIA686_CPU_RESET_SOURCE_INIT 0x80000000 463 #define VIA686_MISC3_IDE_INTR 0x48 464 #define VIA686_IDE_PRIMARY_CHAN_MASK 0x00030000 465 #define VIA686_IDE_PRIMARY_CHAN_SHIFT 16 466 #define VIA686_IDE_SECONDARY_CHAN_MASK 0x000c0000 467 #define VIA686_IDE_SECONDARY_CHAN_SHIFT 18 468 #define VIA686_IDE_IRQ14 00 469 #define VIA686_IDE_IRQ15 01 470 #define VIA686_IDE_IRQ10 02 471 #define VIA686_IDE_IRQ11 03 472 #define VIA686_IDE_PGNT 0x00800000 473 #define VIA686_PNP_DMA_IRQ 0x50 474 #define VIA686_DMA_FDC_MASK 0x00000003 475 #define VIA686_DMA_FDC_SHIFT 0 476 #define VIA686_DMA_LPT_MASK 0x0000000c 477 #define VIA686_DMA_LPT_SHIFT 2 478 #define VIA686_IRQ_FDC_MASK 0x00000f00 479 #define VIA686_IRQ_FDC_SHIFT 8 480 #define VIA686_IRQ_LPT_MASK 0x0000f000 481 #define VIA686_IRQ_LPT_SHIFT 12 482 #define VIA686_IRQ_COM0_MASK 0x000f0000 483 #define VIA686_IRQ_COM0_SHIFT 16 484 #define VIA686_IRQ_COM1_MASK 0x00f00000 485 #define VIA686_IRQ_COM1_SHIFT 20 486 #define VIA686_PCI_LEVEL_PNP_IRQ2 0x54 487 #define VIA686_PCI_IRQD_EDGE 0x00000001 488 #define VIA686_PCI_IRQC_EDGE 0x00000002 489 #define VIA686_PCI_IRQB_EDGE 0x00000004 490 #define VIA686_PCI_IRQA_EDGE 0x00000008 491 #define VIA686_IRQ_PCIA_MASK 0x0000f000 492 #define VIA686_IRQ_PCIA_SHIFT 12 493 #define VIA686_IRQ_PCIB_MASK 0x000f0000 494 #define VIA686_IRQ_PCIB_SHIFT 16 495 #define VIA686_IRQ_PCIC_MASK 0x00f00000 496 #define VIA686_IRQ_PCIC_SHIFT 20 497 #define VIA686_IRQ_PCID_MASK 0xf0000000 498 #define VIA686_IRQ_PCID_SHIFT 28 499 500 void 501 via686sb_setup(pci_chipset_tag_t pc, int dev) 502 { 503 pcitag_t tag; 504 pcireg_t reg; 505 uint elcr; 506 507 tag = pci_make_tag(pc, 0, dev, 0); 508 509 /* 510 * Generic ISA bus initialization. 511 */ 512 513 reg = pci_conf_read(pc, tag, VIA686_ISA_ROM_CONTROL); 514 reg |= VIA686_IO_RECOVERY_TIME | VIA686_ISA_REFRESH; 515 pci_conf_write(pc, tag, VIA686_ISA_ROM_CONTROL, reg); 516 517 reg = pci_conf_read(pc, tag, VIA686_KBC_DMA_MISC12); 518 reg |= VIA686_CPU_RESET_SOURCE_INIT | 519 VIA686_PCI_DELAY_TRANSACTION_ENABLE | 520 VIA686_EISA_PORT_4D0_4D1_ENABLE | 521 VIA686_PCI_WRITE_DELAY_TRANSACTION_TMO | 522 VIA686_PCI_READ_DELAY_TRANSACTION_TMO | 523 VIA686_PCI_MASTER_WRITE_WAIT_STATE | VIA686_GATE_INTR | 524 VIA686_FLUSH_LINE_BUFFER_ON_INTR; 525 reg &= ~VIA686_ISA_MASTER_TO_LINE_BUFFER; 526 pci_conf_write(pc, tag, VIA686_KBC_DMA_MISC12, reg); 527 528 /* 529 * SuperIO devices interrupt and DMA setup. 530 */ 531 532 reg = pci_conf_read(pc, tag, VIA686_MISC3_IDE_INTR); 533 reg &= ~(VIA686_IDE_PRIMARY_CHAN_MASK | VIA686_IDE_SECONDARY_CHAN_MASK); 534 reg |= (VIA686_IDE_IRQ14 << VIA686_IDE_PRIMARY_CHAN_SHIFT); 535 reg |= (VIA686_IDE_IRQ15 << VIA686_IDE_SECONDARY_CHAN_SHIFT); 536 reg |= VIA686_IDE_PGNT; 537 pci_conf_write(pc, tag, VIA686_MISC3_IDE_INTR, reg); 538 539 reg = pci_conf_read(pc, tag, VIA686_PNP_DMA_IRQ); 540 reg &= ~(VIA686_DMA_FDC_MASK | VIA686_DMA_LPT_MASK); 541 reg |= (2 << VIA686_DMA_FDC_SHIFT) | (3 << VIA686_DMA_LPT_SHIFT); 542 reg &= ~(VIA686_IRQ_FDC_MASK | VIA686_IRQ_LPT_MASK); 543 reg |= (6 << VIA686_IRQ_FDC_SHIFT) | (7 << VIA686_IRQ_LPT_SHIFT); 544 reg &= ~(VIA686_IRQ_COM0_MASK | VIA686_IRQ_COM1_MASK); 545 reg |= (4 << VIA686_IRQ_COM0_SHIFT) | (3 << VIA686_IRQ_COM1_SHIFT); 546 547 reg = pci_conf_read(pc, tag, VIA686_PCI_LEVEL_PNP_IRQ2); 548 reg &= ~(VIA686_PCI_IRQA_EDGE | VIA686_PCI_IRQB_EDGE | 549 VIA686_PCI_IRQB_EDGE | VIA686_PCI_IRQD_EDGE); 550 reg &= ~(VIA686_IRQ_PCIA_MASK | VIA686_IRQ_PCIB_MASK | 551 VIA686_IRQ_PCIC_MASK | VIA686_IRQ_PCID_MASK); 552 reg |= (VIA686_IRQ_PCIA << VIA686_IRQ_PCIA_SHIFT) | 553 (VIA686_IRQ_PCIB << VIA686_IRQ_PCIB_SHIFT) | 554 (VIA686_IRQ_PCIC << VIA686_IRQ_PCIC_SHIFT) | 555 (VIA686_IRQ_PCID << VIA686_IRQ_PCID_SHIFT); 556 557 /* 558 * Interrupt controller setup. 559 */ 560 561 /* reset; program device, four bytes */ 562 REGVAL8(BONITO_PCIIO_BASE + IO_ICU1 + PIC_ICW1) = 563 ICW1_SELECT | ICW1_IC4; 564 REGVAL8(BONITO_PCIIO_BASE + IO_ICU1 + PIC_ICW2) = ICW2_VECTOR(0); 565 REGVAL8(BONITO_PCIIO_BASE + IO_ICU1 + PIC_ICW3) = ICW3_CASCADE(2); 566 REGVAL8(BONITO_PCIIO_BASE + IO_ICU1 + PIC_ICW4) = ICW4_8086; 567 /* leave interrupts masked */ 568 REGVAL8(BONITO_PCIIO_BASE + IO_ICU1 + PIC_OCW1) = 0xff; 569 /* special mask mode (if available) */ 570 REGVAL8(BONITO_PCIIO_BASE + IO_ICU1 + PIC_OCW3) = 571 OCW3_SELECT | OCW3_SSMM | OCW3_SMM; 572 /* read IRR by default. */ 573 REGVAL8(BONITO_PCIIO_BASE + IO_ICU1 + PIC_OCW3) = OCW3_SELECT | OCW3_RR; 574 575 /* reset; program device, four bytes */ 576 REGVAL8(BONITO_PCIIO_BASE + IO_ICU2 + PIC_ICW1) = 577 ICW1_SELECT | ICW1_IC4; 578 REGVAL8(BONITO_PCIIO_BASE + IO_ICU2 + PIC_ICW2) = ICW2_VECTOR(8); 579 REGVAL8(BONITO_PCIIO_BASE + IO_ICU2 + PIC_ICW3) = ICW3_SIC(2); 580 REGVAL8(BONITO_PCIIO_BASE + IO_ICU2 + PIC_ICW4) = ICW4_8086; 581 /* leave interrupts masked */ 582 REGVAL8(BONITO_PCIIO_BASE + IO_ICU2 + PIC_OCW1) = 0xff; 583 /* special mask mode (if available) */ 584 REGVAL8(BONITO_PCIIO_BASE + IO_ICU2 + PIC_OCW3) = 585 OCW3_SELECT | OCW3_SSMM | OCW3_SMM; 586 /* read IRR by default. */ 587 REGVAL8(BONITO_PCIIO_BASE + IO_ICU2 + PIC_OCW3) = OCW3_SELECT | OCW3_RR; 588 589 /* setup ELCR: PCI interrupts are level-triggered. */ 590 elcr = (1 << VIA686_IRQ_PCIA) | (1 << VIA686_IRQ_PCIB) | 591 (1 << VIA686_IRQ_PCIC) | (1 << VIA686_IRQ_PCID); 592 REGVAL8(BONITO_PCIIO_BASE + 0x4d0) = (elcr >> 0) & 0xff; 593 REGVAL8(BONITO_PCIIO_BASE + 0x4d1) = (elcr >> 8) & 0xff; 594 595 __asm__ __volatile__ ("sync" ::: "memory"); 596 597 /* 598 * Update interrupt information for secondary functions. 599 * Although this information is not used by pci_intr_establish() 600 * because of generic2e_intr_map() behaviour, it seems to be 601 * required to complete proper interrupt routing. 602 */ 603 604 tag = pci_make_tag(pc, 0, dev, 2); 605 reg = pci_conf_read(pc, tag, PCI_INTERRUPT_REG); 606 reg &= ~(PCI_INTERRUPT_LINE_MASK << PCI_INTERRUPT_LINE_SHIFT); 607 reg |= VIA686_IRQ_PCIB << PCI_INTERRUPT_LINE_SHIFT; 608 pci_conf_write(pc, tag, PCI_INTERRUPT_REG, reg); 609 610 tag = pci_make_tag(pc, 0, dev, 3); 611 reg = pci_conf_read(pc, tag, PCI_INTERRUPT_REG); 612 reg &= ~(PCI_INTERRUPT_LINE_MASK << PCI_INTERRUPT_LINE_SHIFT); 613 reg |= VIA686_IRQ_PCIC << PCI_INTERRUPT_LINE_SHIFT; 614 pci_conf_write(pc, tag, PCI_INTERRUPT_REG, reg); 615 616 tag = pci_make_tag(pc, 0, dev, 5); 617 reg = pci_conf_read(pc, tag, PCI_INTERRUPT_REG); 618 reg &= ~(PCI_INTERRUPT_LINE_MASK << PCI_INTERRUPT_LINE_SHIFT); 619 reg |= VIA686_IRQ_PCIA << PCI_INTERRUPT_LINE_SHIFT; 620 pci_conf_write(pc, tag, PCI_INTERRUPT_REG, reg); 621 } 622
Indexes created Tue Sep 30 17:09:57 GMT 2025