loongson_clock.c revision 1.1.18.2
1 /* $NetBSD: loongson_clock.c,v 1.1.18.2 2017/12/03 11:36:09 jdolecek Exp $ */ 2 3 /* 4 * Copyright (c) 2011, 2016 Michael Lorenz 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 21 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 22 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 23 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 25 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 #include <sys/cdefs.h> 29 __KERNEL_RCSID(0, "$NetBSD: loongson_clock.c,v 1.1.18.2 2017/12/03 11:36:09 jdolecek Exp $"); 30 31 #include <sys/param.h> 32 #include <sys/systm.h> 33 #include <sys/kernel.h> 34 #include <sys/device.h> 35 #include <sys/cpu.h> 36 #include <sys/timetc.h> 37 #include <sys/sysctl.h> 38 39 #include <mips/mips3_clock.h> 40 #include <mips/locore.h> 41 #include <mips/bonito/bonitoreg.h> 42 #include <mips/bonito/bonitovar.h> 43 44 #ifdef LOONGSON_CLOCK_DEBUG 45 #define DPRINTF aprint_error 46 #else 47 #define DPRINTF while (0) printf 48 #endif 49 50 static uint32_t sc_last; 51 static uint32_t sc_scale[8]; 52 static uint32_t sc_count; /* should probably be 64 bit */ 53 static int sc_step = 7; 54 static int sc_step_wanted = 7; 55 static void *sc_shutdown_cookie; 56 57 /* 0, 1/4, 3/8, 1/2, 5/8, 3/4, 7/8, 1 */ 58 static int scale_m[] = {1, 1, 3, 1, 5, 3, 7, 1}; 59 static int scale_d[] = {0, 4, 8, 2, 8, 4, 8, 1}; 60 static int cycles[8]; 61 62 #define scale(x, f) (x * scale_d[f] / scale_m[f]) 63 #define rscale(x, f) (x * scale_m[f] / scale_d[f]) 64 65 static void loongson_set_speed(int); 66 static int loongson_cpuspeed_temp(SYSCTLFN_ARGS); 67 static int loongson_cpuspeed_cur(SYSCTLFN_ARGS); 68 static int loongson_cpuspeed_available(SYSCTLFN_ARGS); 69 70 static void loongson_clock_shutdown(void *); 71 static u_int get_loongson_timecount(struct timecounter *); 72 void loongson_delay(int); 73 void loongson_setstatclockrate(int); 74 void loongson_initclocks(void); 75 76 static struct timecounter loongson_timecounter = { 77 get_loongson_timecount, /* get_timecount */ 78 0, /* no poll_pps */ 79 0xffffffff, /* counter_mask */ 80 0, /* frequency */ 81 "loongson", /* name */ 82 100, /* quality */ 83 NULL, /* tc_priv */ 84 NULL /* tc_next */ 85 }; 86 87 void 88 loongson_initclocks(void) 89 { 90 const struct sysctlnode *sysctl_node, *me, *freq; 91 int clk; 92 93 /* 94 * Establish a hook so on shutdown we can set the CPU clock back to 95 * full speed. This is necessary because PMON doesn't change the 96 * clock scale register on a warm boot, the MIPS clock code gets 97 * confused if we're too slow and the loongson-specific bits run 98 * too late in the boot process 99 */ 100 sc_shutdown_cookie = shutdownhook_establish(loongson_clock_shutdown, NULL); 101 102 for (clk = 1; clk < 8; clk++) { 103 sc_scale[clk] = rscale(curcpu()->ci_cpu_freq / 1000000, clk); 104 cycles[clk] = 105 (rscale(curcpu()->ci_cpu_freq, clk) + hz / 2) / (2 * hz); 106 } 107 #ifdef LOONGSON_CLOCK_DEBUG 108 for (clk = 1; clk < 8; clk++) { 109 aprint_normal("frequencies: %d/8: %d\n", clk + 1, 110 sc_scale[clk]); 111 } 112 #endif 113 114 /* now setup sysctl */ 115 if (sysctl_createv(NULL, 0, NULL, 116 &me, 117 CTLFLAG_READWRITE, CTLTYPE_NODE, "loongson", NULL, NULL, 118 0, NULL, 0, CTL_MACHDEP, CTL_CREATE, CTL_EOL) != 0) 119 aprint_error("couldn't create 'loongson' node\n"); 120 121 if (sysctl_createv(NULL, 0, NULL, 122 &freq, 123 CTLFLAG_READWRITE, CTLTYPE_NODE, "frequency", NULL, NULL, 0, NULL, 124 0, CTL_MACHDEP, me->sysctl_num, CTL_CREATE, CTL_EOL) != 0) 125 aprint_error("couldn't create 'frequency' node\n"); 126 127 if (sysctl_createv(NULL, 0, NULL, 128 &sysctl_node, 129 CTLFLAG_READWRITE | CTLFLAG_OWNDESC, 130 CTLTYPE_INT, "target", "CPU speed", loongson_cpuspeed_temp, 131 0, NULL, 0, CTL_MACHDEP, me->sysctl_num, freq->sysctl_num, 132 CTL_CREATE, CTL_EOL) == 0) { 133 } else 134 aprint_error("couldn't create 'target' node\n"); 135 136 if (sysctl_createv(NULL, 0, NULL, 137 &sysctl_node, 138 CTLFLAG_READWRITE, 139 CTLTYPE_INT, "current", NULL, loongson_cpuspeed_cur, 140 1, NULL, 0, CTL_MACHDEP, me->sysctl_num, freq->sysctl_num, 141 CTL_CREATE, CTL_EOL) == 0) { 142 } else 143 aprint_error("couldn't create 'current' node\n"); 144 145 if (sysctl_createv(NULL, 0, NULL, 146 &sysctl_node, 147 CTLFLAG_READWRITE, 148 CTLTYPE_STRING, "available", NULL, loongson_cpuspeed_available, 149 2, NULL, 0, CTL_MACHDEP, me->sysctl_num, freq->sysctl_num, 150 CTL_CREATE, CTL_EOL) == 0) { 151 } else 152 aprint_error("couldn't create 'available' node\n"); 153 154 sc_count = 0; 155 loongson_timecounter.tc_frequency = curcpu()->ci_cpu_freq / 2; 156 curcpu()->ci_cctr_freq = loongson_timecounter.tc_frequency; 157 158 sc_last = mips3_cp0_count_read(); 159 mips3_cp0_compare_write(sc_last + curcpu()->ci_cycles_per_hz); 160 161 tc_init(&loongson_timecounter); 162 163 /* 164 * Now we can enable all interrupts including hardclock(9) 165 * by CPU INT5. 166 */ 167 spl0(); 168 printf("boom\n"); 169 } 170 171 static void 172 loongson_clock_shutdown(void *cookie) 173 { 174 175 /* just in case the interrupt handler runs again after this */ 176 sc_step_wanted = 7; 177 /* set the clock to full speed */ 178 REGVAL(LS2F_CHIPCFG0) = 179 (REGVAL(LS2F_CHIPCFG0) & ~LS2FCFG_FREQSCALE_MASK) | 7; 180 } 181 182 void 183 loongson_set_speed(int speed) 184 { 185 186 if ((speed < 1) || (speed > 7)) 187 return; 188 sc_step_wanted = speed; 189 DPRINTF("%s: %d\n", __func__, speed); 190 } 191 192 /* 193 * the clock interrupt handler 194 * we don't have a CPU clock independent, high resolution counter so we're 195 * stuck with a PWM that can't count and a CP0 counter that slows down or 196 * speeds up with the actual CPU speed. In order to still get halfway 197 * accurate time we do the following: 198 * - only change CPU speed in the timer interrupt 199 * - each timer interrupt we measure how many CP0 cycles passed since last 200 * time, adjust for CPU speed since we can be sure it didn't change, use 201 * that to update a separate counter 202 * - when reading the time counter we take the number of CP0 ticks since 203 * the last timer interrupt, scale it to CPU clock, return that plus the 204 * interrupt updated counter mentioned above to get something close to 205 * CP0 running at full speed 206 * - when changing CPU speed do it as close to taking the time from CP0 as 207 * possible to keep the period of time we spend with CP0 running at the 208 * wrong frequency as short as possible - hopefully short enough to stay 209 * insignificant compared to other noise since switching speeds isn't 210 * going to happen all that often 211 */ 212 213 void 214 mips3_clockintr(struct clockframe *cf) 215 { 216 uint32_t now, diff, next, new_cnt; 217 218 /* 219 * this looks kinda funny but what we want here is this: 220 * - reading the counter and changing the CPU clock should be as 221 * close together as possible in order to remain halfway accurate 222 * - we need to use the previous sc_step in order to scale the 223 * interval passed since the last clock interrupt correctly, so 224 * we only change sc_step after doing that 225 */ 226 if (sc_step_wanted != sc_step) { 227 228 REGVAL(LS2F_CHIPCFG0) = 229 (REGVAL(LS2F_CHIPCFG0) & ~LS2FCFG_FREQSCALE_MASK) | 230 sc_step_wanted; 231 } 232 233 now = mips3_cp0_count_read(); 234 diff = now - sc_last; 235 sc_count += scale(diff, sc_step); 236 sc_last = now; 237 if (sc_step_wanted != sc_step) { 238 sc_step = sc_step_wanted; 239 curcpu()->ci_cycles_per_hz = cycles[sc_step]; 240 } 241 next = now + curcpu()->ci_cycles_per_hz; 242 curcpu()->ci_ev_count_compare.ev_count++; 243 244 mips3_cp0_compare_write(next); 245 246 /* Check for lost clock interrupts */ 247 new_cnt = mips3_cp0_count_read(); 248 249 /* 250 * Missed one or more clock interrupts, so let's start 251 * counting again from the current value. 252 */ 253 if ((next - new_cnt) & 0x80000000) { 254 255 next = new_cnt + curcpu()->ci_cycles_per_hz; 256 mips3_cp0_compare_write(next); 257 curcpu()->ci_ev_count_compare_missed.ev_count++; 258 } 259 260 hardclock(cf); 261 } 262 263 static u_int 264 get_loongson_timecount(struct timecounter *tc) 265 { 266 uint32_t now, diff; 267 268 now = mips3_cp0_count_read(); 269 diff = now - sc_last; 270 return sc_count + scale(diff, sc_step); 271 } 272 273 static int 274 loongson_cpuspeed_temp(SYSCTLFN_ARGS) 275 { 276 struct sysctlnode node = *rnode; 277 int mhz, i; 278 279 mhz = sc_scale[sc_step_wanted]; 280 281 node.sysctl_data = &mhz; 282 if (sysctl_lookup(SYSCTLFN_CALL(&node)) == 0) { 283 int new_reg; 284 285 new_reg = *(int *)node.sysctl_data; 286 i = 1; 287 while ((i < 8) && (sc_scale[i] != new_reg)) 288 i++; 289 if (i > 7) 290 return EINVAL; 291 loongson_set_speed(i); 292 return 0; 293 } 294 return EINVAL; 295 } 296 297 static int 298 loongson_cpuspeed_cur(SYSCTLFN_ARGS) 299 { 300 struct sysctlnode node = *rnode; 301 int mhz; 302 303 mhz = sc_scale[sc_step]; 304 node.sysctl_data = &mhz; 305 return sysctl_lookup(SYSCTLFN_CALL(&node)); 306 } 307 308 static int 309 loongson_cpuspeed_available(SYSCTLFN_ARGS) 310 { 311 struct sysctlnode node = *rnode; 312 char buf[128]; 313 314 snprintf(buf, 128, "%d %d %d %d %d %d %d", sc_scale[1], 315 sc_scale[2], sc_scale[3], sc_scale[4], 316 sc_scale[5], sc_scale[6], sc_scale[7]); 317 node.sysctl_data = buf; 318 return(sysctl_lookup(SYSCTLFN_CALL(&node))); 319 } 320 321 /* 322 * Wait for at least "n" microseconds. 323 */ 324 void 325 loongson_delay(int n) 326 { 327 u_long divisor_delay; 328 uint32_t cur, last, delta, usecs; 329 330 last = mips3_cp0_count_read(); 331 delta = usecs = 0; 332 333 divisor_delay = rscale(curcpu()->ci_divisor_delay, sc_step); 334 if (divisor_delay == 0) { 335 /* 336 * Frequency values in curcpu() are not initialized. 337 * Assume faster frequency since longer delays are harmless. 338 * Note CPU_MIPS_DOUBLE_COUNT is ignored here. 339 */ 340 #define FAST_FREQ (300 * 1000 * 1000) /* fast enough? */ 341 divisor_delay = FAST_FREQ / (1000 * 1000); 342 } 343 344 while (n > usecs) { 345 cur = mips3_cp0_count_read(); 346 347 /* 348 * The MIPS3 CP0 counter always counts upto UINT32_MAX, 349 * so no need to check wrapped around case. 350 */ 351 delta += (cur - last); 352 353 last = cur; 354 355 while (delta >= divisor_delay) { 356 /* 357 * delta is not so larger than divisor_delay here, 358 * and using DIV/DIVU ops could be much slower. 359 * (though longer delay may be harmless) 360 */ 361 usecs++; 362 delta -= divisor_delay; 363 } 364 } 365 } 366 367 SYSCTL_SETUP(sysctl_ams_setup, "sysctl obio subtree setup") 368 { 369 370 sysctl_createv(NULL, 0, NULL, NULL, 371 CTLFLAG_PERMANENT, 372 CTLTYPE_NODE, "machdep", NULL, 373 NULL, 0, NULL, 0, 374 CTL_MACHDEP, CTL_EOL); 375 } 376 377 /* 378 * We assume newhz is either stathz or profhz, and that neither will 379 * change after being set up above. Could recalculate intervals here 380 * but that would be a drag. 381 */ 382 void 383 loongson_setstatclockrate(int newhz) 384 { 385 386 /* nothing we can do */ 387 } 388 389 __weak_alias(setstatclockrate, loongson_setstatclockrate); 390 __weak_alias(cpu_initclocks, loongson_initclocks); 391 __weak_alias(delay, loongson_delay);
Indexes created Sat Oct 25 16:10:12 GMT 2025