gtreg.h revision 1.1.34.1
1 1.1.34.1 yamt /* $NetBSD: gtreg.h,v 1.1.34.1 2006/06/21 14:51:03 yamt Exp $ */ 2 1.1 simonb 3 1.1.34.1 yamt #define GT_REGVAL(x) *((volatile u_int32_t *) \ 4 1.1 simonb (MIPS_PHYS_TO_KSEG1(MALTA_CORECTRL_BASE + (x)))) 5 1.1 simonb 6 1.1 simonb /* CPU Configuration Register Map */ 7 1.1 simonb #define GT_CPU_INT 0x000 8 1.1 simonb #define GT_MULTIGT 0x120 9 1.1 simonb 10 1.1 simonb /* CPU Address Decode Register Map */ 11 1.1 simonb 12 1.1 simonb /* CPU Error Report Register Map */ 13 1.1 simonb 14 1.1 simonb /* CPU Sync Barrier Register Map */ 15 1.1 simonb 16 1.1 simonb /* SDRAM and Device Address Decode Register Map */ 17 1.1 simonb 18 1.1 simonb /* SDRAM Configuration Register Map */ 19 1.1 simonb 20 1.1 simonb /* SDRAM Parameters Register Map */ 21 1.1 simonb 22 1.1 simonb /* ECC Register Map */ 23 1.1 simonb 24 1.1 simonb /* Device Parameters Register Map */ 25 1.1 simonb 26 1.1 simonb /* DMA Record Register Map */ 27 1.1 simonb 28 1.1 simonb /* DMA Arbiter Register Map */ 29 1.1 simonb 30 1.1 simonb /* Timer/Counter Register Map */ 31 1.1 simonb //#define GT_TC_0 0x850 32 1.1 simonb //#define GT_TC_1 0x854 33 1.1 simonb //#define GT_TC_2 0x858 34 1.1 simonb //#define GT_TC_3 0x85c 35 1.1 simonb //#define GT_TC_CONTROL 0x864 36 1.1 simonb 37 1.1 simonb /* PCI Internal Register Map */ 38 1.1 simonb #define GT_PCI0_CFG_ADDR 0xcf8 39 1.1 simonb #define GT_PCI0_CFG_DATA 0xcfc 40 1.1 simonb #define GT_PCI0_INTR_ACK 0xc34 41 1.1 simonb 42 1.1 simonb /* Interrupts Register Map */ 43 1.1 simonb #define GT_INTR_CAUSE 0xc18 44 1.1 simonb #define GTIC_INTSUM 0x00000001 45 1.1 simonb #define GTIC_MEMOUT 0x00000002 46 1.1 simonb #define GTIC_DMAOUT 0x00000004 47 1.1 simonb #define GTIC_CPUOUT 0x00000008 48 1.1 simonb #define GTIC_DMA0COMP 0x00000010 49 1.1 simonb #define GTIC_DMA1COMP 0x00000020 50 1.1 simonb #define GTIC_DMA2COMP 0x00000040 51 1.1 simonb #define GTIC_DMA3COMP 0x00000080 52 1.1 simonb #define GTIC_T0EXP 0x00000100 53 1.1 simonb #define GTIC_T1EXP 0x00000200 54 1.1 simonb #define GTIC_T2EXP 0x00000400 55 1.1 simonb #define GTIC_T3EXP 0x00000800 56 1.1 simonb #define GTIC_MASRDERR0 0x00001000 57 1.1 simonb #define GTIC_SLVWRERR0 0x00002000 58 1.1 simonb #define GTIC_MASWRERR0 0x00004000 59 1.1 simonb #define GTIC_SLVRDERR0 0x00008000 60 1.1 simonb #define GTIC_ADDRERR0 0x00010000 61 1.1 simonb #define GTIC_MEMERR 0x00020000 62 1.1 simonb #define GTIC_MASABORT0 0x00040000 63 1.1 simonb #define GTIC_TARABORT0 0x00080000 64 1.1 simonb #define GTIC_RETRYCNT0 0x00100000 65 1.1 simonb #define GTIC_PMCINT_0 0x00200000 66 1.1 simonb #define GTIC_CPUINT 0x0c300000 67 1.1 simonb #define GTIC_PCINT 0xc3000000 68 1.1 simonb #define GTIC_CPUINTSUM 0x40000000 69 1.1 simonb #define GTIC_PCIINTSUM 0x80000000 70 1.1 simonb 71 1.1 simonb /* PCI Configuration Register Map */ 72 1.1 simonb //#define GT_PCICONFIGBASE 0 73 1.1 simonb //#define GT_PCIDID BONITO(GT_PCICONFIGBASE + 0x00) 74 1.1 simonb //#define GT_PCICMD BONITO(GT_PCICONFIGBASE + 0x04) 75 1.1 simonb //#define GT_PCICLASS BONITO(GT_PCICONFIGBASE + 0x08) 76 1.1 simonb //#define GT_PCILTIMER BONITO(GT_PCICONFIGBASE + 0x0c) 77 1.1 simonb //#define GT_PCIBASE0 BONITO(GT_PCICONFIGBASE + 0x10) 78 1.1 simonb //#define GT_PCIBASE1 BONITO(GT_PCICONFIGBASE + 0x14) 79 1.1 simonb //#define GT_PCIBASE2 BONITO(GT_PCICONFIGBASE + 0x18) 80 1.1 simonb //#define GT_PCIEXPRBASE BONITO(GT_PCICONFIGBASE + 0x30) 81 1.1 simonb //#define GT_PCIINT BONITO(GT_PCICONFIGBASE + 0x3c) 82 1.1 simonb 83 1.1 simonb /* PCI Configuration, Function 1, Register Map */ 84 1.1 simonb 85 1.1 simonb /* I2O Support Register Map */ 86
Indexes created Tue Oct 28 02:10:10 GMT 2025