mainbus.c revision 1.17
11.17Sthorpej/*	$NetBSD: mainbus.c,v 1.17 2021/08/07 16:18:51 thorpej Exp $	*/
21.1Ssimonb
31.1Ssimonb/*
41.1Ssimonb * Copyright 2002 Wasabi Systems, Inc.
51.1Ssimonb * All rights reserved.
61.1Ssimonb *
71.1Ssimonb * Written by Simon Burge for Wasabi Systems, Inc.
81.1Ssimonb *
91.1Ssimonb * Redistribution and use in source and binary forms, with or without
101.1Ssimonb * modification, are permitted provided that the following conditions
111.1Ssimonb * are met:
121.1Ssimonb * 1. Redistributions of source code must retain the above copyright
131.1Ssimonb *    notice, this list of conditions and the following disclaimer.
141.1Ssimonb * 2. Redistributions in binary form must reproduce the above copyright
151.1Ssimonb *    notice, this list of conditions and the following disclaimer in the
161.1Ssimonb *    documentation and/or other materials provided with the distribution.
171.1Ssimonb * 3. All advertising materials mentioning features or use of this software
181.1Ssimonb *    must display the following acknowledgement:
191.1Ssimonb *      This product includes software developed for the NetBSD Project by
201.1Ssimonb *      Wasabi Systems, Inc.
211.1Ssimonb * 4. The name of Wasabi Systems, Inc. may not be used to endorse
221.1Ssimonb *    or promote products derived from this software without specific prior
231.1Ssimonb *    written permission.
241.1Ssimonb *
251.1Ssimonb * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
261.1Ssimonb * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
271.1Ssimonb * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
281.1Ssimonb * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL WASABI SYSTEMS, INC
291.1Ssimonb * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
301.1Ssimonb * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
311.1Ssimonb * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
321.1Ssimonb * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
331.1Ssimonb * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
341.1Ssimonb * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
351.1Ssimonb * POSSIBILITY OF SUCH DAMAGE.
361.1Ssimonb */
371.7Slukem
381.7Slukem#include <sys/cdefs.h>
391.17Sthorpej__KERNEL_RCSID(0, "$NetBSD: mainbus.c,v 1.17 2021/08/07 16:18:51 thorpej Exp $");
401.1Ssimonb
411.1Ssimonb#include "opt_pci.h"
421.1Ssimonb
431.1Ssimonb#include <sys/param.h>
441.1Ssimonb#include <sys/systm.h>
451.1Ssimonb#include <sys/device.h>
461.1Ssimonb#if defined(PCI_NETBSD_CONFIGURE)
471.1Ssimonb#include <sys/malloc.h>
481.1Ssimonb#endif
491.1Ssimonb
501.1Ssimonb#include <dev/pci/pcivar.h>
511.1Ssimonb#if defined(PCI_NETBSD_CONFIGURE)
521.1Ssimonb#include <dev/pci/pciconf.h>
531.1Ssimonb#endif
541.1Ssimonb
551.1Ssimonb#include <mips/cache.h>
561.1Ssimonb#include <mips/cpuregs.h>
571.1Ssimonb
581.1Ssimonb#include <evbmips/malta/autoconf.h>
591.1Ssimonb#include <evbmips/malta/maltareg.h>
601.1Ssimonb#include <evbmips/malta/maltavar.h>
611.1Ssimonb
621.1Ssimonb#if defined(PCI_NETBSD_ENABLE_IDE)
631.1Ssimonb#include <dev/pci/pciide_piix_reg.h>
641.1Ssimonb#endif /* PCI_NETBSD_ENABLE_IDE */
651.1Ssimonb
661.1Ssimonb#include "locators.h"
671.1Ssimonb#include "pci.h"
681.1Ssimonb
691.12Smattstatic int	mainbus_match(device_t, cfdata_t, void *);
701.12Smattstatic void	mainbus_attach(device_t, device_t, void *);
711.12Smattstatic int	mainbus_submatch(device_t, cfdata_t, const int *, void *);
721.1Ssimonbstatic int	mainbus_print(void *, const char *);
731.1Ssimonb
741.12SmattCFATTACH_DECL_NEW(mainbus, 0,
751.5Sthorpej    mainbus_match, mainbus_attach, NULL, NULL);
761.1Ssimonb
771.1Ssimonb/* There can be only one. */
781.12Smattbool mainbus_found;
791.1Ssimonb
801.1Ssimonbstruct mainbusdev {
811.1Ssimonb	const char *md_name;
821.1Ssimonb	bus_addr_t md_addr;
831.1Ssimonb	int md_intr;
841.1Ssimonb};
851.1Ssimonb
861.12Smattconst struct mainbusdev mainbusdevs[] = {
871.1Ssimonb	{ "cpu",		-1,			-1 },
881.1Ssimonb	{ "gt",			MALTA_CORECTRL_BASE,	-1 },
891.1Ssimonb	{ "com",		MALTA_CBUSUART,		MALTA_CBUSUART_INTR },
901.1Ssimonb	{ "i2c",		MALTA_I2C_BASE,		-1 },
911.1Ssimonb	{ "gpio",		MALTA_GPIO_BASE,	-1 },
921.1Ssimonb	{ NULL,			0,			0 },
931.1Ssimonb};
941.1Ssimonb
951.15Sthorpej#define	PCI_IO_START	0x00001000
961.15Sthorpej#define	PCI_IO_END	0x0000efff
971.15Sthorpej#define	PCI_IO_SIZE	((PCI_IO_END - PCI_IO_START) + 1)
981.15Sthorpej
991.15Sthorpej#define	PCI_MEM_START	MALTA_PCIMEM1_BASE
1001.15Sthorpej#define	PCI_MEM_SIZE	MALTA_PCIMEM1_SIZE
1011.15Sthorpej
1021.1Ssimonbstatic int
1031.12Smattmainbus_match(device_t parent, cfdata_t match, void *aux)
1041.1Ssimonb{
1051.1Ssimonb
1061.1Ssimonb	if (mainbus_found)
1071.1Ssimonb		return (0);
1081.1Ssimonb
1091.1Ssimonb	return (1);
1101.1Ssimonb}
1111.1Ssimonb
1121.1Ssimonbstatic void
1131.12Smattmainbus_attach(device_t parent, device_t self, void *aux)
1141.1Ssimonb{
1151.1Ssimonb	struct mainbus_attach_args ma;
1161.12Smatt	const struct mainbusdev *md;
1171.13Sskrll#if defined(PCI_NETBSD_ENABLE_IDE) || defined(PCI_NETBSD_CONFIGURE)
1181.13Sskrll	struct malta_config *mcp = &malta_configuration;
1191.13Sskrll	pci_chipset_tag_t pc = &mcp->mc_pc;
1201.1Ssimonb#endif
1211.1Ssimonb
1221.12Smatt	mainbus_found = true;
1231.1Ssimonb	printf("\n");
1241.1Ssimonb
1251.1Ssimonb#if defined(PCI_NETBSD_CONFIGURE)
1261.13Sskrll	struct mips_cache_info * const mci = &mips_cache_info;
1271.15Sthorpej	struct pciconf_resources *pcires = pciconf_resource_init();
1281.15Sthorpej
1291.15Sthorpej	pciconf_resource_add(pcires, PCICONF_RESOURCE_IO,
1301.15Sthorpej	    PCI_IO_START, PCI_IO_SIZE);
1311.15Sthorpej	pciconf_resource_add(pcires, PCICONF_RESOURCE_MEM,
1321.15Sthorpej	    PCI_MEM_START, PCI_MEM_SIZE);
1331.13Sskrll
1341.15Sthorpej	pci_configure_bus(pc, pcires, 0, mci->mci_dcache_align);
1351.15Sthorpej	pciconf_resource_fini(pcires);
1361.1Ssimonb#endif /* PCI_NETBSD_CONFIGURE */
1371.1Ssimonb
1381.1Ssimonb#if defined(PCI_NETBSD_ENABLE_IDE)
1391.1Ssimonb	/*
1401.1Ssimonb	 * Perhaps PMON has not enabled the IDE controller.  Easy to
1411.1Ssimonb	 * fix -- just set the ENABLE bits for each channel in the
1421.1Ssimonb	 * IDETIM register.  Just clear all the bits for the channel
1431.1Ssimonb	 * except for the ENABLE bits -- the `pciide' driver will
1441.1Ssimonb	 * properly configure it later.
1451.1Ssimonb	 */
1461.15Sthorpej	pcireg_t idetim = 0;
1471.1Ssimonb	if (PCI_NETBSD_ENABLE_IDE & 0x01)
1481.1Ssimonb		idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE, 0);
1491.1Ssimonb	if (PCI_NETBSD_ENABLE_IDE & 0x02)
1501.1Ssimonb		idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE, 1);
1511.1Ssimonb
1521.1Ssimonb	/* pciide0 is pci device 10, function 1 */
1531.15Sthorpej	pcitag_t idetag = pci_make_tag(pc, 0, 10, 1);
1541.1Ssimonb	pci_conf_write(pc, idetag, PIIX_IDETIM, idetim);
1551.1Ssimonb#endif
1561.1Ssimonb	for (md = mainbusdevs; md->md_name != NULL; md++) {
1571.1Ssimonb		ma.ma_name = md->md_name;
1581.1Ssimonb		ma.ma_addr = md->md_addr;
1591.1Ssimonb		ma.ma_intr = md->md_intr;
1601.16Sthorpej		config_found(self, &ma, mainbus_print,
1611.17Sthorpej		    CFARGS(.submatch = mainbus_submatch));
1621.1Ssimonb	}
1631.1Ssimonb}
1641.1Ssimonb
1651.1Ssimonbstatic int
1661.12Smattmainbus_submatch(device_t parent, cfdata_t cf,
1671.9Sdrochner		 const int *ldesc, void *aux)
1681.1Ssimonb{
1691.1Ssimonb	struct mainbus_attach_args *ma = aux;
1701.1Ssimonb
1711.1Ssimonb	if (cf->cf_loc[MAINBUSCF_ADDR] != MAINBUSCF_ADDR_DEFAULT &&
1721.1Ssimonb	    cf->cf_loc[MAINBUSCF_ADDR] != ma->ma_addr)
1731.1Ssimonb		return (0);
1741.1Ssimonb
1751.2Sthorpej	return (config_match(parent, cf, aux));
1761.1Ssimonb}
1771.1Ssimonb
1781.1Ssimonbstatic int
1791.1Ssimonbmainbus_print(void *aux, const char *pnp)
1801.1Ssimonb{
1811.1Ssimonb	struct mainbus_attach_args *ma = aux;
1821.1Ssimonb
1831.1Ssimonb	if (pnp != 0)
1841.1Ssimonb		return QUIET;
1851.1Ssimonb
1861.1Ssimonb	if (pnp)
1871.6Sthorpej		aprint_normal("%s at %s", ma->ma_name, pnp);
1881.1Ssimonb	if (ma->ma_addr != MAINBUSCF_ADDR_DEFAULT)
1891.6Sthorpej		aprint_normal(" addr 0x%lx", ma->ma_addr);
1901.1Ssimonb
1911.1Ssimonb	return (UNCONF);
1921.1Ssimonb}
193