malta_intr.c revision 1.1
1 /* $NetBSD: malta_intr.c,v 1.1 2002/03/07 14:44:04 simonb Exp $ */ 2 3 /* 4 * Copyright 2001, 2002 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Jason R. Thorpe and Simon Burge for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 /* 39 * Platform-specific interrupt support for the MIPS Malta. 40 */ 41 42 43 #include <sys/param.h> 44 #include <sys/device.h> 45 #include <sys/kernel.h> 46 #include <sys/malloc.h> 47 48 #include <mips/locore.h> 49 50 #include <evbmips/evbmips/clockvar.h> 51 52 #include <evbmips/malta/maltavar.h> 53 #include <evbmips/malta/pci/pcibvar.h> 54 55 #include <dev/ic/mc146818reg.h> /* for malta_cal_timer() */ 56 57 #include <dev/isa/isavar.h> 58 #include <dev/pci/pciidereg.h> 59 60 /* 61 * This is a mask of bits to clear in the SR when we go to a 62 * given hardware interrupt priority level. 63 */ 64 const u_int32_t ipl_sr_bits[_IPL_N] = { 65 0, /* IPL_NONE */ 66 67 MIPS_SOFT_INT_MASK_0, /* IPL_SOFT */ 68 69 MIPS_SOFT_INT_MASK_0, /* IPL_SOFTCLOCK */ 70 71 MIPS_SOFT_INT_MASK_0| 72 MIPS_SOFT_INT_MASK_1, /* IPL_SOFTNET */ 73 74 MIPS_SOFT_INT_MASK_0| 75 MIPS_SOFT_INT_MASK_1, /* IPL_SOFTSERIAL */ 76 77 MIPS_SOFT_INT_MASK_0| 78 MIPS_SOFT_INT_MASK_1| 79 MIPS_INT_MASK_0, /* IPL_BIO */ 80 81 MIPS_SOFT_INT_MASK_0| 82 MIPS_SOFT_INT_MASK_1| 83 MIPS_INT_MASK_0, /* IPL_NET */ 84 85 MIPS_SOFT_INT_MASK_0| 86 MIPS_SOFT_INT_MASK_1| 87 MIPS_INT_MASK_0, /* IPL_{TTY,SERIAL} */ 88 89 MIPS_SOFT_INT_MASK_0| 90 MIPS_SOFT_INT_MASK_1| 91 MIPS_INT_MASK_0| 92 MIPS_INT_MASK_1| 93 MIPS_INT_MASK_2| 94 MIPS_INT_MASK_3| 95 MIPS_INT_MASK_4| 96 MIPS_INT_MASK_5, /* IPL_{CLOCK,HIGH} */ 97 }; 98 99 struct malta_cpuintr { 100 LIST_HEAD(, evbmips_intrhand) cintr_list; 101 struct evcnt cintr_count; 102 }; 103 #define NINTRS 5 /* MIPS INT0 - INT4 */ 104 105 struct malta_cpuintr malta_cpuintrs[NINTRS]; 106 const char *malta_cpuintrnames[NINTRS] = { 107 "int 0 (piix4)", 108 "int 1 (smi)", 109 "int 2 (uart)", 110 "int 3 (core hi/gt64120)", 111 "int 4 (core lo)", 112 }; 113 114 static int malta_pci_intr_map(struct pci_attach_args *, pci_intr_handle_t *); 115 static const char 116 *malta_pci_intr_string(void *, pci_intr_handle_t); 117 static const struct evcnt 118 *malta_pci_intr_evcnt(void *, pci_intr_handle_t); 119 static void *malta_pci_intr_establish(void *, pci_intr_handle_t, int, 120 int (*)(void *), void *); 121 static void malta_pci_intr_disestablish(void *, void *); 122 static void malta_pci_conf_interrupt(void *, int, int, int, int, int *); 123 static void *malta_pciide_compat_intr_establish(void *, struct device *, 124 struct pci_attach_args *, int, int (*)(void *), void *); 125 126 void 127 evbmips_intr_init(void) 128 { 129 struct malta_config *mcp = &malta_configuration; 130 int i; 131 132 for (i = 0; i < NINTRS; i++) { 133 LIST_INIT(&malta_cpuintrs[i].cintr_list); 134 evcnt_attach_dynamic(&malta_cpuintrs[i].cintr_count, 135 EVCNT_TYPE_INTR, NULL, "mips", malta_cpuintrnames[i]); 136 } 137 138 evcnt_attach_static(&mips_int5_evcnt); 139 140 mcp->mc_pc.pc_intr_v = NULL; 141 mcp->mc_pc.pc_intr_map = malta_pci_intr_map; 142 mcp->mc_pc.pc_intr_string = malta_pci_intr_string; 143 mcp->mc_pc.pc_intr_evcnt = malta_pci_intr_evcnt; 144 mcp->mc_pc.pc_intr_establish = malta_pci_intr_establish; 145 mcp->mc_pc.pc_intr_disestablish = malta_pci_intr_disestablish; 146 mcp->mc_pc.pc_conf_interrupt = malta_pci_conf_interrupt; 147 mcp->mc_pc.pc_pciide_compat_intr_establish = 148 malta_pciide_compat_intr_establish; 149 } 150 151 void 152 malta_cal_timer(bus_space_tag_t st, bus_space_handle_t sh) 153 { 154 u_long ctrdiff[4], startctr, endctr; 155 u_int8_t regc; 156 int i; 157 158 /* Disable interrupts first. */ 159 bus_space_write_1(st, sh, 0, MC_REGB); 160 bus_space_write_1(st, sh, 1, MC_REGB_SQWE | MC_REGB_BINARY | 161 MC_REGB_24HR); 162 163 /* Initialize for 16Hz. */ 164 bus_space_write_1(st, sh, 0, MC_REGA); 165 bus_space_write_1(st, sh, 1, MC_BASE_32_KHz | MC_RATE_16_Hz); 166 167 /* Run the loop an extra time to prime the cache. */ 168 for (i = 0; i < 4; i++) { 169 // led_display('h', 'z', '0' + i, ' '); 170 171 /* Enable the interrupt. */ 172 bus_space_write_1(st, sh, 0, MC_REGB); 173 bus_space_write_1(st, sh, 1, MC_REGB_PIE | MC_REGB_SQWE | 174 MC_REGB_BINARY | MC_REGB_24HR); 175 176 /* Go to REGC. */ 177 bus_space_write_1(st, sh, 0, MC_REGC); 178 179 /* Wait for it to happen. */ 180 startctr = mips3_cp0_count_read(); 181 do { 182 regc = bus_space_read_1(st, sh, 1); 183 endctr = mips3_cp0_count_read(); 184 } while ((regc & MC_REGC_IRQF) == 0); 185 186 /* Already ACK'd. */ 187 188 /* Disable. */ 189 bus_space_write_1(st, sh, 0, MC_REGB); 190 bus_space_write_1(st, sh, 1, MC_REGB_SQWE | MC_REGB_BINARY | 191 MC_REGB_24HR); 192 193 ctrdiff[i] = endctr - startctr; 194 } 195 196 /* Compute the number of cycles per second. */ 197 curcpu()->ci_cpu_freq = ((ctrdiff[2] + ctrdiff[3]) / 2) * 16/*Hz*/; 198 199 /* Compute the number of ticks for hz. */ 200 curcpu()->ci_cycles_per_hz = curcpu()->ci_cpu_freq / hz; 201 202 /* Compute the delay divisor. */ 203 curcpu()->ci_divisor_delay = (curcpu()->ci_cpu_freq / 1000000) / 2; 204 205 #ifdef DEBUG 206 printf("Timer calibration: %lu cycles/sec [(%lu, %lu) * 16]\n", 207 curcpu()->ci_cpu_freq, ctrdiff[2], ctrdiff[3]); 208 #endif 209 } 210 211 void * 212 evbmips_intr_establish(int irq, int (*func)(void *), void *arg) 213 { 214 struct evbmips_intrhand *ih; 215 int s; 216 217 ih = malloc(sizeof(*ih), M_DEVBUF, M_NOWAIT); 218 if (ih == NULL) 219 return (NULL); 220 221 ih->ih_func = func; 222 ih->ih_arg = arg; 223 224 s = splhigh(); 225 226 /* 227 * Link it into the tables. 228 */ 229 LIST_INSERT_HEAD(&malta_cpuintrs[0].cintr_list, ih, ih_q); 230 231 /* XXX - should check that MIPS_INT_MASK_0 is set... */ 232 233 splx(s); 234 235 return (ih); 236 } 237 238 void 239 evbmips_intr_disestablish(void *arg) 240 { 241 struct evbmips_intrhand *ih = arg; 242 int s; 243 244 s = splhigh(); 245 246 /* 247 * First, remove it from the table. 248 */ 249 LIST_REMOVE(ih, ih_q); 250 251 /* XXX - disable MIPS_INT_MASK_0 if list is empty? */ 252 253 splx(s); 254 255 free(ih, M_DEVBUF); 256 } 257 258 void 259 evbmips_iointr(uint32_t status, uint32_t cause, uint32_t pc, uint32_t ipending) 260 { 261 struct evbmips_intrhand *ih; 262 263 /* Check for error interrupts (SMI, GT62140) */ 264 if (ipending & (MIPS_INT_MASK_1 | MIPS_INT_MASK_3)) { 265 if (ipending & MIPS_INT_MASK_1) 266 panic("piix4 SMI interrupt"); 267 if (ipending & MIPS_INT_MASK_3) 268 panic("gt62140 error interrupt"); 269 } 270 271 /* 272 * Read the interrupt pending registers, mask them with the 273 * ones we have enabled, and service them in order of decreasing 274 * priority. 275 */ 276 if (ipending & MIPS_INT_MASK_0) { 277 /* All interrupts are gated through MIPS HW interrupt 0 */ 278 malta_cpuintrs[0].cintr_count.ev_count++; 279 LIST_FOREACH(ih, &malta_cpuintrs[0].cintr_list, ih_q) 280 (*ih->ih_func)(ih->ih_arg); 281 cause &= ~MIPS_INT_MASK_0; 282 } 283 284 /* Re-enable anything that we have processed. */ 285 _splset(MIPS_SR_INT_IE | ((status & ~cause) & MIPS_HARD_INT_MASK)); 286 } 287 288 /* 289 * YAMON configures pa_intrline correctly (so far), so we trust it to DTRT 290 * in the future... 291 */ 292 #undef YAMON_IRQ_MAP_BAD 293 294 /* 295 * PCI interrupt support 296 */ 297 static int 298 malta_pci_intr_map(struct pci_attach_args *pa, pci_intr_handle_t *ihp) 299 { 300 #ifdef YAMON_IRQ_MAP_BAD 301 static const int pciirqmap[13/*device*/][4/*pin*/] = { 302 { -1, -1, -1, 11 }, /* 10: USB */ 303 { 10, -1, -1, -1 }, /* 11: Ethernet */ 304 { 11, -1, -1, -1 }, /* 12: Audio */ 305 { -1, -1, -1, -1 }, /* 13: not used */ 306 { -1, -1, -1, -1 }, /* 14: not used */ 307 { -1, -1, -1, -1 }, /* 15: not used */ 308 { -1, -1, -1, -1 }, /* 16: not used */ 309 { -1, -1, -1, -1 }, /* 17: Core card(?) */ 310 { 10, 10, 11, 11 }, /* 18: PCI Slot 1 */ 311 { 10, 11, 11, 10 }, /* 19: PCI Slot 2 */ 312 { 11, 11, 10, 10 }, /* 20: PCI Slot 3 */ 313 { 11, 10, 10, 11 }, /* 21: PCI Slot 4 */ 314 }; 315 int buspin, device, irq; 316 #else /* !YAMON_IRQ_MAP_BAD */ 317 int buspin; 318 #endif /* !YAMON_IRQ_MAP_BAD */ 319 320 buspin = pa->pa_intrpin; 321 322 if (buspin == 0) { 323 /* No IRQ used. */ 324 return (1); 325 } 326 327 if (buspin > 4) { 328 printf("malta_pci_intr_map: bad interrupt pin %d\n", buspin); 329 return (1); 330 } 331 332 #ifdef YAMON_IRQ_MAP_BAD 333 pci_decompose_tag(pa->pa_pc, pa->pa_intrtag, NULL, &device, NULL); 334 335 if (device < 10 || device > 21) { 336 printf("malta_pci_intr_map: bad device %d\n", device); 337 return (1); 338 } 339 340 irq = pciirqmap[device - 10][buspin - 1]; 341 if (irq == -1) { 342 printf("malta_pci_intr_map: no mapping for device %d pin %d\n", 343 device, buspin); 344 return (1); 345 } 346 347 *ihp = irq; 348 #else /* !YAMON_IRQ_MAP_BAD */ 349 *ihp = pa->pa_intrline; 350 #endif /* !YAMON_IRQ_MAP_BAD */ 351 return (0); 352 } 353 354 static const char * 355 malta_pci_intr_string(void *v, pci_intr_handle_t irq) 356 { 357 358 return (isa_intr_string(pcib_ic, irq)); 359 } 360 361 static const struct evcnt * 362 malta_pci_intr_evcnt(void *v, pci_intr_handle_t irq) 363 { 364 365 return (isa_intr_evcnt(pcib_ic, irq)); 366 } 367 368 static void * 369 malta_pci_intr_establish(void *v, pci_intr_handle_t irq, int level, 370 int (*func)(void *), void *arg) 371 { 372 373 return (isa_intr_establish(pcib_ic, irq, IST_LEVEL, level, func, arg)); 374 } 375 376 static void 377 malta_pci_intr_disestablish(void *v, void *arg) 378 { 379 380 return (isa_intr_disestablish(pcib_ic, arg)); 381 } 382 383 static void 384 malta_pci_conf_interrupt(void *v, int bus, int dev, int func, int swiz, 385 int *iline) 386 { 387 388 /* 389 * We actually don't need to do anything; everything is handled 390 * in pci_intr_map(). 391 */ 392 *iline = 0; 393 } 394 395 void * 396 malta_pciide_compat_intr_establish(void *v, struct device *dev, 397 struct pci_attach_args *pa, int chan, int (*func)(void *), void *arg) 398 { 399 pci_chipset_tag_t pc = pa->pa_pc; 400 void *cookie; 401 int bus, irq; 402 403 pci_decompose_tag(pc, pa->pa_tag, &bus, NULL, NULL); 404 405 /* 406 * If this isn't PCI bus #0, all bets are off. 407 */ 408 if (bus != 0) 409 return (NULL); 410 411 irq = PCIIDE_COMPAT_IRQ(chan); 412 cookie = isa_intr_establish(pcib_ic, irq, IST_EDGE, IPL_BIO, func, arg); 413 if (cookie == NULL) 414 return (NULL); 415 printf("%s: %s channel interrupting at %s\n", dev->dv_xname, 416 PCIIDE_CHANNEL_NAME(chan), malta_pci_intr_string(v, irq)); 417 return (cookie); 418 } 419
Indexes created Thu Oct 02 10:09:58 GMT 2025