malta_intr.c revision 1.19.16.3
1 /* $NetBSD: malta_intr.c,v 1.19.16.3 2010/02/15 07:37:36 matt Exp $ */ 2 3 /* 4 * Copyright 2001, 2002 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Jason R. Thorpe and Simon Burge for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 /* 39 * Platform-specific interrupt support for the MIPS Malta. 40 */ 41 42 #include <sys/cdefs.h> 43 __KERNEL_RCSID(0, "$NetBSD: malta_intr.c,v 1.19.16.3 2010/02/15 07:37:36 matt Exp $"); 44 45 #include <sys/param.h> 46 #include <sys/device.h> 47 #include <sys/kernel.h> 48 #include <sys/malloc.h> 49 #include <sys/systm.h> 50 #include <sys/cpu.h> 51 52 #include <mips/locore.h> 53 54 #include <evbmips/malta/maltavar.h> 55 #include <evbmips/malta/pci/pcibvar.h> 56 57 #include <dev/ic/mc146818reg.h> /* for malta_cal_timer() */ 58 59 #include <dev/isa/isavar.h> 60 #include <dev/pci/pciidereg.h> 61 62 /* 63 * This is a mask of bits to clear in the SR when we go to a 64 * given hardware interrupt priority level. 65 */ 66 const uint32_t ipl_sr_bits[_IPL_N] = { 67 [IPL_NONE] = 0, 68 [IPL_PREEMPT] = 0, 69 [IPL_SOFTCLOCK] = 70 MIPS_SOFT_INT_MASK_0, 71 [IPL_SOFTNET] = 72 MIPS_SOFT_INT_MASK_0 | 73 MIPS_SOFT_INT_MASK_1, 74 [IPL_VM] = 75 MIPS_SOFT_INT_MASK_0 | 76 MIPS_SOFT_INT_MASK_1 | 77 MIPS_INT_MASK_0, 78 [IPL_SCHED] = 79 MIPS_SOFT_INT_MASK_0 | 80 MIPS_SOFT_INT_MASK_1 | 81 MIPS_INT_MASK_0 | 82 MIPS_INT_MASK_1 | 83 MIPS_INT_MASK_2 | 84 MIPS_INT_MASK_3 | 85 MIPS_INT_MASK_4 | 86 MIPS_INT_MASK_5, 87 [IPL_HIGH] = 88 MIPS_SOFT_INT_MASK_0 | 89 MIPS_SOFT_INT_MASK_1 | 90 MIPS_INT_MASK_0 | 91 MIPS_INT_MASK_1 | 92 MIPS_INT_MASK_2 | 93 MIPS_INT_MASK_3 | 94 MIPS_INT_MASK_4 | 95 MIPS_INT_MASK_5, 96 }; 97 98 struct malta_cpuintr { 99 LIST_HEAD(, evbmips_intrhand) cintr_list; 100 struct evcnt cintr_count; 101 }; 102 #define NINTRS 5 /* MIPS INT0 - INT4 */ 103 104 struct malta_cpuintr malta_cpuintrs[NINTRS]; 105 const char * const malta_cpuintrnames[NINTRS] = { 106 "int 0 (piix4)", 107 "int 1 (smi)", 108 "int 2 (uart)", 109 "int 3 (core hi/gt64120)", 110 "int 4 (core lo)", 111 }; 112 113 static int malta_pci_intr_map(struct pci_attach_args *, pci_intr_handle_t *); 114 static const char 115 *malta_pci_intr_string(void *, pci_intr_handle_t); 116 static const struct evcnt 117 *malta_pci_intr_evcnt(void *, pci_intr_handle_t); 118 static void *malta_pci_intr_establish(void *, pci_intr_handle_t, int, 119 int (*)(void *), void *); 120 static void malta_pci_intr_disestablish(void *, void *); 121 static void malta_pci_conf_interrupt(void *, int, int, int, int, int *); 122 static void *malta_pciide_compat_intr_establish(void *, struct device *, 123 struct pci_attach_args *, int, int (*)(void *), void *); 124 125 void 126 evbmips_intr_init(void) 127 { 128 struct malta_config *mcp = &malta_configuration; 129 int i; 130 131 for (i = 0; i < NINTRS; i++) { 132 LIST_INIT(&malta_cpuintrs[i].cintr_list); 133 evcnt_attach_dynamic(&malta_cpuintrs[i].cintr_count, 134 EVCNT_TYPE_INTR, NULL, "mips", malta_cpuintrnames[i]); 135 } 136 137 mcp->mc_pc.pc_intr_v = NULL; 138 mcp->mc_pc.pc_intr_map = malta_pci_intr_map; 139 mcp->mc_pc.pc_intr_string = malta_pci_intr_string; 140 mcp->mc_pc.pc_intr_evcnt = malta_pci_intr_evcnt; 141 mcp->mc_pc.pc_intr_establish = malta_pci_intr_establish; 142 mcp->mc_pc.pc_intr_disestablish = malta_pci_intr_disestablish; 143 mcp->mc_pc.pc_conf_interrupt = malta_pci_conf_interrupt; 144 mcp->mc_pc.pc_pciide_compat_intr_establish = 145 malta_pciide_compat_intr_establish; 146 } 147 148 void 149 malta_cal_timer(bus_space_tag_t st, bus_space_handle_t sh) 150 { 151 struct cpu_info * const ci = curcpu(); 152 uint32_t ctrdiff[4], startctr, endctr; 153 uint8_t regc; 154 int i; 155 156 /* Disable interrupts first. */ 157 bus_space_write_1(st, sh, 0, MC_REGB); 158 bus_space_write_1(st, sh, 1, MC_REGB_SQWE | MC_REGB_BINARY | 159 MC_REGB_24HR); 160 161 /* Initialize for 16Hz. */ 162 bus_space_write_1(st, sh, 0, MC_REGA); 163 bus_space_write_1(st, sh, 1, MC_BASE_32_KHz | MC_RATE_16_Hz); 164 165 /* Run the loop an extra time to prime the cache. */ 166 for (i = 0; i < 4; i++) { 167 // led_display('h', 'z', '0' + i, ' '); 168 169 /* Enable the interrupt. */ 170 bus_space_write_1(st, sh, 0, MC_REGB); 171 bus_space_write_1(st, sh, 1, MC_REGB_PIE | MC_REGB_SQWE | 172 MC_REGB_BINARY | MC_REGB_24HR); 173 174 /* Go to REGC. */ 175 bus_space_write_1(st, sh, 0, MC_REGC); 176 177 /* Wait for it to happen. */ 178 startctr = mips3_cp0_count_read(); 179 do { 180 regc = bus_space_read_1(st, sh, 1); 181 endctr = mips3_cp0_count_read(); 182 } while ((regc & MC_REGC_IRQF) == 0); 183 184 /* Already ACK'd. */ 185 186 /* Disable. */ 187 bus_space_write_1(st, sh, 0, MC_REGB); 188 bus_space_write_1(st, sh, 1, MC_REGB_SQWE | MC_REGB_BINARY | 189 MC_REGB_24HR); 190 191 ctrdiff[i] = endctr - startctr; 192 } 193 194 /* Compute the number of cycles per second. */ 195 ci->ci_cpu_freq = ((ctrdiff[2] + ctrdiff[3]) / 2) * 16/*Hz*/; 196 197 /* Compute the number of ticks for hz. */ 198 ci->ci_cycles_per_hz = (ci->ci_cpu_freq + hz / 2) / hz; 199 200 /* Compute the delay divisor. */ 201 ci->ci_divisor_delay = ((ci->ci_cpu_freq + 500000) / 1000000); 202 203 /* 204 * Get correct cpu frequency if the CPU runs at twice the 205 * external/cp0-count frequency. 206 */ 207 ci->ci_cctr_freq = ci->ci_cpu_freq; 208 if (mips_options.mips_cpu_flags & CPU_MIPS_DOUBLE_COUNT) 209 ci->ci_cpu_freq *= 2; 210 211 #ifdef DEBUG 212 printf("Timer calibration: %lu cycles/sec [(%u, %u) * 16]\n", 213 ci->ci_cpu_freq, ctrdiff[2], ctrdiff[3]); 214 #endif 215 } 216 217 void * 218 evbmips_intr_establish(int irq, int (*func)(void *), void *arg) 219 { 220 struct evbmips_intrhand *ih; 221 int s; 222 223 ih = malloc(sizeof(*ih), M_DEVBUF, M_NOWAIT); 224 if (ih == NULL) 225 return (NULL); 226 227 ih->ih_func = func; 228 ih->ih_arg = arg; 229 230 s = splhigh(); 231 232 /* 233 * Link it into the tables. 234 */ 235 LIST_INSERT_HEAD(&malta_cpuintrs[0].cintr_list, ih, ih_q); 236 237 /* XXX - should check that MIPS_INT_MASK_0 is set... */ 238 239 splx(s); 240 241 return (ih); 242 } 243 244 void 245 evbmips_intr_disestablish(void *arg) 246 { 247 struct evbmips_intrhand *ih = arg; 248 int s; 249 250 s = splhigh(); 251 252 /* 253 * First, remove it from the table. 254 */ 255 LIST_REMOVE(ih, ih_q); 256 257 /* XXX - disable MIPS_INT_MASK_0 if list is empty? */ 258 259 splx(s); 260 261 free(ih, M_DEVBUF); 262 } 263 264 void 265 evbmips_iointr(int ipl, vaddr_t pc, uint32_t ipending) 266 { 267 268 /* Check for error interrupts (SMI, GT64120) */ 269 if (ipending & (MIPS_INT_MASK_1 | MIPS_INT_MASK_3)) { 270 if (ipending & MIPS_INT_MASK_1) 271 panic("piix4 SMI interrupt"); 272 if (ipending & MIPS_INT_MASK_3) 273 panic("gt64120 error interrupt"); 274 } 275 276 /* 277 * Read the interrupt pending registers, mask them with the 278 * ones we have enabled, and service them in order of decreasing 279 * priority. 280 */ 281 if (ipending & MIPS_INT_MASK_0) { 282 struct evbmips_intrhand *ih; 283 /* All interrupts are gated through MIPS HW interrupt 0 */ 284 malta_cpuintrs[0].cintr_count.ev_count++; 285 LIST_FOREACH(ih, &malta_cpuintrs[0].cintr_list, ih_q) 286 (*ih->ih_func)(ih->ih_arg); 287 } 288 } 289 290 /* 291 * YAMON configures pa_intrline correctly (so far), so we trust it to DTRT 292 * in the future... 293 */ 294 #undef YAMON_IRQ_MAP_BAD 295 296 /* 297 * PCI interrupt support 298 */ 299 static int 300 malta_pci_intr_map(struct pci_attach_args *pa, pci_intr_handle_t *ihp) 301 { 302 #ifdef YAMON_IRQ_MAP_BAD 303 static const int pciirqmap[12/*device*/][4/*pin*/] = { 304 { -1, -1, -1, 11 }, /* 10: USB */ 305 { 10, -1, -1, -1 }, /* 11: Ethernet */ 306 { 11, -1, -1, -1 }, /* 12: Audio */ 307 { -1, -1, -1, -1 }, /* 13: not used */ 308 { -1, -1, -1, -1 }, /* 14: not used */ 309 { -1, -1, -1, -1 }, /* 15: not used */ 310 { -1, -1, -1, -1 }, /* 16: not used */ 311 { -1, -1, -1, -1 }, /* 17: Core card(?) */ 312 { 10, 10, 11, 11 }, /* 18: PCI Slot 1 */ 313 { 10, 11, 11, 10 }, /* 19: PCI Slot 2 */ 314 { 11, 11, 10, 10 }, /* 20: PCI Slot 3 */ 315 { 11, 10, 10, 11 }, /* 21: PCI Slot 4 */ 316 }; 317 int buspin, device, irq; 318 #else /* !YAMON_IRQ_MAP_BAD */ 319 int buspin; 320 #endif /* !YAMON_IRQ_MAP_BAD */ 321 322 buspin = pa->pa_intrpin; 323 324 if (buspin == 0) { 325 /* No IRQ used. */ 326 return (1); 327 } 328 329 if (buspin > 4) { 330 printf("malta_pci_intr_map: bad interrupt pin %d\n", buspin); 331 return (1); 332 } 333 334 #ifdef YAMON_IRQ_MAP_BAD 335 pci_decompose_tag(pa->pa_pc, pa->pa_intrtag, NULL, &device, NULL); 336 337 if (device < 10 || device > 21) { 338 printf("malta_pci_intr_map: bad device %d\n", device); 339 return (1); 340 } 341 342 irq = pciirqmap[device - 10][buspin - 1]; 343 if (irq == -1) { 344 printf("malta_pci_intr_map: no mapping for device %d pin %d\n", 345 device, buspin); 346 return (1); 347 } 348 349 *ihp = irq; 350 #else /* !YAMON_IRQ_MAP_BAD */ 351 *ihp = pa->pa_intrline; 352 #endif /* !YAMON_IRQ_MAP_BAD */ 353 return (0); 354 } 355 356 static const char * 357 malta_pci_intr_string(void *v, pci_intr_handle_t irq) 358 { 359 360 return (isa_intr_string(pcib_ic, irq)); 361 } 362 363 static const struct evcnt * 364 malta_pci_intr_evcnt(void *v, pci_intr_handle_t irq) 365 { 366 367 return (isa_intr_evcnt(pcib_ic, irq)); 368 } 369 370 static void * 371 malta_pci_intr_establish(void *v, pci_intr_handle_t irq, int level, 372 int (*func)(void *), void *arg) 373 { 374 375 return (isa_intr_establish(pcib_ic, irq, IST_LEVEL, level, func, arg)); 376 } 377 378 static void 379 malta_pci_intr_disestablish(void *v, void *arg) 380 { 381 382 return (isa_intr_disestablish(pcib_ic, arg)); 383 } 384 385 static void 386 malta_pci_conf_interrupt(void *v, int bus, int dev, int func, int swiz, 387 int *iline) 388 { 389 390 /* 391 * We actually don't need to do anything; everything is handled 392 * in pci_intr_map(). 393 */ 394 *iline = 0; 395 } 396 397 void * 398 malta_pciide_compat_intr_establish(void *v, struct device *dev, 399 struct pci_attach_args *pa, int chan, int (*func)(void *), void *arg) 400 { 401 pci_chipset_tag_t pc = pa->pa_pc; 402 void *cookie; 403 int bus, irq; 404 405 pci_decompose_tag(pc, pa->pa_tag, &bus, NULL, NULL); 406 407 /* 408 * If this isn't PCI bus #0, all bets are off. 409 */ 410 if (bus != 0) 411 return (NULL); 412 413 irq = PCIIDE_COMPAT_IRQ(chan); 414 cookie = isa_intr_establish(pcib_ic, irq, IST_EDGE, IPL_BIO, func, arg); 415 if (cookie == NULL) 416 return (NULL); 417 printf("%s: %s channel interrupting at %s\n", dev->dv_xname, 418 PCIIDE_CHANNEL_NAME(chan), malta_pci_intr_string(v, irq)); 419 return (cookie); 420 } 421
Indexes created Thu Oct 30 23:09:54 GMT 2025