malta_intr.c revision 1.19.16.5
1 /* $NetBSD: malta_intr.c,v 1.19.16.5 2010/02/23 20:24:37 matt Exp $ */ 2 3 /* 4 * Copyright 2001, 2002 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Jason R. Thorpe and Simon Burge for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 /* 39 * Platform-specific interrupt support for the MIPS Malta. 40 */ 41 42 #include <sys/cdefs.h> 43 __KERNEL_RCSID(0, "$NetBSD: malta_intr.c,v 1.19.16.5 2010/02/23 20:24:37 matt Exp $"); 44 45 #include <sys/param.h> 46 #include <sys/device.h> 47 #include <sys/kernel.h> 48 #include <sys/malloc.h> 49 #include <sys/systm.h> 50 #include <sys/cpu.h> 51 52 #include <mips/locore.h> 53 54 #include <evbmips/malta/maltavar.h> 55 #include <evbmips/malta/pci/pcibvar.h> 56 57 #include <dev/ic/mc146818reg.h> /* for malta_cal_timer() */ 58 59 #include <dev/isa/isavar.h> 60 #include <dev/pci/pciidereg.h> 61 62 /* 63 * This is a mask of bits to clear in the SR when we go to a 64 * given hardware interrupt priority level. 65 */ 66 static const struct ipl_sr_map malta_ipl_sr_map = { 67 .sr_bits = { 68 [IPL_NONE] = 0, 69 [IPL_SOFTCLOCK] = MIPS_SOFT_INT_MASK_0, 70 [IPL_SOFTNET] = MIPS_SOFT_INT_MASK, 71 [IPL_VM] = MIPS_SOFT_INT_MASK | MIPS_INT_MASK_0, 72 [IPL_SCHED] = MIPS_INT_MASK, 73 [IPL_HIGH] = MIPS_INT_MASK, 74 }, 75 }; 76 77 struct malta_cpuintr { 78 LIST_HEAD(, evbmips_intrhand) cintr_list; 79 struct evcnt cintr_count; 80 }; 81 #define NINTRS 5 /* MIPS INT0 - INT4 */ 82 83 struct malta_cpuintr malta_cpuintrs[NINTRS]; 84 const char * const malta_cpuintrnames[NINTRS] = { 85 "int 0 (piix4)", 86 "int 1 (smi)", 87 "int 2 (uart)", 88 "int 3 (core hi/gt64120)", 89 "int 4 (core lo)", 90 }; 91 92 static int malta_pci_intr_map(struct pci_attach_args *, pci_intr_handle_t *); 93 static const char 94 *malta_pci_intr_string(void *, pci_intr_handle_t); 95 static const struct evcnt 96 *malta_pci_intr_evcnt(void *, pci_intr_handle_t); 97 static void *malta_pci_intr_establish(void *, pci_intr_handle_t, int, 98 int (*)(void *), void *); 99 static void malta_pci_intr_disestablish(void *, void *); 100 static void malta_pci_conf_interrupt(void *, int, int, int, int, int *); 101 static void *malta_pciide_compat_intr_establish(void *, struct device *, 102 struct pci_attach_args *, int, int (*)(void *), void *); 103 104 void 105 evbmips_intr_init(void) 106 { 107 struct malta_config * const mcp = &malta_configuration; 108 109 ipl_sr_map = malta_ipl_sr_map; 110 111 for (size_t i = 0; i < NINTRS; i++) { 112 LIST_INIT(&malta_cpuintrs[i].cintr_list); 113 evcnt_attach_dynamic(&malta_cpuintrs[i].cintr_count, 114 EVCNT_TYPE_INTR, NULL, "mips", malta_cpuintrnames[i]); 115 } 116 117 mcp->mc_pc.pc_intr_v = NULL; 118 mcp->mc_pc.pc_intr_map = malta_pci_intr_map; 119 mcp->mc_pc.pc_intr_string = malta_pci_intr_string; 120 mcp->mc_pc.pc_intr_evcnt = malta_pci_intr_evcnt; 121 mcp->mc_pc.pc_intr_establish = malta_pci_intr_establish; 122 mcp->mc_pc.pc_intr_disestablish = malta_pci_intr_disestablish; 123 mcp->mc_pc.pc_conf_interrupt = malta_pci_conf_interrupt; 124 mcp->mc_pc.pc_pciide_compat_intr_establish = 125 malta_pciide_compat_intr_establish; 126 } 127 128 void 129 malta_cal_timer(bus_space_tag_t st, bus_space_handle_t sh) 130 { 131 struct cpu_info * const ci = curcpu(); 132 uint32_t ctrdiff[4], startctr, endctr; 133 uint8_t regc; 134 int i; 135 136 /* Disable interrupts first. */ 137 bus_space_write_1(st, sh, 0, MC_REGB); 138 bus_space_write_1(st, sh, 1, MC_REGB_SQWE | MC_REGB_BINARY | 139 MC_REGB_24HR); 140 141 /* Initialize for 16Hz. */ 142 bus_space_write_1(st, sh, 0, MC_REGA); 143 bus_space_write_1(st, sh, 1, MC_BASE_32_KHz | MC_RATE_16_Hz); 144 145 /* Run the loop an extra time to prime the cache. */ 146 for (i = 0; i < 4; i++) { 147 // led_display('h', 'z', '0' + i, ' '); 148 149 /* Enable the interrupt. */ 150 bus_space_write_1(st, sh, 0, MC_REGB); 151 bus_space_write_1(st, sh, 1, MC_REGB_PIE | MC_REGB_SQWE | 152 MC_REGB_BINARY | MC_REGB_24HR); 153 154 /* Go to REGC. */ 155 bus_space_write_1(st, sh, 0, MC_REGC); 156 157 /* Wait for it to happen. */ 158 startctr = mips3_cp0_count_read(); 159 do { 160 regc = bus_space_read_1(st, sh, 1); 161 endctr = mips3_cp0_count_read(); 162 } while ((regc & MC_REGC_IRQF) == 0); 163 164 /* Already ACK'd. */ 165 166 /* Disable. */ 167 bus_space_write_1(st, sh, 0, MC_REGB); 168 bus_space_write_1(st, sh, 1, MC_REGB_SQWE | MC_REGB_BINARY | 169 MC_REGB_24HR); 170 171 ctrdiff[i] = endctr - startctr; 172 } 173 174 /* Compute the number of cycles per second. */ 175 ci->ci_cpu_freq = ((ctrdiff[2] + ctrdiff[3]) / 2) * 16/*Hz*/; 176 177 /* Compute the number of ticks for hz. */ 178 ci->ci_cycles_per_hz = (ci->ci_cpu_freq + hz / 2) / hz; 179 180 /* Compute the delay divisor. */ 181 ci->ci_divisor_delay = ((ci->ci_cpu_freq + 500000) / 1000000); 182 183 /* 184 * Get correct cpu frequency if the CPU runs at twice the 185 * external/cp0-count frequency. 186 */ 187 ci->ci_cctr_freq = ci->ci_cpu_freq; 188 if (mips_options.mips_cpu_flags & CPU_MIPS_DOUBLE_COUNT) 189 ci->ci_cpu_freq *= 2; 190 191 #ifdef DEBUG 192 printf("Timer calibration: %lu cycles/sec [(%u, %u) * 16]\n", 193 ci->ci_cpu_freq, ctrdiff[2], ctrdiff[3]); 194 #endif 195 } 196 197 void * 198 evbmips_intr_establish(int irq, int (*func)(void *), void *arg) 199 { 200 struct evbmips_intrhand *ih; 201 int s; 202 203 ih = malloc(sizeof(*ih), M_DEVBUF, M_NOWAIT); 204 if (ih == NULL) 205 return (NULL); 206 207 ih->ih_func = func; 208 ih->ih_arg = arg; 209 210 s = splhigh(); 211 212 /* 213 * Link it into the tables. 214 */ 215 LIST_INSERT_HEAD(&malta_cpuintrs[0].cintr_list, ih, ih_q); 216 217 /* XXX - should check that MIPS_INT_MASK_0 is set... */ 218 219 splx(s); 220 221 return (ih); 222 } 223 224 void 225 evbmips_intr_disestablish(void *arg) 226 { 227 struct evbmips_intrhand *ih = arg; 228 int s; 229 230 s = splhigh(); 231 232 /* 233 * First, remove it from the table. 234 */ 235 LIST_REMOVE(ih, ih_q); 236 237 /* XXX - disable MIPS_INT_MASK_0 if list is empty? */ 238 239 splx(s); 240 241 free(ih, M_DEVBUF); 242 } 243 244 void 245 evbmips_iointr(int ipl, vaddr_t pc, uint32_t ipending) 246 { 247 248 /* Check for error interrupts (SMI, GT64120) */ 249 if (ipending & (MIPS_INT_MASK_1 | MIPS_INT_MASK_3)) { 250 if (ipending & MIPS_INT_MASK_1) 251 panic("piix4 SMI interrupt"); 252 if (ipending & MIPS_INT_MASK_3) 253 panic("gt64120 error interrupt"); 254 } 255 256 /* 257 * Read the interrupt pending registers, mask them with the 258 * ones we have enabled, and service them in order of decreasing 259 * priority. 260 */ 261 if (ipending & MIPS_INT_MASK_0) { 262 struct evbmips_intrhand *ih; 263 /* All interrupts are gated through MIPS HW interrupt 0 */ 264 malta_cpuintrs[0].cintr_count.ev_count++; 265 LIST_FOREACH(ih, &malta_cpuintrs[0].cintr_list, ih_q) 266 (*ih->ih_func)(ih->ih_arg); 267 } 268 } 269 270 /* 271 * YAMON configures pa_intrline correctly (so far), so we trust it to DTRT 272 * in the future... 273 */ 274 #undef YAMON_IRQ_MAP_BAD 275 276 /* 277 * PCI interrupt support 278 */ 279 static int 280 malta_pci_intr_map(struct pci_attach_args *pa, pci_intr_handle_t *ihp) 281 { 282 #ifdef YAMON_IRQ_MAP_BAD 283 static const int pciirqmap[12/*device*/][4/*pin*/] = { 284 { -1, -1, -1, 11 }, /* 10: USB */ 285 { 10, -1, -1, -1 }, /* 11: Ethernet */ 286 { 11, -1, -1, -1 }, /* 12: Audio */ 287 { -1, -1, -1, -1 }, /* 13: not used */ 288 { -1, -1, -1, -1 }, /* 14: not used */ 289 { -1, -1, -1, -1 }, /* 15: not used */ 290 { -1, -1, -1, -1 }, /* 16: not used */ 291 { -1, -1, -1, -1 }, /* 17: Core card(?) */ 292 { 10, 10, 11, 11 }, /* 18: PCI Slot 1 */ 293 { 10, 11, 11, 10 }, /* 19: PCI Slot 2 */ 294 { 11, 11, 10, 10 }, /* 20: PCI Slot 3 */ 295 { 11, 10, 10, 11 }, /* 21: PCI Slot 4 */ 296 }; 297 int buspin, device, irq; 298 #else /* !YAMON_IRQ_MAP_BAD */ 299 int buspin; 300 #endif /* !YAMON_IRQ_MAP_BAD */ 301 302 buspin = pa->pa_intrpin; 303 304 if (buspin == 0) { 305 /* No IRQ used. */ 306 return (1); 307 } 308 309 if (buspin > 4) { 310 printf("malta_pci_intr_map: bad interrupt pin %d\n", buspin); 311 return (1); 312 } 313 314 #ifdef YAMON_IRQ_MAP_BAD 315 pci_decompose_tag(pa->pa_pc, pa->pa_intrtag, NULL, &device, NULL); 316 317 if (device < 10 || device > 21) { 318 printf("malta_pci_intr_map: bad device %d\n", device); 319 return (1); 320 } 321 322 irq = pciirqmap[device - 10][buspin - 1]; 323 if (irq == -1) { 324 printf("malta_pci_intr_map: no mapping for device %d pin %d\n", 325 device, buspin); 326 return (1); 327 } 328 329 *ihp = irq; 330 #else /* !YAMON_IRQ_MAP_BAD */ 331 *ihp = pa->pa_intrline; 332 #endif /* !YAMON_IRQ_MAP_BAD */ 333 return (0); 334 } 335 336 static const char * 337 malta_pci_intr_string(void *v, pci_intr_handle_t irq) 338 { 339 340 return (isa_intr_string(pcib_ic, irq)); 341 } 342 343 static const struct evcnt * 344 malta_pci_intr_evcnt(void *v, pci_intr_handle_t irq) 345 { 346 347 return (isa_intr_evcnt(pcib_ic, irq)); 348 } 349 350 static void * 351 malta_pci_intr_establish(void *v, pci_intr_handle_t irq, int level, 352 int (*func)(void *), void *arg) 353 { 354 355 return (isa_intr_establish(pcib_ic, irq, IST_LEVEL, level, func, arg)); 356 } 357 358 static void 359 malta_pci_intr_disestablish(void *v, void *arg) 360 { 361 362 return (isa_intr_disestablish(pcib_ic, arg)); 363 } 364 365 static void 366 malta_pci_conf_interrupt(void *v, int bus, int dev, int func, int swiz, 367 int *iline) 368 { 369 370 /* 371 * We actually don't need to do anything; everything is handled 372 * in pci_intr_map(). 373 */ 374 *iline = 0; 375 } 376 377 void * 378 malta_pciide_compat_intr_establish(void *v, struct device *dev, 379 struct pci_attach_args *pa, int chan, int (*func)(void *), void *arg) 380 { 381 pci_chipset_tag_t pc = pa->pa_pc; 382 void *cookie; 383 int bus, irq; 384 385 pci_decompose_tag(pc, pa->pa_tag, &bus, NULL, NULL); 386 387 /* 388 * If this isn't PCI bus #0, all bets are off. 389 */ 390 if (bus != 0) 391 return (NULL); 392 393 irq = PCIIDE_COMPAT_IRQ(chan); 394 cookie = isa_intr_establish(pcib_ic, irq, IST_EDGE, IPL_BIO, func, arg); 395 if (cookie == NULL) 396 return (NULL); 397 printf("%s: %s channel interrupting at %s\n", dev->dv_xname, 398 PCIIDE_CHANNEL_NAME(chan), malta_pci_intr_string(v, irq)); 399 return (cookie); 400 } 401
Indexes created Thu Oct 30 23:09:54 GMT 2025