pcib.c revision 1.3
1 /* $NetBSD: pcib.c,v 1.3 2002/09/27 15:36:01 provos Exp $ */ 2 3 /* 4 * Copyright 2002 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Simon Burge for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 #include <sys/param.h> 39 #include <sys/systm.h> 40 #include <sys/kernel.h> 41 #include <sys/device.h> 42 #include <sys/malloc.h> 43 44 #include <machine/bus.h> 45 #include <evbmips/malta/maltareg.h> 46 #include <evbmips/malta/maltavar.h> 47 #include <evbmips/malta/dev/gtreg.h> 48 #include <evbmips/malta/pci/pcibvar.h> 49 50 #include <dev/isa/isareg.h> 51 #include <dev/isa/isavar.h> 52 53 #include <dev/pci/pcireg.h> 54 #include <dev/pci/pcivar.h> 55 #include <dev/pci/pcidevs.h> 56 57 #include <dev/ic/i8259reg.h> 58 59 60 #define ICU_LEN 16 /* number of ISA IRQs */ 61 62 const char *isa_intrnames[ICU_LEN] = { 63 "timer", 64 "keyboard", 65 "reserved", /* by South Bridge (for cascading) */ 66 "com1", 67 "com0", 68 "not used", 69 "floppy", 70 "centronics", 71 "mcclock", 72 "i2c", 73 "pci A,B", /* PCI slots 1..4, ethernet */ 74 "pci C,D", /* PCI slots 1..4, audio, usb */ 75 "mouse", 76 "reserved", 77 "ide primary", 78 "ide secondary", /* and compact flash connector */ 79 }; 80 81 struct pcib_intrhead { 82 LIST_HEAD(, evbmips_intrhand) intr_q; 83 struct evcnt intr_count; 84 int intr_type; 85 }; 86 87 struct pcib_softc { 88 struct device sc_dev; 89 90 bus_space_tag_t sc_iot; 91 bus_space_handle_t sc_ioh_icu1; 92 bus_space_handle_t sc_ioh_icu2; 93 bus_space_handle_t sc_ioh_elcr; 94 95 struct mips_isa_chipset sc_ic; 96 97 struct pcib_intrhead sc_intrtab[ICU_LEN]; 98 99 u_int16_t sc_imask; 100 u_int16_t sc_elcr; 101 102 u_int16_t sc_reserved; 103 104 void *sc_ih; 105 }; 106 107 /* 108 * XXX 109 * There is only one pci-isa bridge, and all external interrupts 110 * are routed through it, so we need to remember the softc when 111 * called from other interrupt handling code. 112 */ 113 static struct pcib_softc *my_sc; 114 struct mips_isa_chipset *pcib_ic; 115 116 static int pcib_match(struct device *, struct cfdata *, void *); 117 static void pcib_attach(struct device *, struct device *, void *); 118 static int pcib_intr(void *v); 119 static void pcib_bridge_callback(struct device *); 120 static int pcib_print(void *, const char *); 121 static void pcib_set_icus(struct pcib_softc *sc); 122 static void pcib_cleanup(void *arg); 123 124 static const struct evcnt * 125 pcib_isa_intr_evcnt(void *, int); 126 static void *pcib_isa_intr_establish(void *, int, int, int, 127 int (*)(void *), void *); 128 static void pcib_isa_intr_disestablish(void *, void *); 129 static void pcib_isa_attach_hook(struct device *, struct device *, 130 struct isabus_attach_args *); 131 static int pcib_isa_intr_alloc(void *, int, int, int *); 132 static const char * 133 pcib_isa_intr_string(void *, int); 134 135 struct cfattach pcib_ca = { 136 sizeof(struct pcib_softc), pcib_match, pcib_attach 137 }; 138 139 static int 140 pcib_match(struct device *parent, struct cfdata *match, void *aux) 141 { 142 struct pci_attach_args *pa = aux; 143 144 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_BRIDGE && 145 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_BRIDGE_ISA) 146 return (1); 147 148 return (0); 149 } 150 151 static void 152 pcib_attach(struct device *parent, struct device *self, void *aux) 153 { 154 struct pci_attach_args *pa = aux; 155 char devinfo[256]; 156 int i; 157 158 printf("\n"); 159 160 if (my_sc != NULL) 161 panic("pcib_attach: already attached!"); 162 my_sc = (void *)self; 163 164 /* 165 * Just print out a description and defer configuration 166 * until all PCI devices have been attached. 167 */ 168 pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo); 169 printf("%s: %s, (rev . 0x%02x)\n", self->dv_xname, devinfo, 170 PCI_REVISION(pa->pa_class)); 171 172 my_sc->sc_iot = pa->pa_iot; 173 174 /* 175 * Map the PIC/ELCR registers. 176 */ 177 if (bus_space_map(my_sc->sc_iot, 0x4d0, 2, 0, &my_sc->sc_ioh_elcr) != 0) 178 printf("%s: unable to map ELCR registers\n", 179 my_sc->sc_dev.dv_xname); 180 if (bus_space_map(my_sc->sc_iot, IO_ICU1, 2, 0, &my_sc->sc_ioh_icu1) != 0) 181 printf("%s: unable to map ICU1 registers\n", 182 my_sc->sc_dev.dv_xname); 183 if (bus_space_map(my_sc->sc_iot, IO_ICU2, 2, 0, &my_sc->sc_ioh_icu2) != 0) 184 printf("%s: unable to map ICU2 registers\n", 185 my_sc->sc_dev.dv_xname); 186 187 /* All interrupts default to "masked off". */ 188 my_sc->sc_imask = 0xffff; 189 190 /* All interrupts default to edge-triggered. */ 191 my_sc->sc_elcr = 0; 192 193 /* 194 * Initialize the 8259s. 195 */ 196 /* reset, program device, 4 bytes */ 197 bus_space_write_1(my_sc->sc_iot, my_sc->sc_ioh_icu1, PIC_ICW1, 198 ICW1_SELECT | ICW1_IC4); 199 bus_space_write_1(my_sc->sc_iot, my_sc->sc_ioh_icu1, PIC_ICW2, 200 ICW2_VECTOR(0)/*XXX*/); 201 bus_space_write_1(my_sc->sc_iot, my_sc->sc_ioh_icu1, PIC_ICW3, 202 ICW3_CASCADE(2)); 203 bus_space_write_1(my_sc->sc_iot, my_sc->sc_ioh_icu1, PIC_ICW4, 204 ICW4_8086); 205 206 /* mask all interrupts */ 207 bus_space_write_1(my_sc->sc_iot, my_sc->sc_ioh_icu1, PIC_OCW1, 208 my_sc->sc_imask & 0xff); 209 210 /* enable special mask mode */ 211 bus_space_write_1(my_sc->sc_iot, my_sc->sc_ioh_icu1, PIC_OCW3, 212 OCW3_SELECT | OCW3_SSMM | OCW3_SMM); 213 214 /* read IRR by default */ 215 bus_space_write_1(my_sc->sc_iot, my_sc->sc_ioh_icu1, PIC_OCW3, 216 OCW3_SELECT | OCW3_RR); 217 218 /* reset, program device, 4 bytes */ 219 bus_space_write_1(my_sc->sc_iot, my_sc->sc_ioh_icu2, PIC_ICW1, 220 ICW1_SELECT | ICW1_IC4); 221 bus_space_write_1(my_sc->sc_iot, my_sc->sc_ioh_icu2, PIC_ICW2, 222 ICW2_VECTOR(0)/*XXX*/); 223 bus_space_write_1(my_sc->sc_iot, my_sc->sc_ioh_icu2, PIC_ICW3, 224 ICW3_CASCADE(2)); 225 bus_space_write_1(my_sc->sc_iot, my_sc->sc_ioh_icu2, PIC_ICW4, 226 ICW4_8086); 227 228 /* mask all interrupts */ 229 bus_space_write_1(my_sc->sc_iot, my_sc->sc_ioh_icu2, PIC_OCW1, 230 my_sc->sc_imask & 0xff); 231 232 /* enable special mask mode */ 233 bus_space_write_1(my_sc->sc_iot, my_sc->sc_ioh_icu2, PIC_OCW3, 234 OCW3_SELECT | OCW3_SSMM | OCW3_SMM); 235 236 /* read IRR by default */ 237 bus_space_write_1(my_sc->sc_iot, my_sc->sc_ioh_icu2, PIC_OCW3, 238 OCW3_SELECT | OCW3_RR); 239 240 /* 241 * Default all interrupts to edge-triggered. 242 */ 243 bus_space_write_1(my_sc->sc_iot, my_sc->sc_ioh_elcr, 0, 244 my_sc->sc_elcr & 0xff); 245 bus_space_write_1(my_sc->sc_iot, my_sc->sc_ioh_elcr, 1, 246 (my_sc->sc_elcr >> 8) & 0xff); 247 248 /* 249 * Some ISA interrupts are reserved for devices that 250 * we know are hard-wired to certain IRQs. 251 */ 252 my_sc->sc_reserved = 253 (1U << 0) | /* timer */ 254 (1U << 1) | /* keyboard controller (keyboard) */ 255 (1U << 2) | /* PIC cascade */ 256 (1U << 3) | /* COM 2 */ 257 (1U << 4) | /* COM 1 */ 258 (1U << 6) | /* floppy */ 259 (1U << 7) | /* centronics */ 260 (1U << 8) | /* RTC */ 261 (1U << 9) | /* I2C */ 262 (1U << 12) | /* keyboard controller (mouse) */ 263 (1U << 14) | /* IDE primary */ 264 (1U << 15); /* IDE secondary */ 265 266 /* Set up our ISA chipset. */ 267 my_sc->sc_ic.ic_v = my_sc; 268 my_sc->sc_ic.ic_intr_evcnt = pcib_isa_intr_evcnt; 269 my_sc->sc_ic.ic_intr_establish = pcib_isa_intr_establish; 270 my_sc->sc_ic.ic_intr_disestablish = pcib_isa_intr_disestablish; 271 my_sc->sc_ic.ic_intr_alloc = pcib_isa_intr_alloc; 272 my_sc->sc_ic.ic_intr_string = pcib_isa_intr_string; 273 274 pcib_ic = &my_sc->sc_ic; /* XXX for external use */ 275 276 /* Initialize our interrupt table. */ 277 for (i = 0; i < ICU_LEN; i++) { 278 #if 0 279 char irqstr[8]; /* 4 + 2 + NULL + sanity */ 280 281 sprintf(irqstr, "irq %d", i); 282 evcnt_attach_dynamic(&my_sc->sc_intrtab[i].intr_count, 283 EVCNT_TYPE_INTR, NULL, "pcib", irqstr); 284 #else 285 evcnt_attach_dynamic(&my_sc->sc_intrtab[i].intr_count, 286 EVCNT_TYPE_INTR, NULL, "pcib", isa_intrnames[i]); 287 #endif 288 LIST_INIT(&my_sc->sc_intrtab[i].intr_q); 289 my_sc->sc_intrtab[i].intr_type = IST_NONE; 290 } 291 292 /* Hook up our interrupt handler. */ 293 my_sc->sc_ih = evbmips_intr_establish(MALTA_SOUTHBRIDGE_INTR, pcib_intr, my_sc); 294 if (my_sc->sc_ih == NULL) 295 printf("%s: WARNING: unable to register interrupt handler\n", 296 my_sc->sc_dev.dv_xname); 297 298 299 /* 300 * Disable ISA interrupts before returning to YAMON. 301 */ 302 if (shutdownhook_establish(pcib_cleanup, my_sc) == NULL) 303 panic("pcib_attach: could not establish shutdown hook"); 304 305 config_defer(self, pcib_bridge_callback); 306 } 307 308 static void 309 pcib_bridge_callback(struct device *self) 310 { 311 struct pcib_softc *sc = (void *)self; 312 struct malta_config *mcp = &malta_configuration; 313 struct isabus_attach_args iba; 314 315 /* 316 * Attach the ISA bus behind this bridge. 317 */ 318 memset(&iba, 0, sizeof(iba)); 319 320 iba.iba_busname = "isa"; 321 iba.iba_iot = &mcp->mc_iot; 322 iba.iba_memt = &mcp->mc_memt; 323 iba.iba_dmat = &mcp->mc_isa_dmat; 324 325 iba.iba_ic = &sc->sc_ic; 326 iba.iba_ic->ic_attach_hook = pcib_isa_attach_hook; 327 328 config_found(&sc->sc_dev, &iba, pcib_print); 329 } 330 331 static int 332 pcib_print(void *aux, const char *pnp) 333 { 334 335 /* Only ISAs can attach to pcib's; easy. */ 336 if (pnp) 337 printf("isa at %s", pnp); 338 return (UNCONF); 339 } 340 341 static void 342 pcib_isa_attach_hook(struct device *parent, struct device *self, 343 struct isabus_attach_args *iba) 344 { 345 346 /* Nothing to do. */ 347 } 348 349 static void 350 pcib_set_icus(struct pcib_softc *sc) 351 { 352 353 /* Enable the cascade IRQ (2) if 8-15 is enabled. */ 354 if ((sc->sc_imask & 0xff00) != 0xff00) 355 sc->sc_imask &= ~(1U << 2); 356 else 357 sc->sc_imask |= (1U << 2); 358 359 bus_space_write_1(sc->sc_iot, sc->sc_ioh_icu1, PIC_OCW1, 360 sc->sc_imask & 0xff); 361 bus_space_write_1(sc->sc_iot, sc->sc_ioh_icu2, PIC_OCW1, 362 (sc->sc_imask >> 8) & 0xff); 363 364 bus_space_write_1(sc->sc_iot, sc->sc_ioh_elcr, 0, 365 sc->sc_elcr & 0xff); 366 bus_space_write_1(sc->sc_iot, sc->sc_ioh_elcr, 1, 367 (sc->sc_elcr >> 8) & 0xff); 368 } 369 370 static int 371 pcib_intr(void *v) 372 { 373 struct pcib_softc *sc = v; 374 struct evbmips_intrhand *ih; 375 int irq; 376 377 for (;;) { 378 #if 1 379 bus_space_write_1(sc->sc_iot, sc->sc_ioh_icu1, PIC_OCW3, 380 OCW3_SELECT | OCW3_POLL); 381 irq = bus_space_read_1(sc->sc_iot, sc->sc_ioh_icu1, PIC_OCW3); 382 if ((irq & OCW3_POLL_PENDING) == 0) 383 return (1); 384 385 irq = OCW3_POLL_IRQ(irq); 386 387 if (irq == 2) { 388 bus_space_write_1(sc->sc_iot, sc->sc_ioh_icu2, 389 PIC_OCW3, OCW3_SELECT | OCW3_POLL); 390 irq = bus_space_read_1(sc->sc_iot, sc->sc_ioh_icu2, 391 PIC_OCW3); 392 if (irq & OCW3_POLL_PENDING) 393 irq = OCW3_POLL_IRQ(irq) + 8; 394 else 395 irq = 2; 396 } 397 #else 398 /* XXX - should be a function call to gt.c? */ 399 irq = GT_REGVAL(GT_PCI0_INTR_ACK) & 0xff; 400 401 /* 402 * From YAMON source code: 403 * 404 * IRQ7 is used to detect spurious interrupts. 405 * The interrupt acknowledge cycle returns IRQ7, if no 406 * interrupts is requested. 407 * We can differentiate between this situation and a 408 * "Normal" IRQ7 by reading the ISR. 409 */ 410 411 if (irq == 7) { 412 int reg; 413 414 bus_space_write_1(sc->sc_iot, sc->sc_ioh_icu1, PIC_OCW3, 415 OCW3_SELECT | OCW3_RR | OCW3_RIS); 416 reg = bus_space_read_1(sc->sc_iot, sc->sc_ioh_icu1, 417 PIC_OCW3); 418 if (!(reg & (1 << 7))) 419 break; /* spurious interrupt */ 420 } 421 #endif 422 423 sc->sc_intrtab[irq].intr_count.ev_count++; 424 LIST_FOREACH(ih, &sc->sc_intrtab[irq].intr_q, ih_q) 425 (*ih->ih_func)(ih->ih_arg); 426 427 /* Send a specific EOI to the 8259. */ 428 if (irq > 7) { 429 bus_space_write_1(sc->sc_iot, sc->sc_ioh_icu2, 430 PIC_OCW2, OCW2_SELECT | OCW3_EOI | OCW3_SL | 431 OCW2_ILS(irq & 7)); 432 irq = 2; 433 } 434 435 bus_space_write_1(sc->sc_iot, sc->sc_ioh_icu1, PIC_OCW2, 436 OCW2_SELECT | OCW3_EOI | OCW3_SL | OCW2_ILS(irq)); 437 } 438 } 439 440 const char * 441 pcib_isa_intr_string(void *v, int irq) 442 { 443 static char irqstr[12]; /* 8 + 2 + NULL + sanity */ 444 445 if (irq == 0 || irq >= ICU_LEN || irq == 2) 446 panic("pcib_isa_intr_string: bogus isa irq 0x%x", irq); 447 448 sprintf(irqstr, "isa irq %d", irq); 449 return (irqstr); 450 } 451 452 const struct evcnt * 453 pcib_isa_intr_evcnt(void *v, int irq) 454 { 455 456 if (irq == 0 || irq >= ICU_LEN || irq == 2) 457 panic("pcib_isa_intr_evcnt: bogus isa irq 0x%x", irq); 458 459 return (&my_sc->sc_intrtab[irq].intr_count); 460 } 461 462 void * 463 pcib_isa_intr_establish(void *v, int irq, int type, int level, 464 int (*func)(void *), void *arg) 465 { 466 struct evbmips_intrhand *ih; 467 int s; 468 469 if (irq >= ICU_LEN || irq == 2 || type == IST_NONE) 470 panic("pcib_isa_intr_establish: bad irq or type"); 471 472 switch (my_sc->sc_intrtab[irq].intr_type) { 473 case IST_NONE: 474 my_sc->sc_intrtab[irq].intr_type = type; 475 break; 476 477 case IST_EDGE: 478 case IST_LEVEL: 479 if (type == my_sc->sc_intrtab[irq].intr_type) 480 break; 481 /* FALLTHROUGH */ 482 case IST_PULSE: 483 /* 484 * We can't share interrupts in this case. 485 */ 486 return (NULL); 487 } 488 489 ih = malloc(sizeof(*ih), M_DEVBUF, M_NOWAIT); 490 if (ih == NULL) 491 return (NULL); 492 493 ih->ih_func = func; 494 ih->ih_arg = arg; 495 ih->ih_irq = irq; 496 497 s = splhigh(); 498 499 /* Insert the handler into the table. */ 500 LIST_INSERT_HEAD(&my_sc->sc_intrtab[irq].intr_q, ih, ih_q); 501 my_sc->sc_intrtab[irq].intr_type = type; 502 503 /* Enable it, set trigger mode. */ 504 my_sc->sc_imask &= ~(1 << irq); 505 if (my_sc->sc_intrtab[irq].intr_type == IST_LEVEL) 506 my_sc->sc_elcr |= (1 << irq); 507 else 508 my_sc->sc_elcr &= ~(1 << irq); 509 510 pcib_set_icus(my_sc); 511 512 splx(s); 513 514 return (ih); 515 } 516 517 void 518 pcib_isa_intr_disestablish(void *v, void *arg) 519 { 520 struct evbmips_intrhand *ih = arg; 521 int s; 522 523 s = splhigh(); 524 525 LIST_REMOVE(ih, ih_q); 526 527 /* If there are no more handlers on this IRQ, disable it. */ 528 if (LIST_FIRST(&my_sc->sc_intrtab[ih->ih_irq].intr_q) == NULL) { 529 my_sc->sc_imask |= (1 << ih->ih_irq); 530 pcib_set_icus(my_sc); 531 } 532 533 splx(s); 534 535 free(ih, M_DEVBUF); 536 } 537 538 static int 539 pcib_isa_intr_alloc(void *v, int mask, int type, int *irq) 540 { 541 int i, tmp, bestirq, count; 542 struct evbmips_intrhand *ih; 543 544 if (type == IST_NONE) 545 panic("pcib_intr_alloc: bogus type"); 546 547 bestirq = -1; 548 count = -1; 549 550 mask &= ~my_sc->sc_reserved; 551 552 for (i = 0; i < ICU_LEN; i++) { 553 if ((mask & (1 << i)) == 0) 554 continue; 555 556 switch (my_sc->sc_intrtab[i].intr_type) { 557 case IST_NONE: 558 /* 559 * If nothing's using the IRQ, just return it. 560 */ 561 *irq = i; 562 return (0); 563 564 case IST_EDGE: 565 case IST_LEVEL: 566 if (type != my_sc->sc_intrtab[i].intr_type) 567 continue; 568 /* 569 * If the IRQ is sharable, count the number of 570 * other handlers, and if it's smaller than the 571 * last IRQ like this, remember it. 572 */ 573 tmp = 0; 574 for (ih = LIST_FIRST(&my_sc->sc_intrtab[i].intr_q); 575 ih != NULL; ih = LIST_NEXT(ih, ih_q)) 576 tmp++; 577 if (bestirq == -1 || count > tmp) { 578 bestirq = i; 579 count = tmp; 580 } 581 break; 582 583 case IST_PULSE: 584 /* This just isn't sharable. */ 585 continue; 586 } 587 } 588 589 if (bestirq == -1) 590 return (1); 591 592 *irq = bestirq; 593 return (0); 594 } 595 596 static void 597 pcib_cleanup(void *arg) 598 { 599 600 my_sc->sc_imask = 0xffff; 601 pcib_set_icus(my_sc); 602 } 603
Indexes created Tue Sep 30 20:09:53 GMT 2025