11.1Ssimonb/* $NetBSD: if_mipsnetreg.h,v 1.1 2021/01/27 05:24:16 simonb Exp $ */ 21.1Ssimonb 31.1Ssimonb/*- 41.1Ssimonb * Copyright (c) 2021 The NetBSD Foundation, Inc. 51.1Ssimonb * All rights reserved. 61.1Ssimonb * 71.1Ssimonb * This code is derived from software contributed to The NetBSD Foundation 81.1Ssimonb * by Simon Burge. 91.1Ssimonb * 101.1Ssimonb * Redistribution and use in source and binary forms, with or without 111.1Ssimonb * modification, are permitted provided that the following conditions 121.1Ssimonb * are met: 131.1Ssimonb * 1. Redistributions of source code must retain the above copyright 141.1Ssimonb * notice, this list of conditions and the following disclaimer. 151.1Ssimonb * 2. Redistributions in binary form must reproduce the above copyright 161.1Ssimonb * notice, this list of conditions and the following disclaimer in the 171.1Ssimonb * documentation and/or other materials provided with the distribution. 181.1Ssimonb * 191.1Ssimonb * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 201.1Ssimonb * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 211.1Ssimonb * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 221.1Ssimonb * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 231.1Ssimonb * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 241.1Ssimonb * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 251.1Ssimonb * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 261.1Ssimonb * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 271.1Ssimonb * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 281.1Ssimonb * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 291.1Ssimonb * POSSIBILITY OF SUCH DAMAGE. 301.1Ssimonb */ 311.1Ssimonb 321.1Ssimonb/* 331.1Ssimonb * MIPSSIM emulator MIPSNET ethernet registers 341.1Ssimonb */ 351.1Ssimonb 361.1Ssimonb#define MN_DEVID0 0x00 /* device info */ 371.1Ssimonb#define MN_DEVID1 0x00 /* device info */ 381.1Ssimonb#define MN_BUSY 0x08 /* rx/tx in progress */ 391.1Ssimonb#define MN_RXDATACOUNT 0x0c /* bytes in rx data buffer */ 401.1Ssimonb#define MN_TXDATACOUNT 0x10 /* bytes for tx data buffer */ 411.1Ssimonb#define MN_INTR 0x14 /* interrupt control */ 421.1Ssimonb#define MN_INTR_TXDONE __BIT(0) /* tx done interrupt */ 431.1Ssimonb#define MN_INTR_RXDONE __BIT(1) /* rx data available interrupt */ 441.1Ssimonb#define MN_INTR_TEST __BIT(31) /* interrupt test */ 451.1Ssimonb#define MN_INTRINFO 0x18 /* core-specific interrupt info */ 461.1Ssimonb#define MN_RXDATA 0x1c /* rx data fifo */ 471.1Ssimonb#define MN_TXDATA 0x20 /* tx data fifo */ 481.1Ssimonb 491.1Ssimonb#define MN_NPORTS 0x24 /* size to map for registers */ 501.1Ssimonb 511.1Ssimonb#define MN_MAXDATA 32768 /* largest transfer size */ 521.1Ssimonb 531.1Ssimonb#define MIPSNET_DEVID0 0x4d495053 /* ascii "MIPS" */ 541.1Ssimonb#define MIPSNET_DEVID1 0x4e455430 /* ascii "NET0" */ 55