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mipssimreg.h revision 1.2 
      1 /* $NetBSD: mipssimreg.h,v 1.2 2021/02/15 22:39:46 reinoud Exp $ */
      2 
      3 /*-
      4  * Copyright (c) 2021 The NetBSD Foundation, Inc.
      5  * All rights reserved.
      6  *
      7  * This code is derived from software contributed to The NetBSD Foundation
      8  * by Simon Burge.
      9  *
     10  * Redistribution and use in source and binary forms, with or without
     11  * modification, are permitted provided that the following conditions
     12  * are met:
     13  * 1. Redistributions of source code must retain the above copyright
     14  *    notice, this list of conditions and the following disclaimer.
     15  * 2. Redistributions in binary form must reproduce the above copyright
     16  *    notice, this list of conditions and the following disclaimer in the
     17  *    documentation and/or other materials provided with the distribution.
     18  *
     19  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
     20  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
     21  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
     22  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
     23  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
     24  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
     25  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
     26  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
     27  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
     28  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
     29  * POSSIBILITY OF SUCH DAMAGE.
     30  */
     31 
     32 
     33 /*
     34  *	Memory Map
     35  *
     36  *	0000.0000	128MB	RAM (max ~500MB)
     37  *	1fd0.0000	 64kB	ISA IO space
     38  *	1fd1.0000	 64kB	'ISA' VirtIO IO space (non standard)
     39  *
     40  *	CPU interrupts
     41  *
     42  *	 0	mipsnet
     43  *	 1	virtio
     44  *	 2	16450 UART
     45  */
     46 
     47 #define	MIPSSIM_UART0_ADDR	0x003f8
     48 #define	MIPSSIM_MIPSNET0_ADDR	0x04200
     49 #define MIPSSIM_VIRTIO_ADDR	0x10000
     50 
     51 #define	MIPSSIM_ISA_IO_BASE	0x1fd00000  /* ISA IO memory:	*/
     52 #define	MIPSSIM_ISA_IO_SIZE	0x00010000  /*    64 kByte	*/
     53 #define MIPSSIM_VIRTIO_IO_SIZE	0x00010000  /*    64 kByte      */
     54 
     55 #define MIPSSIM_DMA_BASE	0x00000000
     56 #define MIPSSIM_DMA_PHYSBASE	0x00000000
     57 #define MIPSSIM_DMA_SIZE	(MIPSSIM_ISA_IO_BASE - MIPSSIM_DMA_BASE)
     58 
     59 #define VIRTIO_NUM_TRANSPORTS	32
     60 #define VIRTIO_STRIDE		512
     61 
     62