Home | History | Annotate | Line # | Download | only in rasoc
      1  1.6      ryo /*	$NetBSD: autoconf.c,v 1.6 2016/10/05 15:54:58 ryo Exp $	*/
      2  1.2     matt /*-
      3  1.2     matt  * Copyright (c) 2011 CradlePoint Technology, Inc.
      4  1.2     matt  * All rights reserved.
      5  1.2     matt  *
      6  1.2     matt  *
      7  1.2     matt  * Redistribution and use in source and binary forms, with or without
      8  1.2     matt  * modification, are permitted provided that the following conditions
      9  1.2     matt  * are met:
     10  1.2     matt  * 1. Redistributions of source code must retain the above copyright
     11  1.2     matt  *    notice, this list of conditions and the following disclaimer.
     12  1.2     matt  * 2. Redistributions in binary form must reproduce the above copyright
     13  1.2     matt  *    notice, this list of conditions and the following disclaimer in the
     14  1.2     matt  *    documentation and/or other materials provided with the distribution.
     15  1.2     matt  *
     16  1.2     matt  * THIS SOFTWARE IS PROVIDED BY CRADLEPOINT TECHNOLOGY, INC. AND CONTRIBUTORS
     17  1.2     matt  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
     18  1.2     matt  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
     19  1.2     matt  * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS
     20  1.2     matt  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
     21  1.2     matt  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
     22  1.2     matt  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
     23  1.2     matt  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
     24  1.2     matt  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
     25  1.2     matt  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
     26  1.2     matt  * POSSIBILITY OF SUCH DAMAGE.
     27  1.2     matt  */
     28  1.2     matt 
     29  1.2     matt #include <sys/cdefs.h>
     30  1.6      ryo __KERNEL_RCSID(0, "$NetBSD: autoconf.c,v 1.6 2016/10/05 15:54:58 ryo Exp $");
     31  1.2     matt 
     32  1.2     matt #include <sys/param.h>
     33  1.2     matt #include <sys/bus.h>
     34  1.2     matt #include <sys/conf.h>
     35  1.2     matt #include <sys/device.h>
     36  1.2     matt #include <sys/systm.h>
     37  1.2     matt 
     38  1.5     matt #include <mips/ralink/ralink_reg.h>
     39  1.5     matt #include <mips/ralink/ralink_var.h>
     40  1.5     matt 
     41  1.2     matt /*
     42  1.2     matt  * Configure all devices on system
     43  1.2     matt  */
     44  1.2     matt void
     45  1.2     matt cpu_configure(void)
     46  1.2     matt {
     47  1.2     matt 	intr_init();
     48  1.2     matt 
     49  1.2     matt 	/* Kick off autoconfiguration. */
     50  1.2     matt 	if (config_rootfound("mainbus", NULL) == NULL)
     51  1.2     matt 		panic("no mainbus found");
     52  1.2     matt 
     53  1.2     matt 	/*
     54  1.2     matt 	 * Hardware interrupts will be enabled in
     55  1.2     matt 	 * sys/arch/mips/mips/mips3_clockintr.c:mips3_initclocks()
     56  1.2     matt 	 * to avoid hardclock(9) by CPU INT5 before softclockintr is
     57  1.2     matt 	 * initialized in initclocks().
     58  1.2     matt 	 */
     59  1.2     matt }
     60  1.2     matt 
     61  1.2     matt void
     62  1.2     matt cpu_rootconf(void)
     63  1.2     matt {
     64  1.3  mlelstv 	rootconf();
     65  1.2     matt }
     66  1.2     matt 
     67  1.5     matt static const struct cfg_info {
     68  1.5     matt 	const char *map_name;
     69  1.5     matt 	uint32_t map_rst;
     70  1.5     matt 	uint32_t map_clkcfg1;
     71  1.5     matt } map_info[] = {
     72  1.6      ryo #if defined(MT7628)
     73  1.6      ryo 	{ "rpci", RST_PCIE0_7620, SYSCTL_CLKCFG1_PCIE_CLK_EN_7620 },
     74  1.6      ryo 	{ "ohci", RST_UHST0_7620|RST_UHST,
     75  1.6      ryo 	    SYSCTL_CLKCFG1_UPHY0_CLK_EN_7620|SYSCTL_CLKCFG1_UPHY0_CLK_EN_7628 },
     76  1.6      ryo 	{ "ehci", RST_UHST0_7620|RST_UHST,
     77  1.6      ryo 	    SYSCTL_CLKCFG1_UPHY0_CLK_EN_7620|SYSCTL_CLKCFG1_UPHY0_CLK_EN_7628 },
     78  1.6      ryo 	{ "sdhc", RST_SDHC_7620, SYSCTL_CLKCFG1_SDHC_CLK_EN },
     79  1.6      ryo 	{ "rsw", RST_ESW_7620, SYSCTL_CLKCFG1_ESW_CLK_EN },
     80  1.6      ryo #endif
     81  1.5     matt #if defined(MT7620)
     82  1.5     matt 	{ "rpci", RST_PCIE0_7620, SYSCTL_CLKCFG1_PCIE_CLK_EN_7620 },
     83  1.5     matt 	{ "ohci", RST_UHST0_7620|RST_UHST, SYSCTL_CLKCFG1_UPHY0_CLK_EN_7620 },
     84  1.5     matt 	{ "ehci", RST_UHST0_7620|RST_UHST, SYSCTL_CLKCFG1_UPHY0_CLK_EN_7620 },
     85  1.5     matt 	{ "sdhc", RST_SDHC_7620, SYSCTL_CLKCFG1_SDHC_CLK_EN },
     86  1.5     matt 	{ "rsw", RST_ESW_7620, SYSCTL_CLKCFG1_ESW_CLK_EN },
     87  1.5     matt #endif
     88  1.5     matt #if defined(RT3883)
     89  1.5     matt 	{ "rpci", RST_PCI_3883 | RST_PCIPCIE_3883,
     90  1.5     matt 	    SYSCTL_CLKCFG1_PCI_CLK_EN|SYSCTL_CLKCFG1_PCIE_CLK_EN_3883 },
     91  1.5     matt 	{ "ohci", RST_UHST, SYSCTL_CLKCFG1_UPHY0_CLK_EN_3883 },
     92  1.5     matt 	{ "ehci", RST_UHST, SYSCTL_CLKCFG1_UPHY0_CLK_EN_3883 },
     93  1.5     matt #endif
     94  1.5     matt };
     95  1.5     matt 
     96  1.5     matt static void
     97  1.5     matt ra_device_fixup(bus_space_tag_t bst, const struct cfg_info *map)
     98  1.5     matt {
     99  1.5     matt 	const uint32_t clkcfg1 = bus_space_read_4(bst, ra_sysctl_bsh,
    100  1.5     matt 	    RA_SYSCTL_CLKCFG1);
    101  1.5     matt 	if ((clkcfg1 & map->map_clkcfg1) != map->map_clkcfg1) {
    102  1.5     matt 		bus_space_write_4(bst, ra_sysctl_bsh, RA_SYSCTL_CLKCFG1,
    103  1.5     matt 		    clkcfg1 | map->map_clkcfg1);
    104  1.5     matt 		delay(10000);
    105  1.5     matt 	}
    106  1.5     matt 
    107  1.5     matt 	const uint32_t rst = bus_space_read_4(bst, ra_sysctl_bsh,
    108  1.5     matt 	    RA_SYSCTL_RST);
    109  1.5     matt 	if ((rst & map->map_rst) != 0) {
    110  1.5     matt 		bus_space_write_4(bst, ra_sysctl_bsh, RA_SYSCTL_RST,
    111  1.5     matt 		    rst & ~map->map_rst);
    112  1.5     matt 		delay(10000);
    113  1.5     matt 	}
    114  1.5     matt }
    115  1.5     matt 
    116  1.2     matt void
    117  1.5     matt device_register(device_t self, void *aux)
    118  1.2     matt {
    119  1.5     matt 	device_t parent = device_parent(self);
    120  1.5     matt 
    121  1.5     matt 	if (parent != NULL && device_is_a(parent, "mainbus")) {
    122  1.5     matt 		// If we are attaching a mainbus device, see if we know how
    123  1.5     matt 		// to bring it out of reset.
    124  1.5     matt 		struct mainbus_attach_args * const ma = aux;
    125  1.5     matt 		for (const struct cfg_info *map = map_info;
    126  1.5     matt 		     map < map_info + __arraycount(map_info);
    127  1.5     matt 		     map++) {
    128  1.5     matt 			if (device_is_a(self, map->map_name)) {
    129  1.5     matt 				ra_device_fixup(ma->ma_memt, map);
    130  1.5     matt 				delay(1000);
    131  1.5     matt 				break;
    132  1.5     matt 			}
    133  1.5     matt 		}
    134  1.5     matt 
    135  1.5     matt #if defined(RT3883) || defined(MT7620)
    136  1.5     matt 		if (device_is_a(self, "ohci") || device_is_a(self, "ehci")) {
    137  1.5     matt 			const uint32_t cfg1 = bus_space_read_4(ma->ma_memt,
    138  1.5     matt 			    ra_sysctl_bsh, RA_SYSCTL_CFG1);
    139  1.5     matt 			if ((cfg1 & SYSCTL_CFG1_USB0_HOST_MODE) == 0) {
    140  1.5     matt 				bus_space_write_4(ma->ma_memt, ra_sysctl_bsh,
    141  1.5     matt 				    RA_SYSCTL_CFG1,
    142  1.5     matt 				    cfg1 | SYSCTL_CFG1_USB0_HOST_MODE);
    143  1.5     matt 				delay(10);
    144  1.5     matt 			}
    145  1.5     matt 		}
    146  1.5     matt #endif
    147  1.5     matt 	}
    148  1.2     matt }
    149