autoconf.c revision 1.3.2.3
1 1.3.2.2 tls /* $NetBSD: autoconf.c,v 1.3.2.3 2017/12/03 11:36:10 jdolecek Exp $ */ 2 1.2 matt /*- 3 1.2 matt * Copyright (c) 2011 CradlePoint Technology, Inc. 4 1.2 matt * All rights reserved. 5 1.2 matt * 6 1.2 matt * 7 1.2 matt * Redistribution and use in source and binary forms, with or without 8 1.2 matt * modification, are permitted provided that the following conditions 9 1.2 matt * are met: 10 1.2 matt * 1. Redistributions of source code must retain the above copyright 11 1.2 matt * notice, this list of conditions and the following disclaimer. 12 1.2 matt * 2. Redistributions in binary form must reproduce the above copyright 13 1.2 matt * notice, this list of conditions and the following disclaimer in the 14 1.2 matt * documentation and/or other materials provided with the distribution. 15 1.2 matt * 16 1.2 matt * THIS SOFTWARE IS PROVIDED BY CRADLEPOINT TECHNOLOGY, INC. AND CONTRIBUTORS 17 1.2 matt * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 18 1.2 matt * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 1.2 matt * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS 20 1.2 matt * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 1.2 matt * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 1.2 matt * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 1.2 matt * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 1.2 matt * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 1.2 matt * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 1.2 matt * POSSIBILITY OF SUCH DAMAGE. 27 1.2 matt */ 28 1.2 matt 29 1.2 matt #include <sys/cdefs.h> 30 1.3.2.2 tls __KERNEL_RCSID(0, "$NetBSD: autoconf.c,v 1.3.2.3 2017/12/03 11:36:10 jdolecek Exp $"); 31 1.2 matt 32 1.2 matt #include <sys/param.h> 33 1.2 matt #include <sys/bus.h> 34 1.2 matt #include <sys/conf.h> 35 1.2 matt #include <sys/device.h> 36 1.2 matt #include <sys/systm.h> 37 1.2 matt 38 1.3.2.2 tls #include <mips/ralink/ralink_reg.h> 39 1.3.2.2 tls #include <mips/ralink/ralink_var.h> 40 1.3.2.2 tls 41 1.2 matt /* 42 1.2 matt * Configure all devices on system 43 1.2 matt */ 44 1.2 matt void 45 1.2 matt cpu_configure(void) 46 1.2 matt { 47 1.2 matt intr_init(); 48 1.2 matt 49 1.2 matt /* Kick off autoconfiguration. */ 50 1.2 matt if (config_rootfound("mainbus", NULL) == NULL) 51 1.2 matt panic("no mainbus found"); 52 1.2 matt 53 1.2 matt /* 54 1.2 matt * Hardware interrupts will be enabled in 55 1.2 matt * sys/arch/mips/mips/mips3_clockintr.c:mips3_initclocks() 56 1.2 matt * to avoid hardclock(9) by CPU INT5 before softclockintr is 57 1.2 matt * initialized in initclocks(). 58 1.2 matt */ 59 1.2 matt } 60 1.2 matt 61 1.2 matt void 62 1.2 matt cpu_rootconf(void) 63 1.2 matt { 64 1.3 mlelstv rootconf(); 65 1.2 matt } 66 1.2 matt 67 1.3.2.2 tls static const struct cfg_info { 68 1.3.2.2 tls const char *map_name; 69 1.3.2.2 tls uint32_t map_rst; 70 1.3.2.2 tls uint32_t map_clkcfg1; 71 1.3.2.2 tls } map_info[] = { 72 1.3.2.3 jdolecek #if defined(MT7628) 73 1.3.2.3 jdolecek { "rpci", RST_PCIE0_7620, SYSCTL_CLKCFG1_PCIE_CLK_EN_7620 }, 74 1.3.2.3 jdolecek { "ohci", RST_UHST0_7620|RST_UHST, 75 1.3.2.3 jdolecek SYSCTL_CLKCFG1_UPHY0_CLK_EN_7620|SYSCTL_CLKCFG1_UPHY0_CLK_EN_7628 }, 76 1.3.2.3 jdolecek { "ehci", RST_UHST0_7620|RST_UHST, 77 1.3.2.3 jdolecek SYSCTL_CLKCFG1_UPHY0_CLK_EN_7620|SYSCTL_CLKCFG1_UPHY0_CLK_EN_7628 }, 78 1.3.2.3 jdolecek { "sdhc", RST_SDHC_7620, SYSCTL_CLKCFG1_SDHC_CLK_EN }, 79 1.3.2.3 jdolecek { "rsw", RST_ESW_7620, SYSCTL_CLKCFG1_ESW_CLK_EN }, 80 1.3.2.3 jdolecek #endif 81 1.3.2.2 tls #if defined(MT7620) 82 1.3.2.2 tls { "rpci", RST_PCIE0_7620, SYSCTL_CLKCFG1_PCIE_CLK_EN_7620 }, 83 1.3.2.2 tls { "ohci", RST_UHST0_7620|RST_UHST, SYSCTL_CLKCFG1_UPHY0_CLK_EN_7620 }, 84 1.3.2.2 tls { "ehci", RST_UHST0_7620|RST_UHST, SYSCTL_CLKCFG1_UPHY0_CLK_EN_7620 }, 85 1.3.2.2 tls { "sdhc", RST_SDHC_7620, SYSCTL_CLKCFG1_SDHC_CLK_EN }, 86 1.3.2.2 tls { "rsw", RST_ESW_7620, SYSCTL_CLKCFG1_ESW_CLK_EN }, 87 1.3.2.2 tls #endif 88 1.3.2.2 tls #if defined(RT3883) 89 1.3.2.2 tls { "rpci", RST_PCI_3883 | RST_PCIPCIE_3883, 90 1.3.2.2 tls SYSCTL_CLKCFG1_PCI_CLK_EN|SYSCTL_CLKCFG1_PCIE_CLK_EN_3883 }, 91 1.3.2.2 tls { "ohci", RST_UHST, SYSCTL_CLKCFG1_UPHY0_CLK_EN_3883 }, 92 1.3.2.2 tls { "ehci", RST_UHST, SYSCTL_CLKCFG1_UPHY0_CLK_EN_3883 }, 93 1.3.2.2 tls #endif 94 1.3.2.2 tls }; 95 1.3.2.2 tls 96 1.3.2.2 tls static void 97 1.3.2.2 tls ra_device_fixup(bus_space_tag_t bst, const struct cfg_info *map) 98 1.3.2.2 tls { 99 1.3.2.2 tls const uint32_t clkcfg1 = bus_space_read_4(bst, ra_sysctl_bsh, 100 1.3.2.2 tls RA_SYSCTL_CLKCFG1); 101 1.3.2.2 tls if ((clkcfg1 & map->map_clkcfg1) != map->map_clkcfg1) { 102 1.3.2.2 tls bus_space_write_4(bst, ra_sysctl_bsh, RA_SYSCTL_CLKCFG1, 103 1.3.2.2 tls clkcfg1 | map->map_clkcfg1); 104 1.3.2.2 tls delay(10000); 105 1.3.2.2 tls } 106 1.3.2.2 tls 107 1.3.2.2 tls const uint32_t rst = bus_space_read_4(bst, ra_sysctl_bsh, 108 1.3.2.2 tls RA_SYSCTL_RST); 109 1.3.2.2 tls if ((rst & map->map_rst) != 0) { 110 1.3.2.2 tls bus_space_write_4(bst, ra_sysctl_bsh, RA_SYSCTL_RST, 111 1.3.2.2 tls rst & ~map->map_rst); 112 1.3.2.2 tls delay(10000); 113 1.3.2.2 tls } 114 1.3.2.2 tls } 115 1.3.2.2 tls 116 1.2 matt void 117 1.3.2.2 tls device_register(device_t self, void *aux) 118 1.2 matt { 119 1.3.2.2 tls device_t parent = device_parent(self); 120 1.3.2.2 tls 121 1.3.2.2 tls if (parent != NULL && device_is_a(parent, "mainbus")) { 122 1.3.2.2 tls // If we are attaching a mainbus device, see if we know how 123 1.3.2.2 tls // to bring it out of reset. 124 1.3.2.2 tls struct mainbus_attach_args * const ma = aux; 125 1.3.2.2 tls for (const struct cfg_info *map = map_info; 126 1.3.2.2 tls map < map_info + __arraycount(map_info); 127 1.3.2.2 tls map++) { 128 1.3.2.2 tls if (device_is_a(self, map->map_name)) { 129 1.3.2.2 tls ra_device_fixup(ma->ma_memt, map); 130 1.3.2.2 tls delay(1000); 131 1.3.2.2 tls break; 132 1.3.2.2 tls } 133 1.3.2.2 tls } 134 1.3.2.2 tls 135 1.3.2.2 tls #if defined(RT3883) || defined(MT7620) 136 1.3.2.2 tls if (device_is_a(self, "ohci") || device_is_a(self, "ehci")) { 137 1.3.2.2 tls const uint32_t cfg1 = bus_space_read_4(ma->ma_memt, 138 1.3.2.2 tls ra_sysctl_bsh, RA_SYSCTL_CFG1); 139 1.3.2.2 tls if ((cfg1 & SYSCTL_CFG1_USB0_HOST_MODE) == 0) { 140 1.3.2.2 tls bus_space_write_4(ma->ma_memt, ra_sysctl_bsh, 141 1.3.2.2 tls RA_SYSCTL_CFG1, 142 1.3.2.2 tls cfg1 | SYSCTL_CFG1_USB0_HOST_MODE); 143 1.3.2.2 tls delay(10); 144 1.3.2.2 tls } 145 1.3.2.2 tls } 146 1.3.2.2 tls #endif 147 1.3.2.2 tls } 148 1.2 matt } 149
Indexes created Sat Oct 11 16:09:52 GMT 2025